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-rw-r--r--bench/tb_core_full_1024.v296
-rw-r--r--bench/tb_core_full_512.v6
-rw-r--r--bench/tb_wrapper.v23
3 files changed, 209 insertions, 116 deletions
diff --git a/bench/tb_core_full_1024.v b/bench/tb_core_full_1024.v
index e6b1a66..87eac79 100644
--- a/bench/tb_core_full_1024.v
+++ b/bench/tb_core_full_1024.v
@@ -31,6 +31,7 @@ module tb_core_full_1024;
reg [31:0] Q_FACTOR[0:TB_NUM_WORDS_PQ-1];
reg [31:0] P_COEFF[0:TB_NUM_WORDS_PQ];
reg [31:0] Q_COEFF[0:TB_NUM_WORDS_PQ];
+ reg [31:0] D[0:TB_NUM_WORDS_N-1];
reg [31:0] DP[0:TB_NUM_WORDS_PQ-1];
reg [31:0] DQ[0:TB_NUM_WORDS_PQ-1];
reg [31:0] QINV[0:TB_NUM_WORDS_PQ-1];
@@ -117,6 +118,14 @@ module tb_core_full_1024;
Q_COEFF[ 8] = 32'h0cf1175c; Q_COEFF[ 9] = 32'h4911b74e; Q_COEFF[ 10] = 32'h331e61cb; Q_COEFF[ 11] = 32'he9527ead;
Q_COEFF[ 12] = 32'h8d6a5911; Q_COEFF[ 13] = 32'hae42d654; Q_COEFF[ 14] = 32'he10d29a8; Q_COEFF[ 15] = 32'h50a5dd76;
Q_COEFF[ 16] = 32'h0000ed75;
+ D[ 0] = 32'h6d4e7831; D[ 1] = 32'ha96f72d6; D[ 2] = 32'h3b47788f; D[ 3] = 32'h07207984;
+ D[ 4] = 32'h3247b99f; D[ 5] = 32'hfe6ade84; D[ 6] = 32'h0e0fdec4; D[ 7] = 32'hc31450bd;
+ D[ 8] = 32'hb8624e9a; D[ 9] = 32'h362966c6; D[ 10] = 32'h4d8a15bf; D[ 11] = 32'h845b6e48;
+ D[ 12] = 32'h0b2259bf; D[ 13] = 32'h793bfff7; D[ 14] = 32'h28eeceb0; D[ 15] = 32'h8d6fde7f;
+ D[ 16] = 32'h0d618632; D[ 17] = 32'hfb371e4b; D[ 18] = 32'h0b80a9a0; D[ 19] = 32'h5c1a1381;
+ D[ 20] = 32'h8dfe755c; D[ 21] = 32'h82564b31; D[ 22] = 32'heee93cbd; D[ 23] = 32'h22bb686e;
+ D[ 24] = 32'hf2ccae97; D[ 25] = 32'he3400736; D[ 26] = 32'h11c4a85e; D[ 27] = 32'ha0c904d0;
+ D[ 28] = 32'hb495cecf; D[ 29] = 32'h32ceb818; D[ 30] = 32'ha2e46c28; D[ 31] = 32'h6915229e;
DP[ 0] = 32'h63d165e5; DP[ 1] = 32'h856ac81e; DP[ 2] = 32'hc4b8779d; DP[ 3] = 32'h8b119544;
DP[ 4] = 32'had780837; DP[ 5] = 32'h3e920266; DP[ 6] = 32'he9d10f2e; DP[ 7] = 32'h7c1b42b2;
DP[ 8] = 32'hc7daca3b; DP[ 9] = 32'h7883be11; DP[ 10] = 32'ha384548d; DP[ 11] = 32'he0848b23;
@@ -124,7 +133,8 @@ module tb_core_full_1024;
DQ[ 0] = 32'hd7ffdc71; DQ[ 1] = 32'hed01b8aa; DQ[ 2] = 32'h2f99d3a6; DQ[ 3] = 32'h8ccb4428;
DQ[ 4] = 32'hb1574616; DQ[ 5] = 32'hfc218e36; DQ[ 6] = 32'h4fe24f91; DQ[ 7] = 32'h9c367c42;
DQ[ 8] = 32'h69dfa208; DQ[ 9] = 32'h3ee3de79; DQ[ 10] = 32'h54ded59b; DQ[ 11] = 32'hcb3b487d;
- DQ[ 12] = 32'hbcc0db4e; DQ[ 13] = 32'hb3e6678c; DQ[ 14] = 32'h3d13ec03; DQ[ 15] = 32'h99e0f684; QINV[ 0] = 32'h9a2f0db2; QINV[ 1] = 32'h4a8075a5; QINV[ 2] = 32'hb61201fa; QINV[ 3] = 32'h0e876a42;
+ DQ[ 12] = 32'hbcc0db4e; DQ[ 13] = 32'hb3e6678c; DQ[ 14] = 32'h3d13ec03; DQ[ 15] = 32'h99e0f684;
+ QINV[ 0] = 32'h9a2f0db2; QINV[ 1] = 32'h4a8075a5; QINV[ 2] = 32'hb61201fa; QINV[ 3] = 32'h0e876a42;
QINV[ 4] = 32'h94667476; QINV[ 5] = 32'h7538b796; QINV[ 6] = 32'h8d8dfa35; QINV[ 7] = 32'h689ee4a7;
QINV[ 8] = 32'h6779dd63; QINV[ 9] = 32'he15b6b5e; QINV[ 10] = 32'h8275500c; QINV[ 11] = 32'he4dcd058;
QINV[ 12] = 32'haf54b86c; QINV[ 13] = 32'hba76dc50; QINV[ 14] = 32'h473d0d6d; QINV[ 15] = 32'ha023ba44;
@@ -155,30 +165,50 @@ module tb_core_full_1024;
end
-
//
// Clocks
//
`define CLK_FREQUENCY_MHZ (100.0)
`define CLK_PERIOD_NS (1000.0 / `CLK_FREQUENCY_MHZ)
`define CLK_PERIOD_HALF_NS (0.5 * `CLK_PERIOD_NS)
+ `define CLK_PERIOD_QUARTER_NS (0.5 * `CLK_PERIOD_HALF_NS)
- `define CLK_BUS_FREQUENCY_MHZ (50.0)
+ `define CLK_BUS_FREQUENCY_MHZ (25.0)
`define CLK_BUS_PERIOD_NS (1000.0 / `CLK_BUS_FREQUENCY_MHZ)
`define CLK_BUS_PERIOD_HALF_NS (0.5 * `CLK_BUS_PERIOD_NS)
- reg clk = 1'b1;
- reg clk_bus = 1'b0;
+ reg clk = 1'b1;
+ reg clk_dly = 1'b0;
+ wire clk_idle = clk & clk_dly;
+
+ reg clk_bus = 1'b1;
+ reg clk_bus_dly = 1'b0;
+ wire clk_bus_idle = clk_bus & clk_bus_dly;
+
+ always #`CLK_PERIOD_HALF_NS clk <= ~clk;
+ always #`CLK_BUS_PERIOD_HALF_NS clk_bus <= ~clk_bus;
+
+ always @(clk ) clk_dly <= #(`CLK_PERIOD_HALF_NS - `CLK_PERIOD_QUARTER_NS) clk;
+ always @(clk_bus) clk_bus_dly <= #(`CLK_BUS_PERIOD_HALF_NS - `CLK_PERIOD_QUARTER_NS) clk_bus;
- always #`CLK_PERIOD_HALF_NS clk = ~clk;
- always #`CLK_BUS_PERIOD_HALF_NS clk_bus = ~clk_bus;
+ //
+ // Clock Sync
+ //
+ task sync_clk;
+ while (clk_idle !== 1) _wait_quarter_clk_tick;
+ endtask
+
+ task sync_clk_bus;
+ while (clk_bus_idle !== 1) _wait_quarter_clk_tick;
+ endtask
//
// Reset
//
reg rst = 1'b1;
+ wire rst_n = ~rst;
//
@@ -196,7 +226,6 @@ module tb_core_full_1024;
//
// System Bus
//
- reg bus_ready;
reg bus_cs = 1'b0;
reg bus_we = 1'b0;
reg [11:0] bus_addr;
@@ -216,7 +245,7 @@ module tb_core_full_1024;
.clk (clk),
.clk_bus (clk_bus),
- .rst (rst),
+ .rst_n (rst_n),
.next (core_next),
.valid (core_valid),
@@ -238,66 +267,106 @@ module tb_core_full_1024;
//
- // Routine (Bus)
+ // Bus Init Routine
//
- initial begin
-
- bus_ready = 1'b0;
-
- while (rst) wait_clock_bus_tick;
- wait_clock_bus_ticks(10);
- $display("Core came out of reset.");
-
- set_input_1;
- set_input_2;
-
- wait_clock_bus_ticks(10);
- bus_ready = 1'b1;
-
- end
-
+ task core_set_input;
+ begin
+ core_set_input_1;
+ core_set_input_2;
+ wait_clk_bus_ticks(10);
+ $display("Core input banks written.");
+ end
+ endtask
+
//
- // Routine (Control/Status, Bus)
+ // Script
//
- initial begin
-
- _wait_half_clock_tick;
- wait_clock_ticks(100);
- rst = 1'b0;
-
- while (!bus_ready) wait_clock_tick;
- wait_clock_ticks(10);
- $display("Core input banks written.");
-
- word_index_last_n = CORE_NUM_WORDS_N - 1;
- word_index_last_pq = CORE_NUM_WORDS_PQ - 1;
-
- bit_index_last_n = TB_MODULUS_LENGTH_N - 1;
- bit_index_last_pq = 9; //TB_MODULUS_LENGTH_N / 2 - 1;
-
- core_crt_mode = 1'b1;
-
- core_next = 1'b1;
- wait_clock_tick;
- core_next = 1'b0;
- $display("Pulsed 'next' control signal.");
-
- while (!core_valid) wait_clock_tick;
- wait_clock_ticks(10);
-
- $display("Detected high 'valid' status signal.");
- core_crt_mode = 1'bX;
+ initial main;
+
+
+ //
+ // Main Routine (Control/Status, Bus)
+ //
+ integer i, j, k;
+ task main;
+ begin
- wait_clock_ticks(10);
- get_output;
- wait_clock_ticks(10);
- $display("Core output banks read.");
+ sync_clk; // switch to fast core clock
+ core_reset; // reset core
+ core_set_params; // set parameters (modulus width, exponent length)
- verify;
+ sync_clk_bus; // switch to slow bus clock
+ core_set_input; // write to core input banks
+
+ //sync_clk; // switch to fast core clock
+ //core_set_crt_mode(1); // enable CRT signing
+ //core_pulse_next; // assert 'next' bit for one cycle
+ //core_wait_valid; // wait till 'valid' bit gets asserted
+
+ //sync_clk_bus; // switch to slow bus clock
+ //core_get_output; // read from core output banks
+ //core_verify_output; // check, whether core output matches precomputed known good refrence values
+
+ bit_index_last_n = 16;
+ bus_write(2'd2, BANK_IN_2_D, 7'd0, 32'h00010001);
+
+ sync_clk; // switch to fast core clock
+ core_set_crt_mode(0); // disable CRT signing
+ core_pulse_next; // assert 'next' bit for one cycle
+ core_wait_valid; // wait till 'valid' bit gets asserted
+
+ sync_clk_bus; // switch to slow bus clock
+ core_get_output; // read from core output banks
+ core_verify_output; // check, whether core output matches precomputed known good refrence values
+ end
+ endtask
- end
+ task core_reset;
+ begin
+ wait_clk_ticks(100);
+ rst = 1'b0;
+ wait_clk_ticks(10);
+ $display("Core reset finished.");
+ end
+ endtask
+
+ task core_set_params;
+ begin
+ word_index_last_n = CORE_NUM_WORDS_N - 1;
+ word_index_last_pq = CORE_NUM_WORDS_PQ - 1;
+ bit_index_last_n = TB_MODULUS_LENGTH_N - 1;
+ bit_index_last_pq = TB_MODULUS_LENGTH_N / 2 - 1;
+ $display("Core parameters set.");
+ end
+ endtask
+
+ task core_set_crt_mode;
+ input _crt;
+ begin
+ core_crt_mode = _crt;
+ if (_crt) $display("Enabled CRT mode.");
+ else $display("Disabled CRT mode.");
+ end
+ endtask
+
+ task core_pulse_next;
+ begin
+ core_next = 1'b1;
+ wait_clk_tick;
+ core_next = 1'b0;
+ $display("Pulsed core 'next' control signal.");
+ end
+ endtask
+
+ task core_wait_valid;
+ begin
+ while (!core_valid) wait_clk_tick;
+ wait_clk_ticks(10);
+ $display("Detected high core 'valid' status signal.");
+ end
+ endtask
//
@@ -307,58 +376,60 @@ module tb_core_full_1024;
//
- // set_input_1;
+ // core_set_input_1
//
- task set_input_1;
+ task core_set_input_1;
reg [9:0] _tn;
begin
_tn = BANK_IN_1_N_COEFF * 2 ** BUS_OP_ADDR_W + TB_NUM_WORDS_N; // trick to write extra trailer word
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_M, _w[6:0], M[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_N, _w[6:0], N[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_N_FACTOR, _w[6:0], N_FACTOR[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_N_COEFF, _w[6:0], N_COEFF[_w]);
- bus_write(2'd0, _tn[9:7], _tn[6:0], N_COEFF[TB_NUM_WORDS_N]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_X, _w[6:0], X[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_Y, _w[6:0], Y[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_M, _w[6:0], M[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_N, _w[6:0], N[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_N_FACTOR, _w[6:0], N_FACTOR[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_N_COEFF, _w[6:0], N_COEFF[_w]);
+ bus_write(2'd1, _tn[9:7], _tn[6:0], N_COEFF[TB_NUM_WORDS_N]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_X, _w[6:0], X[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_Y, _w[6:0], Y[_w]);
end
endtask
//
- // set_input_2;
+ // core_set_input_2
//
- task set_input_2;
+ task core_set_input_2;
begin
-// for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd0, BANK_IN_1_M, _w[6:0], M[_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_P, {1'b0, _w[5:0]}, P [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_P, {1'b1, _w[5:0]}, DP [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_P_FACTOR, { _w[6:0]}, P_FACTOR[_w]);
- for (_w=0; _w<=TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_P_COEFF, { _w[6:0]}, P_COEFF [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_Q, {1'b0, _w[5:0]}, Q [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_Q, {1'b1, _w[5:0]}, DQ [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_Q_FACTOR, { _w[6:0]}, Q_FACTOR[_w]);
- for (_w=0; _w<=TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_Q_COEFF, { _w[6:0]}, Q_COEFF [_w]);
- for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd1, BANK_IN_2_QINV, { _w[6:0]}, QINV [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd2, BANK_IN_2_D, { _w[6:0]}, D [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P, {1'b0, _w[5:0]}, P [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P, {1'b1, _w[5:0]}, DP [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P_FACTOR, { _w[6:0]}, P_FACTOR[_w]);
+ for (_w=0; _w<=TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P_COEFF, { _w[6:0]}, P_COEFF [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_Q, {1'b0, _w[5:0]}, Q [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_Q, {1'b1, _w[5:0]}, DQ [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_Q_FACTOR, { _w[6:0]}, Q_FACTOR[_w]);
+ for (_w=0; _w<=TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_Q_COEFF, { _w[6:0]}, Q_COEFF [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_QINV, { _w[6:0]}, QINV [_w]);
end
endtask
//
- // get_output;
+ // core_get_output
//
- task get_output;
+ task core_get_output;
begin
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd2, BANK_OUT_XM, _w[6:0], XM_READBACK[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd2, BANK_OUT_YM, _w[6:0], YM_READBACK[_w]);
- for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd2, BANK_OUT_S, _w[6:0], S_READBACK[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd3, BANK_OUT_XM, _w[6:0], XM_READBACK[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd3, BANK_OUT_YM, _w[6:0], YM_READBACK[_w]);
+ for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_read(2'd3, BANK_OUT_S, _w[6:0], S_READBACK[_w]);
+ wait_clk_bus_ticks(10);
+ $display("Core output banks read.");
end
endtask
//
- // verify;
+ // core_verify_output
//
- task verify;
+ task core_verify_output;
//
reg xm_ok;
reg ym_ok;
@@ -440,7 +511,7 @@ module tb_core_full_1024;
input [31:0] data;
begin
_bus_drive(1'b1, 1'b1, {sel, bank, addr}, data);
- wait_clock_bus_tick;
+ wait_clk_bus_tick;
_bus_drive(1'b0, 1'b0, 12'hXXX, 32'hXXXXXXXX);
end
endtask
@@ -456,7 +527,7 @@ module tb_core_full_1024;
output [31:0] data;
begin
_bus_drive(1'b1, 1'b0, {sel, bank, addr}, 32'hXXXXXXXX);
- wait_clock_bus_tick;
+ wait_clk_bus_tick;
data = bus_data_rd;
_bus_drive(1'b0, 1'b0, 12'hXXX, 32'hXXXXXXXX);
end
@@ -464,48 +535,61 @@ module tb_core_full_1024;
//
- // _wait_half_clock_tick()
+ // _wait_quarter_clk_tick()
//
- task _wait_half_clock_tick;
- #`CLK_PERIOD_HALF_NS;
+ task _wait_quarter_clk_tick;
+ #`CLK_PERIOD_QUARTER_NS;
+ endtask
+
+
+ //
+ // _wait_half_clk_tick()
+ //
+ task _wait_half_clk_tick;
+ begin
+ _wait_quarter_clk_tick;
+ _wait_quarter_clk_tick;
+ end
endtask
+
//
- // wait_clock_tick()
+ // wait_clk_tick()
//
- task wait_clock_tick;
+ task wait_clk_tick;
begin
- _wait_half_clock_tick;
- _wait_half_clock_tick;
+ _wait_half_clk_tick;
+ _wait_half_clk_tick;
end
endtask
//
- // wait_clock_bus_tick()
+ // wait_clk_bus_tick()
//
- task wait_clock_bus_tick;
+ task wait_clk_bus_tick;
#`CLK_BUS_PERIOD_NS;
endtask
//
- // wait_clock_ticks()
+ // wait_clk_ticks()
//
- task wait_clock_ticks;
+ task wait_clk_ticks;
input integer num_ticks;
for (_n=0; _n<num_ticks; _n=_n+1)
- wait_clock_tick;
+ wait_clk_tick;
endtask
//
- // wait_clock_bus_ticks()
+ // wait_clk_bus_ticks()
//
- task wait_clock_bus_ticks;
+ task wait_clk_bus_ticks;
input integer num_ticks;
for (_n=0; _n<num_ticks; _n=_n+1)
- wait_clock_bus_tick;
+ wait_clk_bus_tick;
endtask
+
endmodule
diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v
index cbcdd1d..6357d4e 100644
--- a/bench/tb_core_full_512.v
+++ b/bench/tb_core_full_512.v
@@ -150,6 +150,7 @@ module tb_core_full_512;
// Reset
//
reg rst = 1'b1;
+ wire rst_n = ~rst;
//
@@ -186,7 +187,7 @@ module tb_core_full_512;
.clk (clk),
.clk_bus (clk_bus),
- .rst (rst),
+ .rst_n (rst_n),
.next (core_next),
.valid (core_valid),
@@ -229,8 +230,10 @@ module tb_core_full_512;
//
// Main Routine (Control/Status, Bus)
//
+ integer i, j, k;
task main;
begin
+
sync_clk; // switch to fast core clock
core_reset; // reset core
@@ -316,7 +319,6 @@ module tb_core_full_512;
//
task core_set_input_1;
reg [9:0] _tn;
- reg [31:0] zzz;
begin
_tn = BANK_IN_1_N_COEFF * 2 ** BUS_OP_ADDR_W + TB_NUM_WORDS_N; // trick to write extra trailer word
for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_M, _w[6:0], M[_w]);
diff --git a/bench/tb_wrapper.v b/bench/tb_wrapper.v
index 2000ec5..0c51228 100644
--- a/bench/tb_wrapper.v
+++ b/bench/tb_wrapper.v
@@ -58,7 +58,7 @@ module tb_wrapper;
.clk (clk_bus),
.rst_n (rst_n),
- .clk_core (clk),
+ .clk_core (clk_bus),
.cs (bus_cs),
.we (bus_we),
@@ -83,10 +83,11 @@ module tb_wrapper;
begin
sync_clk_bus;
- wait_clk_bus_ticks(10);
+ wait_clk_bus_ticks(100);
rst_n = 1'b1;
- wait_clk_bus_ticks(10);
+ wait_clk_bus_ticks(100);
+ /*
bus_read('h11, to); $display("modulus_bits = %0d", to);
ti = 100; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
ti = 510; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
@@ -103,8 +104,8 @@ module tb_wrapper;
ti = 1026; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
ti = 4094; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
- ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
- ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
+ ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);*/
+ ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);/*
ti = 4097; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
ti = 4098; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);
@@ -135,11 +136,17 @@ module tb_wrapper;
ti = 1026; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
ti = 4094; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
- ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
- ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
+ ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);*/
+ ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);/*
ti = 4097; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
ti = 4098; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);
-
+ */
+ //ti = 0; bus_write('h08, ti);
+ //ti = 2; bus_write('h08, ti);
+ //ti = 0; bus_write('h08, ti);
+ //ti = 2; bus_write('h08, ti);
+ //ti = 0; bus_write('h08, ti);
+ //ti = 2; bus_write('h08, ti);
end
endtask
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 01:41:08 +0000