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-rw-r--r--bench/tb_core_full_512.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v
index c3a62ab..f17b56c 100644
--- a/bench/tb_core_full_512.v
+++ b/bench/tb_core_full_512.v
@@ -273,7 +273,7 @@ module tb_core_full_512;
sync_clk_bus; // switch to slow bus clock
core_set_input; // write to core input banks
-
+ /*//*/
sync_clk; // switch to fast core clock
core_set_crt_mode(1); // enable CRT signing
core_pulse_next; // assert 'next' bit for one cycle
@@ -282,7 +282,7 @@ module tb_core_full_512;
sync_clk_bus; // switch to slow bus clock
core_get_output; // read from core output banks
core_verify_output; // check, whether core output matches precomputed known good refrence values
-
+ /*//*/
sync_clk; // switch to fast core clock
core_set_crt_mode(0); // disable CRT signing
core_pulse_next; // assert 'next' bit for one cycle
@@ -291,6 +291,7 @@ module tb_core_full_512;
sync_clk_bus; // switch to slow bus clock
core_get_output; // read from core output banks
core_verify_output; // check, whether core output matches precomputed known good refrence values
+ /*//*/
end
endtask
@@ -458,7 +459,6 @@ module tb_core_full_512;
//
endtask
-
//
// _bus_drive()