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author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-16 15:09:59 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-16 15:09:59 +0300 |
commit | 6a0438e33fa300822216c259668180f177ac0343 (patch) | |
tree | 344a8772842e130835110c4388d6618ff1f28d05 /rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v | |
parent | 83f8779a661202183f5866a4e80ef36f24b9e1ea (diff) |
Turns out, fabric addition and subtraction in the general worker module are
actually in the critical paths of the ModExpNG core and are plaguing the place
and route tools. I was barely able to achieve timing closure at 180 MHz even
with the highest Map and PaR effort levels. This means that any further clock
frequency increase is effectively impossible, moreover any small change in the
design may prevent it from meeting timing constants. The obvious solution is to
use DSP slices not only for modular multiplication, but also for supporting
math operations. When fully pipelined, they can be clocked even faster then the
block memory, so there definitely should not be any timing problems with them.
The general worker module does three things that currently involve fabric-based
math operations:
* carry propagation (conversion to non-redundant repsesentation)
* modular subtraction
* regular addition
This commit adds four DSP slice instances and makes the carry propagation
opcode use DSP slice products instead of fabric logic.
Diffstat (limited to 'rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v')
0 files changed, 0 insertions, 0 deletions