Added two pairs of new wrappers.

1 files changed, 124 insertions, 0 deletions

diff --git a/rtl/modexpng_dsp_slice_mult_wrapper_generic.v b/rtl/modexpng_dsp_slice_mult_wrapper_generic.v
new file mode 100644
index 0000000..524d0dd
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_mult_wrapper_generic.v
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+//======================================================================
+//
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpng_dsp_slice_mult_wrapper_generic #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    clk,
+    ce_a1, ce_b1, ce_a2, ce_b2,
+    ce_m, ce_p, ce_mode,
+    a, b, p,
+    inmode, opmode, alumode,
+    casc_a_in,  casc_b_in,
+    casc_a_out, casc_b_out
+);
+
+    `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+        
+    input                           clk;            //
+    input                           ce_a1;          //
+    input                           ce_b1;          //
+    input                           ce_a2;          //
+    input                           ce_b2;          //
+    input                           ce_m;           //
+    input                           ce_p;           //
+    input                           ce_mode;        //
+    input  [       WORD_EXT_W -1:0] a;              //
+    input  [           WORD_W -1:0] b;              //
+    output [            MAC_W -1:0] p;              //
+    input  [ DSP48E1_INMODE_W -1:0] inmode;         //
+    input  [ DSP48E1_OPMODE_W -1:0] opmode;         //
+    input  [DSP48E1_ALUMODE_W -1:0] alumode;        //
+    input  [      DSP48E1_A_W -1:0] casc_a_in;      //
+    input  [      DSP48E1_B_W -1:0] casc_b_in;      //
+    output [      DSP48E1_A_W -1:0] casc_a_out;     //
+    output [      DSP48E1_B_W -1:0] casc_b_out;     //
+    
+    //
+    // A Port
+    //
+    wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in[WORD_EXT_W-1:0];
+    reg  [WORD_EXT_W -1:0] a_reg1;
+    reg  [WORD_EXT_W -1:0] a_reg2;
+
+    assign casc_a_out = a_reg1;
+
+    always @(posedge clk) begin
+        if (ce_a1) a_reg1 <= a_mux;
+        if (ce_a2) a_reg2 <= a_reg1;
+    end
+    
+    //
+    // B Port
+    //
+    wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in[WORD_W-1:0];
+    reg  [WORD_W -1:0] b_reg1;
+    reg  [WORD_W -1:0] b_reg2;
+
+    assign casc_b_out = b_reg1;
+
+    always @(posedge clk) begin
+        if (ce_b1) b_reg1 <= b_mux;
+        if (ce_b2) b_reg2 <= B_REG == 2 ? b_reg1 : b_mux;
+    end
+
+    //
+    // OPMODE Port
+    //
+    reg [DSP48E1_OPMODE_W -1:0] opmode_reg;
+    
+    always @(posedge clk) begin
+        if (ce_mode) opmode_reg <= opmode;
+    end
+
+    //
+    // M, P
+    //
+    reg [MAC_W-1:0] m_reg;
+    reg [MAC_W-1:0] p_reg;
+    
+    wire [MAC_W-1:0] a_pad = {{MAC_W-WORD_EXT_W{1'b0}}, a_reg2};
+    wire [MAC_W-1:0] b_pad = {{MAC_W-WORD_W{1'b0}}, b_reg2};
+    wire [MAC_W-1:0] p_pad = opmode_reg[5] ? p_reg : {MAC_W{1'b0}};
+    
+    assign p = p_reg;
+    
+    always @(posedge clk) begin
+        if (ce_m) m_reg <= a_pad * b_pad;
+        if (ce_p) p_reg <= m_reg + p_pad;
+    end
+
+endmodule