Redesigned core architecture, unified bank structure. All storage blocks now

have eight 4kbit entries and occupy one 36K BRAM tile.

1 files changed, 40 insertions, 0 deletions

diff --git a/rtl/_modexpng_recombinator_cell.v b/rtl/_modexpng_recombinator_cell.v
new file mode 100644
index 0000000..b72395e
--- /dev/null
+++ b/rtl/_modexpng_recombinator_cell.v
@@ -0,0 +1,40 @@
+module modexpng_recombinator_cell
+(
+    clk,
+    ce, clr,
+    din, dout
+);
+
+    //
+    // Headers
+    //
+    `include "modexpng_parameters.vh"
+    
+    //
+    // Ports
+    //
+    input                clk;
+    input                ce;
+    input                clr;
+    input  [ MAC_W -1:0] din;
+    output [WORD_W -1:0] dout;
+
+    reg [WORD_W -2:0] z;
+    reg [WORD_W   :0] y;
+    reg [WORD_W +1:0] x;
+
+    assign dout = x[WORD_W-1:0];
+    
+    wire [WORD_W -2:0] din_z = din[3*WORD_W -2 :2*WORD_W];  // [46:32]
+    wire [WORD_W -1:0] din_y = din[2*WORD_W -1 :  WORD_W];  // [31:16]
+    wire [WORD_W -1:0] din_x = din[  WORD_W -1 :       0];  // [15: 0]
+    
+    always @(posedge clk)
+        //
+        if (ce) begin
+            z <= din_z;
+            y <= clr ? {1'b0,  din_y} : {1'b0,  din_y} + {2'b00, z};
+            x <= clr ? {2'b00, din_x} : {2'b00, din_x} + {1'b0,  y} + {WORD_NULL, x[WORD_EXT_W-1:WORD_W]};        
+        end
+    
+endmodule