Reworked testbench, clk_sys and clk_core can now have any ratio, not

necessarily 1:2.

Fixed compile-time issue where ISE fails to place two DSP slices next to each
other, if A and/or B cascade path(s) between then are partially connected.
Basically, if cascade is used, entire bus must be connected.

1 files changed, 4 insertions, 2 deletions

diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v
index cbcdd1d..6357d4e 100644
--- a/bench/tb_core_full_512.v
+++ b/bench/tb_core_full_512.v
@@ -150,6 +150,7 @@ module tb_core_full_512;
     // Reset
     //
     reg rst = 1'b1;
+    wire rst_n = ~rst;
     
     
     //
@@ -186,7 +187,7 @@ module tb_core_full_512;
         .clk                (clk),
         .clk_bus            (clk_bus),
         
-        .rst                (rst),
+        .rst_n              (rst_n),
         
         .next               (core_next),
         .valid              (core_valid),
@@ -229,8 +230,10 @@ module tb_core_full_512;
     //
     // Main Routine (Control/Status, Bus)
     //
+    integer i, j, k;
     task main;
         begin
+
         
             sync_clk;               // switch to fast core clock
             core_reset;             // reset core
@@ -316,7 +319,6 @@ module tb_core_full_512;
     //
     task core_set_input_1;
         reg [9:0] _tn;
-        reg [31:0] zzz; 
         begin
             _tn = BANK_IN_1_N_COEFF * 2 ** BUS_OP_ADDR_W + TB_NUM_WORDS_N; // trick to write extra trailer word
             for (_w=0; _w<TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd1, BANK_IN_1_M,        _w[6:0],  M[_w]);