Uniform testbenches.

1 files changed, 3 insertions, 3 deletions

diff --git a/bench/tb_core_full_1024.v b/bench/tb_core_full_1024.v
index 96d918e..48a742a 100644
--- a/bench/tb_core_full_1024.v
+++ b/bench/tb_core_full_1024.v
@@ -331,7 +331,7 @@ module tb_core_full_1024;
         
             sync_clk_bus;           // switch to slow bus clock
             core_set_input;         // write to core input banks
-            
+            /**//**/
             sync_clk;               // switch to fast core clock
             core_set_crt_mode(1);   // enable CRT signing
             core_pulse_next;        // assert 'next' bit for one cycle
@@ -341,7 +341,7 @@ module tb_core_full_1024;
             core_get_output;        // read from core output banks
             core_verify_output;     // check, whether core output matches precomputed known good refrence values
             core_print_load;        //
-                        
+            /**//**/
             sync_clk;               // switch to fast core clock
             core_set_crt_mode(0);   // disable CRT signing
             core_pulse_next;        // assert 'next' bit for one cycle
@@ -351,6 +351,7 @@ module tb_core_full_1024;
             core_get_output;        // read from core output banks
             core_verify_output;     // check, whether core output matches precomputed known good refrence values
             core_print_load;        //
+            /**//**/
         end
     endtask
     
@@ -519,7 +520,6 @@ module tb_core_full_1024;
     endtask
     
     
-
     //
     // _bus_drive()
     //