From 2db58a7ba317da318eca5ae19dcc0e4899c423e1 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 18 Jul 2017 02:14:27 +0300 Subject: Changes to the model: * Follow what Verilog does more closely: FPGA can't do PP = P * P, because it can't read from two different block mem P locations at the same time, we have to do P1 = P2 = P, PP = P1 * P2 * Updated the test vector script to format additional quantities to help debug Verilog exponentiation module * Added the trick suggested by Bernd Paysan to help better conceal whether we're discarding multiplication result when the current exponent bit is not set --- modexp_fpga_model.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'modexp_fpga_model.h') diff --git a/modexp_fpga_model.h b/modexp_fpga_model.h index 2a91d32..567b625 100644 --- a/modexp_fpga_model.h +++ b/modexp_fpga_model.h @@ -57,6 +57,12 @@ typedef uint64_t _WIDE_WORD; // only used internally to mimic DSP slice operati #define SYSTOLIC_WIDTH 128 // width of systolic array in bits +//---------------------------------------------------------------- +// Power Consumption Masking Constant +//---------------------------------------------------------------- +#define POWER_MASK 0x5A5A5A5A + + //---------------------------------------------------------------- // Handy values //---------------------------------------------------------------- -- cgit v1.2.3