From 53e92c5355aca120eab8d59e6904282c9e3b4ab1 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 13 Jun 2017 20:11:58 +0300 Subject: Initial commit of faster modular exponentiation model based on systolic architecture. --- README.md | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 README.md (limited to 'README.md') diff --git a/README.md b/README.md new file mode 100644 index 0000000..8db40cc --- /dev/null +++ b/README.md @@ -0,0 +1,10 @@ +# modexp_fpga_model + +This reference model was written to help debug Verilog code, it mimics how an FPGA would do modular exponentiation using systolic Montgomery multiplier. Note, that the model may do weird (from CPU point of view, of course) things at times. Another important thing is that while FPGA modules are written to operate in true constant-time manner, this model itself doesn't take any active measures to keep run-time constant. Do **NOT** use it in production as-is! + +The model is split into low-level primitives (32-bit adder, 32-bit subtractor, 32x32-bit multiplier with pre-adder) and higher-level arithmetic routines (multiplier and exponentiator). + +This model uses tips and tricks from the following sources: +1. [High-Speed RSA Implementation](ftp://ftp.rsasecurity.com/pub/pdfs/tr201.pdf) +2. [Handbook of Applied Cryptography](http://cacr.uwaterloo.ca/hac/) +3. [Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation](https://www.hindawi.com/journals/ijrc/2011/127147/) -- cgit v1.2.3