From 91cdd1b39e10a604719a030c98a2339ab3164941 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sun, 6 Aug 2017 21:41:03 +0300 Subject: Follow what Verilog does more closely. --- modexp_fpga_model_montgomery.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/modexp_fpga_model_montgomery.cpp b/modexp_fpga_model_montgomery.cpp index 92a5e47..7455b23 100644 --- a/modexp_fpga_model_montgomery.cpp +++ b/modexp_fpga_model_montgomery.cpp @@ -85,9 +85,9 @@ void montgomery_multiply(const FPGA_WORD *A, const FPGA_WORD *B, const FPGA_WORD for (i=0; i<(2*len); i++) AB[i] = A[i]; - if (!reduce_only) multiply_systolic(A, B, AB, len, 2 * len); // AB = A * B - multiply_systolic(AB, N_COEFF, Q, len, len); // Q = AB * N_COEFF - multiply_systolic(Q, N, QN, len, 2 * len); // QN = Q * N + if (!reduce_only) multiply_systolic(A, B, AB, len, 2 * len); // AB = A * B + multiply_systolic(N_COEFF, AB, Q, len, len); // Q = AB * N_COEFF + multiply_systolic(Q, N, QN, len, 2 * len); // QN = Q * N // initialize 1-bit carry and borrow c_in_s = 0, b_in_sn = 0; -- cgit v1.2.3