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//------------------------------------------------------------------------------
//
// ecdsa_fpga_microcode.h
// --------------------------------
// Microcode Architecture for ECDSA
//
// Authors: Pavel Shatov
//
// Copyright (c) 2018, 2021 NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <stdlib.h> // NULL
//------------------------------------------------------------------------------
enum UOP_BANK
//------------------------------------------------------------------------------
{
BANK_LO, BANK_HI
};
//--------------------------
enum UOP_OPERAND
//--------------------------
{
CONST_ZERO, // 0
CONST_ONE, // 1
CONST_DELTA, // 2
CONST_GX, // 3
CONST_GY, // 4
CYCLE_R0X, // 5
CYCLE_R0Y, // 6
CYCLE_R0Z, // 7
CYCLE_R1X, // 8
CYCLE_R1Y, // 9
CYCLE_R1Z, // 10
CYCLE_SX, // 11
CYCLE_SY, // 12
CYCLE_SZ, // 13
CYCLE_TX, // 14
CYCLE_TY, // 15
CYCLE_TZ, // 16
CYCLE_T1, // 17
CYCLE_T2, // 18
CYCLE_T3, // 19
CYCLE_T4, // 20
CYCLE_T5, // 21
CYCLE_T6, // 22
CYCLE_T7, // 23
CYCLE_T8, // 24
INVERT_R1, // 25
INVERT_R2, // 26
INVERT_X2, // 27
INVERT_X3, // 28
INVERT_X6, // 29
INVERT_X12, // 30
INVERT_X15, // 31
INVERT_X30, // 32
INVERT_X32, // 33
INVERT_X60, // 34
INVERT_X120, // 35
INVERT_A2, // 36
INVERT_A3, // 37
ECDSA_UOP_OPERAND_COUNT
};
//------------------------------------------------------------------------------
enum UOP_MATH
//------------------------------------------------------------------------------
{
ADD, SUB, MUL
};
//------------------------------------------------------------------------------
// Global Storage Buffers
//------------------------------------------------------------------------------
extern FPGA_BUFFER BUF_LO[ECDSA_UOP_OPERAND_COUNT];
extern FPGA_BUFFER BUF_HI[ECDSA_UOP_OPERAND_COUNT];
//------------------------------------------------------------------------------
// Global Flags
//------------------------------------------------------------------------------
extern bool uop_flagz_r0z;
extern bool uop_flagz_r1z;
//------------------------------------------------------------------------------
// Loop Macros
//------------------------------------------------------------------------------
#define uop_loop int uop_cnt
#define uop_cycle(iters); for (uop_cnt=0; uop_cnt<iters; uop_cnt++) {
#define uop_repeat(); }
#define uop_calc_if_even(...) if (!(uop_cnt % 2)) uop_calc(__VA_ARGS__)
#define uop_calc_if_odd(...) else uop_calc(__VA_ARGS__)
//------------------------------------------------------------------------------
// Prototypes (Micro-Operations)
//------------------------------------------------------------------------------
void uop_move(enum UOP_BANK src, int s_op1, UOP_BANK dst, int d_op1);
void uop_cmpz(UOP_BANK src, int s_op);
void uop_calc (UOP_MATH math,
UOP_BANK src, int s_op1, int s_op2,
UOP_BANK dst, int d_op);
void uop_load(const FPGA_BUFFER *mem, UOP_BANK dst, int d_op);
void uop_stor(UOP_BANK src, int s_op, FPGA_BUFFER *mem);
//------------------------------------------------------------------------------
// End-of-File
//------------------------------------------------------------------------------
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