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-rw-r--r--ecdsa_fpga_modular.cpp27
-rw-r--r--ecdsa_fpga_modular.h8
2 files changed, 33 insertions, 2 deletions
diff --git a/ecdsa_fpga_modular.cpp b/ecdsa_fpga_modular.cpp
index 9d22c05..4ef4dc1 100644
--- a/ecdsa_fpga_modular.cpp
+++ b/ecdsa_fpga_modular.cpp
@@ -6,7 +6,7 @@
//
// Authors: Pavel Shatov
//
-// Copyright (c) 2015-2016, 2018 NORDUnet A/S
+// Copyright (c) 2015-2016, 2018, 2021 NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
@@ -51,6 +51,12 @@ FPGA_BUFFER ECDSA_DELTA;
//------------------------------------------------------------------------------
+// Settings
+//------------------------------------------------------------------------------
+bool _DUMP_MODULAR_RESULTS = false;
+
+
+//------------------------------------------------------------------------------
void fpga_modular_init()
//------------------------------------------------------------------------------
{
@@ -126,6 +132,9 @@ void fpga_modular_add(const FPGA_BUFFER *a, const FPGA_BUFFER *b, FPGA_BUFFER *s
*/
for (w=0; w<FPGA_OPERAND_NUM_WORDS; w++)
s->words[w] = (b_out && !c_out) ? ab.words[w] : ab_n.words[w];
+
+ if (_DUMP_MODULAR_RESULTS)
+ dump_uop_output("ADD", s);
}
@@ -180,6 +189,9 @@ void fpga_modular_sub(const FPGA_BUFFER *a, const FPGA_BUFFER *b, FPGA_BUFFER *d
*/
for (w=0; w<FPGA_OPERAND_NUM_WORDS; w++)
d->words[w] = b_out ? ab_n.words[w] : ab.words[w];
+
+ if (_DUMP_MODULAR_RESULTS)
+ dump_uop_output("SUB", d);
}
@@ -207,6 +219,12 @@ void fpga_modular_mul(const FPGA_BUFFER *a, const FPGA_BUFFER *b, FPGA_BUFFER *p
FPGA_WORD_EXTENDED si[4*FPGA_OPERAND_NUM_WORDS-1]; // parts of intermediate product
FPGA_WORD c[2*FPGA_OPERAND_NUM_WORDS]; // full-size intermediate product
+ /* save debug flag */
+ bool _save_dump_modular_results = _DUMP_MODULAR_RESULTS;
+
+ /* mask debug flag to not garble output */
+ _DUMP_MODULAR_RESULTS = false;
+
/* multiply to get partial words */
fpga_modular_mul_helper_multiply(a, b, si);
@@ -215,6 +233,13 @@ void fpga_modular_mul(const FPGA_BUFFER *a, const FPGA_BUFFER *b, FPGA_BUFFER *p
/* reduce full-size product using special routine */
fpga_modular_mul_helper_reduce(c, p);
+
+ /* restore debug flag */
+ _DUMP_MODULAR_RESULTS = _save_dump_modular_results;
+
+ /* now dump result if needed */
+ if (_DUMP_MODULAR_RESULTS)
+ dump_uop_output("MUL", p);
}
diff --git a/ecdsa_fpga_modular.h b/ecdsa_fpga_modular.h
index 3b75779..3a054e3 100644
--- a/ecdsa_fpga_modular.h
+++ b/ecdsa_fpga_modular.h
@@ -6,7 +6,7 @@
//
// Authors: Pavel Shatov
//
-// Copyright (c) 2015-2016, 2018 NORDUnet A/S
+// Copyright (c) 2015-2016, 2018, 2021 NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
@@ -97,6 +97,12 @@ extern FPGA_BUFFER ECDSA_DELTA;
//------------------------------------------------------------------------------
+// Settings
+//------------------------------------------------------------------------------
+extern bool _DUMP_MODULAR_RESULTS;
+
+
+//------------------------------------------------------------------------------
// Prototypes
//------------------------------------------------------------------------------
void fpga_modular_init ();