From af8406afa98ae2c2ddca0c9e16a0cb34eb79519b Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Fri, 20 Jan 2017 17:52:11 -0500 Subject: Minimal changes needed to build with core_selector. Synthesizes, not yet tested with libhal (driver still needs writing). This changes the bare minimum necessary to get core/platform/alpha/build/Makefile to run to completion with this core added: * Verilog include filename syntax changed from from DOS ("\") to Unix ("/"). * rst_n => reset_n in ecdsa256_wrapper to match all the other cores. * address port changed from 5 bits to 8 bits in ecdsa256_wrapper to match all the other cores. This code could use some cosmetic cleanup, indentation is inconsistent (at least, it displays inconsistently, may depend on tab stop settings or something like that) and end of line still uses DOS convention (CRLF instead of Unix LF), but that stuff can wait. --- rtl/ecdsa256_wrapper.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/ecdsa256_wrapper.v') diff --git a/rtl/ecdsa256_wrapper.v b/rtl/ecdsa256_wrapper.v index c6e93ea..ff324b6 100644 --- a/rtl/ecdsa256_wrapper.v +++ b/rtl/ecdsa256_wrapper.v @@ -33,12 +33,12 @@ module ecdsa256_wrapper ( input wire clk, - input wire rst_n, + input wire reset_n, input wire cs, input wire we, - input wire [5: 0] address, + input wire [7: 0] address, input wire [31: 0] write_data, output wire [31: 0] read_data ); @@ -102,7 +102,7 @@ module ecdsa256_wrapper ecdsa256 ecdsa256_inst ( .clk (clk), - .rst_n (rst_n), + .rst_n (reset_n), .next (reg_control), .valid (reg_status), @@ -126,7 +126,7 @@ module ecdsa256_wrapper // always @(posedge clk) // - if (!rst_n) begin + if (!reset_n) begin // reg_control <= 1'b0; // -- cgit v1.2.3