|
Synthesizes, not yet tested with libhal (driver still needs writing).
This changes the bare minimum necessary to get
core/platform/alpha/build/Makefile to run to completion with this core
added:
* Verilog include filename syntax changed from from DOS ("\") to Unix ("/").
* rst_n => reset_n in ecdsa256_wrapper to match all the other cores.
* address port changed from 5 bits to 8 bits in ecdsa256_wrapper to
match all the other cores.
This code could use some cosmetic cleanup, indentation is inconsistent
(at least, it displays inconsistently, may depend on tab stop settings
or something like that) and end of line still uses DOS convention
(CRLF instead of Unix LF), but that stuff can wait.
|
