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2017-01-20Minimal changes needed to build with core_selector.core_selectorRob Austein
Synthesizes, not yet tested with libhal (driver still needs writing). This changes the bare minimum necessary to get core/platform/alpha/build/Makefile to run to completion with this core added: * Verilog include filename syntax changed from from DOS ("\") to Unix ("/"). * rst_n => reset_n in ecdsa256_wrapper to match all the other cores. * address port changed from 5 bits to 8 bits in ecdsa256_wrapper to match all the other cores. This code could use some cosmetic cleanup, indentation is inconsistent (at least, it displays inconsistently, may depend on tab stop settings or something like that) and end of line still uses DOS convention (CRLF instead of Unix LF), but that stuff can wait.
2016-12-04Added README.md with core description, API details, etcPavel V. Shatov (Meister)
Added previously forgotten generic replacements for vendor-specific primitives Minor clean up of comments Slightly reduced power consumption
2016-10-31Initial commit of base point multiplier core for ECDSA curve P-256.Pavel V. Shatov (Meister)