Initial commit of base point multiplier core for ECDSA curve P-256.

1 files changed, 70 insertions, 0 deletions

diff --git a/rtl/curve/rom/brom_p256_zero.v b/rtl/curve/rom/brom_p256_zero.v
new file mode 100644
index 0000000..f6d19a1
--- /dev/null
+++ b/rtl/curve/rom/brom_p256_zero.v
@@ -0,0 +1,70 @@
+//======================================================================
+//
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+`timescale 1ns / 1ps
+
+module brom_p256_zero
+   (
+		//input		wire				clk,
+		//input		wire	[ 3-1:0]	b_addr,
+		output	wire	[32-1:0]	b_out
+    );
+
+

+	assign b_out = {32{1'b0}};

+
+   //
+   // Output Registers
+   //
+   //reg [31:0] bram_reg_b;
+
+   //assign b_out = bram_reg_b;
+
+
+   //
+   // Read-Only Port B
+	//
+	//always @(posedge clk)
+		//

+		//case (b_addr)

+			//3'b000:	bram_reg_b <= 32'h00000000;

+			//3'b001:	bram_reg_b <= 32'h00000000;

+			//3'b010:	bram_reg_b <= 32'h00000000;

+			//3'b011:	bram_reg_b <= 32'h00000000;

+			//3'b100:	bram_reg_b <= 32'h00000000;

+			//3'b101:	bram_reg_b <= 32'h00000000;

+			//3'b110:	bram_reg_b <= 32'h00000000;

+			//3'b111:	bram_reg_b <= 32'h00000000;

+		//endcase
+
+
+endmodule