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authorRob Austein <sra@hactrn.net>2017-01-20 17:52:11 -0500
committerRob Austein <sra@hactrn.net>2017-01-20 17:52:11 -0500
commitaf8406afa98ae2c2ddca0c9e16a0cb34eb79519b (patch)
tree6e513cf115ea4465c60ce82dd3ceb50fb6a11bbf /bench
parenta66be3237f5e9f4b6144cec093b047acfd70ffc6 (diff)
Minimal changes needed to build with core_selector.core_selector
Synthesizes, not yet tested with libhal (driver still needs writing). This changes the bare minimum necessary to get core/platform/alpha/build/Makefile to run to completion with this core added: * Verilog include filename syntax changed from from DOS ("\") to Unix ("/"). * rst_n => reset_n in ecdsa256_wrapper to match all the other cores. * address port changed from 5 bits to 8 bits in ecdsa256_wrapper to match all the other cores. This code could use some cosmetic cleanup, indentation is inconsistent (at least, it displays inconsistently, may depend on tab stop settings or something like that) and end of line still uses DOS convention (CRLF instead of Unix LF), but that stuff can wait.
Diffstat (limited to 'bench')
0 files changed, 0 insertions, 0 deletions