From d705299dee1f1826e9fcd4a31e8212b955de17bf Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 3 Apr 2018 00:29:40 +0300 Subject: Verilog test vector generation. --- test_vectors/ecdh_test_vectors.v | 74 ++++++++++++ test_vectors/format_test_vectors.py | 218 ++++++++++-------------------------- 2 files changed, 135 insertions(+), 157 deletions(-) create mode 100644 test_vectors/ecdh_test_vectors.v diff --git a/test_vectors/ecdh_test_vectors.v b/test_vectors/ecdh_test_vectors.v new file mode 100644 index 0000000..a1bc092 --- /dev/null +++ b/test_vectors/ecdh_test_vectors.v @@ -0,0 +1,74 @@ +/* Generated automatically, do not edit. */ + +localparam [255:0] P_256_DA \ + {32'h404d4afa, 32'h3865a3d6, 32'hf921ccb4, 32'h7cdea4e9, + 32'h276c3d45, 32'h6e84d196, 32'h63324daf, 32'h8c5e2f44}; + +localparam [255:0] P_256_QA_X \ + {32'h6f3b61af, 32'h3d79d1b6, 32'h7c128369, 32'h1fe8e872, + 32'hde81e17a, 32'h06b5d4e1, 32'haeedcd57, 32'h09bf1d1b}; + +localparam [255:0] P_256_QA_Y \ + {32'hd1345bcc, 32'ha022ea89, 32'h53b04c2d, 32'h11fc24f8, + 32'h0b3b7f84, 32'h7b79deee, 32'hd92ec430, 32'hd8ec3c98}; + +localparam [255:0] P_256_DB \ + {32'h7159a43b, 32'he8322471, 32'h19feaeb2, 32'h7a92466e, + 32'h2b07c8df, 32'h29bbd7ea, 32'hd3232af8, 32'h44995a95}; + +localparam [255:0] P_256_QB_X \ + {32'h0514608d, 32'hc2dc6a21, 32'h74b084d6, 32'h168aad13, + 32'h4acd3f52, 32'h6e49dc32, 32'hbf9872aa, 32'ha4be99d9}; + +localparam [255:0] P_256_QB_Y \ + {32'h724afa75, 32'h4c672b71, 32'he87c9bda, 32'he1e2b15f, + 32'h784f480f, 32'heb62040e, 32'h281953bd, 32'hea382946}; + +localparam [255:0] P_256_S_X \ + {32'ha001c11b, 32'h0d04b6c3, 32'hbe99551e, 32'h9115b811, + 32'h0a41a0b7, 32'h59c3e3f2, 32'hfb636df1, 32'heb0e9a42}; + +localparam [255:0] P_256_S_Y \ + {32'h14ed5674, 32'h62b6ba27, 32'h2ba0e01b, 32'h2647d725, + 32'h5919bf5e, 32'hcbb542f7, 32'h659d40de, 32'h324524ac}; + +localparam [383:0] P_384_DA \ + {32'he733d9db, 32'hb8867b57, 32'h3cbbc0bd, 32'h899c88db, + 32'h669322e8, 32'h0435c1a4, 32'he2b0ddb1, 32'h5e757371, + 32'hf684a595, 32'h05d923c8, 32'hbf96dc11, 32'hc3ae505a}; + +localparam [383:0] P_384_QA_X \ + {32'h8b852708, 32'h18311f7f, 32'h1ef2f04d, 32'hb38e68b2, + 32'h3c008bfb, 32'h14e20cb0, 32'h37efa421, 32'hc3c3df6d, + 32'ha37c484e, 32'h855da981, 32'hda866580, 32'h7203ff36}; + +localparam [383:0] P_384_QA_Y \ + {32'hd748f515, 32'hef7f2672, 32'h0ce8a70e, 32'h20827296, + 32'h8ee6a89a, 32'haeccd8fb, 32'h61b35364, 32'hc70dfb48, + 32'heb5c685c, 32'h810bd9cb, 32'h2d184fb1, 32'h096ab30f}; + +localparam [383:0] P_384_DB \ + {32'h5601820d, 32'h705224a5, 32'hdd6ddb13, 32'he0a15e76, + 32'h869e6abe, 32'h37ba2235, 32'h792af9f6, 32'ha9bf114a, + 32'hd1fd319d, 32'hd8181e06, 32'h44f15448, 32'h4e73a75a}; + +localparam [383:0] P_384_QB_X \ + {32'h37ab556d, 32'h0652c6b9, 32'he352c643, 32'h4502be19, + 32'h9fb9c50f, 32'h2ade049b, 32'h06e50c30, 32'hcdab0673, + 32'h69efe0c0, 32'h6e114a76, 32'hf1338175, 32'hdb4f4982}; + +localparam [383:0] P_384_QB_Y \ + {32'h21cddae0, 32'hf117b656, 32'h7c9d477b, 32'hc1fc5d24, + 32'h3b26651e, 32'h1406f1ee, 32'hb3418552, 32'h739c9395, + 32'h6774c84d, 32'h20cedc15, 32'h92fd5de0, 32'h4bbf98ad}; + +localparam [383:0] P_384_S_X \ + {32'h15ac62cb, 32'hbb51e1ed, 32'hd41d489f, 32'hdfa05d45, + 32'h115f4ef2, 32'h269fbd26, 32'h3f6c7364, 32'h673f0b19, + 32'h489e8a7b, 32'hdfad6d40, 32'h277edf9f, 32'h62220c51}; + +localparam [383:0] P_384_S_Y \ + {32'ha0b846fe, 32'ha76973b4, 32'h12dfae76, 32'h2b3b6587, + 32'hf62be0a3, 32'h73da36ef, 32'h8992e7c9, 32'h6cf7619d, + 32'ha2d6c0a2, 32'hd31ad05d, 32'hb3a16a95, 32'h0cb7055f}; + diff --git a/test_vectors/format_test_vectors.py b/test_vectors/format_test_vectors.py index a49b34b..1389711 100644 --- a/test_vectors/format_test_vectors.py +++ b/test_vectors/format_test_vectors.py @@ -60,82 +60,6 @@ P256_GY = 0x4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5 P384_GX = 0xaa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7 P384_GY = 0x3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f - -# -# get part of string between two markers -# -#def string_between(s, s_left, s_right): -# s_begin = s.index(s_left) + len(s_left) -# s_end = s.index(s_right, s_begin) -# return s[s_begin:s_end] - -# -# load message from file -# -#def read_message(key): -# with open(key + ".txt", "r") as f: -# return f.readlines()[0] -# -# -# read modulus from file -# -#def read_modulus(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-modulus"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# return openssl_stdout.strip().split("=")[1] - -# -# read private exponent from file -# -#def read_secret(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-text"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# openssl_secret = string_between(openssl_stdout, "privateExponent", "prime1") -# openssl_secret = openssl_secret.replace(":", "") -# openssl_secret = openssl_secret.replace("\n", "") -# openssl_secret = openssl_secret.replace(" ", "") -# return openssl_secret - -# -# read part of private key from file -# -#def read_prime1(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-text"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# openssl_secret = string_between(openssl_stdout, "prime1", "prime2") -# openssl_secret = openssl_secret.replace(":", "") -# openssl_secret = openssl_secret.replace("\n", "") -# openssl_secret = openssl_secret.replace(" ", "") -# return openssl_secret -#def read_prime2(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-text"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# openssl_secret = string_between(openssl_stdout, "prime2", "exponent1") -# openssl_secret = openssl_secret.replace(":", "") -# openssl_secret = openssl_secret.replace("\n", "") -# openssl_secret = openssl_secret.replace(" ", "") -# return openssl_secret - -# -# read prive exponent from file -# -#def read_exponent1(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-text"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# openssl_secret = string_between(openssl_stdout, "exponent1", "exponent2") -# openssl_secret = openssl_secret.replace(":", "") -# openssl_secret = openssl_secret.replace("\n", "") -# openssl_secret = openssl_secret.replace(" ", "") -# return openssl_secret -#def read_exponent2(key): -# openssl_command = ["openssl", "rsa", "-in", key + ".key", "-noout", "-text"] -# openssl_stdout = subprocess.check_output(openssl_command).decode("utf-8") -# openssl_secret = string_between(openssl_stdout, "exponent2", "coefficient") -# openssl_secret = openssl_secret.replace(":", "") -# openssl_secret = openssl_secret.replace("\n", "") -# openssl_secret = openssl_secret.replace(" ", "") -# return openssl_secret - # # format one test vector # @@ -156,49 +80,30 @@ def format_c_header(f, curve, da, qax, qay, db, qbx, qby, sx, sy): format_c_array(f, sx, "#define " + curve_str + "_S_X" + " \\\n") format_c_array(f, sy, "#define " + curve_str + "_S_Y" + " \\\n") - # # format one test vector # -#def format_verilog_include(f, key, n, m, d, s, p, q, dp, dq, mp, mq): -# -# # calculate factor to bring message into Montgomery domain -# factor = calc_montgomery_factor(int(key), n) -# factor_p = calc_montgomery_factor(int(key)//2, p); -# factor_q = calc_montgomery_factor(int(key)//2, q); -# -# # calculate helper coefficients for Montgomery multiplication -# n_coeff = calc_montgomery_n_coeff(int(key), n) -# p_coeff = calc_montgomery_n_coeff(int(key)//2, p) -# q_coeff = calc_montgomery_n_coeff(int(key)//2, q) -# -# # calculate the extra coefficient Montgomery multiplication brings in -# coeff = modinv(1 << int(key), n) -# -# # convert m into Montgomery representation -# m_factor = (m * factor * coeff) % n -# -# # write all numbers -# format_verilog_concatenation(f, m, "localparam [" + str(int(key)-1) + ":0] M_" + key + " =\n") -# format_verilog_concatenation(f, n, "localparam [" + str(int(key)-1) + ":0] N_" + key + " =\n") -# format_verilog_concatenation(f, n_coeff, "localparam [" + str(int(key)-1) + ":0] N_COEFF_" + key + " =\n") -# format_verilog_concatenation(f, factor, "localparam [" + str(int(key)-1) + ":0] FACTOR_" + key + " =\n") -# format_verilog_concatenation(f, coeff, "localparam [" + str(int(key)-1) + ":0] COEFF_" + key + " =\n") -# format_verilog_concatenation(f, m_factor, "localparam [" + str(int(key)-1) + ":0] M_FACTOR_" + key + " =\n") -# format_verilog_concatenation(f, d, "localparam [" + str(int(key)-1) + ":0] D_" + key + " =\n") -# format_verilog_concatenation(f, s, "localparam [" + str(int(key)-1) + ":0] S_" + key + " =\n") -# -# format_verilog_concatenation(f, p, "localparam [" + str(int(key)//2-1) + ":0] P_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, q, "localparam [" + str(int(key)//2-1) + ":0] Q_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, p_coeff, "localparam [" + str(int(key)//2-1) + ":0] P_COEFF_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, q_coeff, "localparam [" + str(int(key)//2-1) + ":0] Q_COEFF_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, factor_p, "localparam [" + str(int(key)//2-1) + ":0] FACTOR_P_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, factor_q, "localparam [" + str(int(key)//2-1) + ":0] FACTOR_Q_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, dp, "localparam [" + str(int(key)//2-1) + ":0] DP_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, dq, "localparam [" + str(int(key)//2-1) + ":0] DQ_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, mp, "localparam [" + str(int(key)//2-1) + ":0] MP_" + str(int(key)//2) + " =\n") -# format_verilog_concatenation(f, mq, "localparam [" + str(int(key)//2-1) + ":0] MQ_" + str(int(key)//2) + " =\n") +def format_verilog_include(f, curve, da, qax, qay, db, qbx, qby, sx, sy): + if curve == CURVE_P256: + curve_str = "P_256" + msb_index = "255" + + if curve == CURVE_P384: + curve_str = "P_384" + msb_index = "383" + + # write all numbers in vector + format_verilog_concatenation(f, da, "localparam [" + msb_index + ":0] " + curve_str + "_DA" + " \\\n") + format_verilog_concatenation(f, qax, "localparam [" + msb_index + ":0] " + curve_str + "_QA_X" + " \\\n") + format_verilog_concatenation(f, qay, "localparam [" + msb_index + ":0] " + curve_str + "_QA_Y" + " \\\n") + + format_verilog_concatenation(f, db, "localparam [" + msb_index + ":0] " + curve_str + "_DB" + " \\\n") + format_verilog_concatenation(f, qbx, "localparam [" + msb_index + ":0] " + curve_str + "_QB_X" + " \\\n") + format_verilog_concatenation(f, qby, "localparam [" + msb_index + ":0] " + curve_str + "_QB_Y" + " \\\n") + + format_verilog_concatenation(f, sx, "localparam [" + msb_index + ":0] " + curve_str + "_S_X" + " \\\n") + format_verilog_concatenation(f, sy, "localparam [" + msb_index + ":0] " + curve_str + "_S_Y" + " \\\n") # # nicely format multi-word integer into C array initializer @@ -247,44 +152,43 @@ def format_c_array(f, n, s): # write final newline f.write("\n") +def format_verilog_concatenation(f, n, s): -#def format_verilog_concatenation(f, n, s): -# -# # print 'localparam ZZZ =' -# f.write(s) -# -# # convert number to hex string and prepend it with zeroes if necessary -# n_hex = hex(n).split("0x")[1] -# while (len(n_hex) % 8) > 0: -# n_hex = "0" + n_hex -# -# # get number of 32-bit words -# num_words = len(n_hex) // 8 -# -# # print all words in n -# w = 0 -# while w < num_words: -# -# n_part = "" -# -# if w == 0: -# n_part += "\t{" -# elif (w % 4) == 0: -# n_part += "\t " -# -# n_part += "32'h" + n_hex[8 * w : 8 * (w + 1)] -# -# if (w + 1) == num_words: -# n_part += "};\n" -# else: -# n_part += ", " -# if (w % 4) == 3: -# n_part += "\n" -# w += 1 -# -# f.write(n_part) -# -# f.write("\n") + # print 'localparam ZZZ =' + f.write(s) + + # convert number to hex string and prepend it with zeroes if necessary + n_hex = hex(n).split("0x")[1] + while (len(n_hex) % 8) > 0: + n_hex = "0" + n_hex + + # get number of 32-bit words + num_words = len(n_hex) // 8 + + # print all words in n + w = 0 + while w < num_words: + + n_part = "" + + if w == 0: + n_part += "\t{" + elif (w % 4) == 0: + n_part += "\t " + + n_part += "32'h" + n_hex[8 * w : 8 * (w + 1)] + + if (w + 1) == num_words: + n_part += "};\n" + else: + n_part += ", " + if (w % 4) == 3: + n_part += "\n" + w += 1 + + f.write(n_part) + + f.write("\n") # @@ -402,12 +306,12 @@ if __name__ == "__main__": curves = [CURVE_P256, CURVE_P384] # open output files - file_h = open('ecdsa_fpga_model_ecdh_vectors.h', 'w') -# file_v = open('modexp_fpga_model_vectors.v', 'w') + file_h = open('ecdh_test_vectors.h', 'w') + file_v = open('ecdh_test_vectors.v', 'w') # write headers file_h.write("/* Generated automatically, do not edit. */\n\n") -# file_v.write("/* Generated automatically, do not edit. */\n\n") + file_v.write("/* Generated automatically, do not edit. */\n\n") # process all the keys for curve in curves: @@ -436,11 +340,11 @@ if __name__ == "__main__": # format numbers and write to file format_c_header(file_h, curve, da, qax, qay, db, qbx, qby, QAB.x, QBA.y) -# format_verilog_include(file_v, key, modulus, message, secret, signature, prime1, prime2, exponent1, exponent2, message1, message2) + format_verilog_include(file_v, curve, da, qax, qay, db, qbx, qby, QAB.x, QBA.y) # done file_h.close() -# file_v.close() + file_v.close() # everything went just fine print("Test vectors formatted.") -- cgit v1.2.3