EESchema Schematic File Version 4 EELAYER 30 0 EELAYER END $Descr B 17000 11000 encoding utf-8 Sheet 21 27 Title "rev04_19" Date "15 10 2016" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Text Notes 2000 3100 0 60 ~ 12 *) Upper Right Bank Text Notes 5000 5450 0 60 ~ 12 *) FPGA_GCLK signal _MUST_ go into either D17 or C18\n(i.e. into one of the two positive (master) sides\nof the two available MRCC differential pairs) Text Notes 5000 5750 0 60 ~ 12 *) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped Text Notes 7930 3010 0 60 ~ 12 *) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank. Text Notes 5000 4850 0 60 ~ 12 NOTE: One of the FPGA_GPIO_* pins\nshould be connected to one of the\nMRCC pins.\nThe non-MRCC GPIO signals should be\nlength matched to within 500 ps of\nthe MRCC signal. Text Notes 7990 1280 0 84 ~ 17 FPGA GPIO Text Notes 9950 3600 2 60 ~ 12 MA08-2 Text Notes 9950 4630 2 60 ~ 12 SV2 Text Notes 9950 5500 2 60 ~ 12 MA08-2 Text Notes 9950 6530 2 60 ~ 12 SV3 Text Notes 8260 4190 0 60 ~ 12 C121 Text Notes 8260 4390 0 60 ~ 12 0.1~uF Text Notes 8260 6090 0 60 ~ 12 C122 Text Notes 8260 6290 0 60 ~ 12 0.1~uF $Comp L power:GND #GND_0125 U 1 1 58023F03 P 8200 4700 F 0 "#GND_0125" H 8200 4700 20 0000 C CNN F 1 "+GND" H 8200 4630 30 0000 C CNN F 2 "" H 8200 4700 70 0000 C CNN F 3 "" H 8200 4700 70 0000 C CNN 1 8200 4700 1 0 0 -1 $EndComp $Comp L power:GND #GND_0126 U 1 1 58023F02 P 9400 4700 F 0 "#GND_0126" H 9400 4700 20 0000 C CNN F 1 "+GND" H 9400 4630 30 0000 C CNN F 2 "" H 9400 4700 70 0000 C CNN F 3 "" H 9400 4700 70 0000 C CNN 1 9400 4700 1 0 0 -1 $EndComp $Comp L power:GND #GND_0127 U 1 1 58023F01 P 10200 4700 F 0 "#GND_0127" H 10200 4700 20 0000 C CNN F 1 "+GND" H 10200 4630 30 0000 C CNN F 2 "" H 10200 4700 70 0000 C CNN F 3 "" H 10200 4700 70 0000 C CNN 1 10200 4700 1 0 0 -1 $EndComp $Comp L power:GND #GND_0128 U 1 1 58023F00 P 8200 6600 F 0 "#GND_0128" H 8200 6600 20 0000 C CNN F 1 "+GND" H 8200 6530 30 0000 C CNN F 2 "" H 8200 6600 70 0000 C CNN F 3 "" H 8200 6600 70 0000 C CNN 1 8200 6600 1 0 0 -1 $EndComp $Comp L power:GND #GND_0129 U 1 1 58023EFF P 9400 6600 F 0 "#GND_0129" H 9400 6600 20 0000 C CNN F 1 "+GND" H 9400 6530 30 0000 C CNN F 2 "" H 9400 6600 70 0000 C CNN F 3 "" H 9400 6600 70 0000 C CNN 1 9400 6600 1 0 0 -1 $EndComp $Comp L power:GND #GND_0130 U 1 1 58023EFE P 10200 6600 F 0 "#GND_0130" H 10200 6600 20 0000 C CNN F 1 "+GND" H 10200 6530 30 0000 C CNN F 2 "" H 10200 6600 70 0000 C CNN F 3 "" H 10200 6600 70 0000 C CNN 1 10200 6600 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_035 U 1 1 58023EFD P 3100 3300 F 0 "#VCCO_3V3_035" H 3100 3300 20 0000 C CNN F 1 "+VCCO_3V3" H 3100 3230 30 0000 C CNN F 2 "" H 3100 3300 70 0000 C CNN F 3 "" H 3100 3300 70 0000 C CNN 1 3100 3300 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_036 U 1 1 58023EFC P 8200 3400 F 0 "#VCCO_3V3_036" H 8200 3400 20 0000 C CNN F 1 "+VCCO_3V3" H 8200 3330 30 0000 C CNN F 2 "" H 8200 3400 70 0000 C CNN F 3 "" H 8200 3400 70 0000 C CNN 1 8200 3400 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_037 U 1 1 58023EFB P 8200 5300 F 0 "#VCCO_3V3_037" H 8200 5300 20 0000 C CNN F 1 "+VCCO_3V3" H 8200 5230 30 0000 C CNN F 2 "" H 8200 5300 70 0000 C CNN F 3 "" H 8200 5300 70 0000 C CNN 1 8200 5300 1 0 0 -1 $EndComp $Comp L power:GND #GND_0131 U 1 1 58023EFA P 10300 8200 F 0 "#GND_0131" H 10300 8200 20 0000 C CNN F 1 "+GND" H 10300 8130 30 0000 C CNN F 2 "" H 10300 8200 70 0000 C CNN F 3 "" H 10300 8200 70 0000 C CNN 1 10300 8200 1 0 0 -1 $EndComp Wire Wire Line 8200 4400 8200 4700 Wire Wire Line 9400 4300 9400 4700 Wire Wire Line 9500 4300 9400 4300 Wire Wire Line 9500 4000 9400 4000 Wire Wire Line 9400 4000 9400 4300 Wire Wire Line 10200 4300 10100 4300 Wire Wire Line 10200 4300 10200 4700 Wire Wire Line 10200 4000 10100 4000 Wire Wire Line 10200 4000 10200 4300 Wire Wire Line 8200 6300 8200 6600 Wire Wire Line 9400 6200 9400 6600 Wire Wire Line 9500 6200 9400 6200 Wire Wire Line 9500 5900 9400 5900 Wire Wire Line 9400 5900 9400 6200 Wire Wire Line 10200 6200 10100 6200 Wire Wire Line 10200 6200 10200 6600 Wire Wire Line 10200 5900 10100 5900 Wire Wire Line 10200 5900 10200 6200 Wire Wire Line 10300 8000 10300 8200 Wire Wire Line 10300 8000 10200 8000 Wire Wire Line 10300 7900 10000 7900 Wire Wire Line 10300 7900 10300 8000 Wire Wire Line 10300 7800 10200 7800 Wire Wire Line 10300 7700 10000 7700 Wire Wire Line 10300 7700 10300 7800 Wire Wire Line 10300 7800 10300 7900 Wire Wire Line 3100 3500 2900 3500 Wire Wire Line 3100 3500 3100 3600 Wire Wire Line 3100 3600 3100 3700 Wire Wire Line 3100 3700 3100 3800 Wire Wire Line 3100 3800 3100 3900 Wire Wire Line 3100 3900 2900 3900 Wire Wire Line 3100 3800 2900 3800 Wire Wire Line 3100 3700 2900 3700 Wire Wire Line 3100 3600 2900 3600 Wire Wire Line 3100 3300 3100 3500 Wire Wire Line 3100 4000 2900 4000 Wire Wire Line 3100 3900 3100 4000 Wire Wire Line 9400 3600 8200 3600 Wire Wire Line 8200 3400 8200 3600 Wire Wire Line 8200 3600 8200 4100 Wire Wire Line 9500 3900 9400 3900 Wire Wire Line 9400 3800 9400 3900 Wire Wire Line 9400 3600 9400 3800 Wire Wire Line 10200 3800 10100 3800 Wire Wire Line 10200 3600 10200 3800 Wire Wire Line 10200 3600 9400 3600 Wire Wire Line 10200 3900 10100 3900 Wire Wire Line 10200 3800 10200 3900 Wire Wire Line 9500 3800 9400 3800 Wire Wire Line 9400 5500 8200 5500 Wire Wire Line 8200 5300 8200 5500 Wire Wire Line 8200 5500 8200 6000 Wire Wire Line 9500 5800 9400 5800 Wire Wire Line 9400 5700 9400 5800 Wire Wire Line 9400 5500 9400 5700 Wire Wire Line 10200 5700 10100 5700 Wire Wire Line 10200 5500 10200 5700 Wire Wire Line 10200 5500 9400 5500 Wire Wire Line 10200 5800 10100 5800 Wire Wire Line 10200 5700 10200 5800 Wire Wire Line 9500 5700 9400 5700 Wire Wire Line 4100 7300 2900 7300 Text GLabel 4100 7300 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_7 Wire Wire Line 4100 4300 2900 4300 Text GLabel 4100 4300 2 48 UnSpc ~ 0 FPGA_IRQ_N_0 Wire Wire Line 4100 4400 2900 4400 Text GLabel 4100 4400 2 48 UnSpc ~ 0 FPGA_IRQ_N_1 Wire Wire Line 4100 4500 2900 4500 Text GLabel 4100 4500 2 48 UnSpc ~ 0 FPGA_IRQ_N_2 Wire Wire Line 4100 4600 2900 4600 Text GLabel 4100 4600 2 48 UnSpc ~ 0 FPGA_IRQ_N_3 Wire Wire Line 4100 4700 2900 4700 Text GLabel 4100 4900 2 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 9500 4100 8600 4100 Text GLabel 8600 4100 0 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 4100 4800 2900 4800 Text GLabel 4100 4800 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 11000 4100 10100 4100 Text GLabel 11000 4100 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 4100 4900 2900 4900 Text GLabel 4100 6000 2 48 BiDi ~ 0 FPGA_GPIO_A_2 Wire Wire Line 9500 4200 8600 4200 Text GLabel 8600 4200 0 48 BiDi ~ 0 FPGA_GPIO_A_2 Text GLabel 4100 6100 2 48 BiDi ~ 0 FPGA_GPIO_A_3 Wire Wire Line 11000 4200 10100 4200 Text GLabel 11000 4200 2 48 BiDi ~ 0 FPGA_GPIO_A_3 Text GLabel 4100 5600 2 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 9500 4400 8600 4400 Text GLabel 8600 4400 0 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 4100 5200 2900 5200 Text GLabel 4100 5700 2 48 BiDi ~ 0 FPGA_GPIO_A_5 Wire Wire Line 11000 4400 10100 4400 Text GLabel 11000 4400 2 48 BiDi ~ 0 FPGA_GPIO_A_5 Text GLabel 4100 5800 2 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 9500 4500 8600 4500 Text GLabel 8600 4500 0 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 4100 5400 2900 5400 Text GLabel 4100 5400 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 11000 4500 10100 4500 Text GLabel 11000 4500 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 4100 5500 2900 5500 Text GLabel 4100 5900 2 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 9500 6000 8600 6000 Text GLabel 8600 6000 0 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 4100 5600 2900 5600 Text GLabel 4100 4700 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 11000 6000 10100 6000 Text GLabel 11000 6000 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 4100 5700 2900 5700 Text GLabel 4100 5500 2 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 9500 6100 8600 6100 Text GLabel 8600 6100 0 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 4100 5800 2900 5800 Text GLabel 4100 5200 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 11000 6100 10100 6100 Text GLabel 11000 6100 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 4100 5900 2900 5900 Text GLabel 4100 6600 2 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 9500 6300 8600 6300 Text GLabel 8600 6300 0 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 4100 6000 2900 6000 Text GLabel 4100 8300 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 11000 6300 10100 6300 Text GLabel 11000 6300 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 4100 6100 2900 6100 Text GLabel 4100 7900 2 48 BiDi ~ 0 FPGA_GPIO_B_6 Wire Wire Line 9500 6400 8600 6400 Text GLabel 8600 6400 0 48 BiDi ~ 0 FPGA_GPIO_B_6 Text GLabel 4100 8000 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 11000 6400 10100 6400 Text GLabel 11000 6400 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 4100 6400 2900 6400 Text GLabel 4100 6400 2 48 UnSpc ~ 0 FPGA_GCLK Wire Wire Line 8890 7800 8300 7800 Text GLabel 8300 7800 0 48 Input ~ 0 FPGA_GPIO_LED_2 Wire Wire Line 9200 7700 8300 7700 Text GLabel 8300 7700 0 48 Input ~ 0 FPGA_GPIO_LED_3 Wire Wire Line 8890 8000 8300 8000 Text GLabel 8300 8000 0 48 Input ~ 0 FPGA_GPIO_LED_0 Wire Wire Line 9200 7900 8300 7900 Text GLabel 8300 7900 0 48 Input ~ 0 FPGA_GPIO_LED_1 Wire Wire Line 9900 8000 9290 8000 Wire Wire Line 9700 7900 9600 7900 Wire Wire Line 9900 7800 9290 7800 Wire Wire Line 9700 7700 9600 7700 Wire Wire Line 4100 6300 2900 6300 Text GLabel 4100 6300 2 48 Output ~ 0 FPGA_ENTROPY_DISABLE Wire Wire Line 4100 7400 2900 7400 Text GLabel 4100 7400 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_6 Wire Wire Line 4100 7500 2900 7500 Text GLabel 4100 7500 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_5 Wire Wire Line 4100 6600 2900 6600 Wire Wire Line 4100 7900 2900 7900 Wire Wire Line 4100 8000 2900 8000 Wire Wire Line 4100 8300 2900 8300 $Comp L Cryptech_Alpha:MA08-2 SV2 U 1 1 58023EF9 P 9800 4100 F 0 "SV2" H 9980 4730 60 0000 R TNN F 1 "PLD-16" H 9800 4100 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:PLD-16" H 9980 4730 60 0001 C CNN F 3 "" H 9800 4100 50 0001 C CNN F 4 "-" H 9800 4100 50 0001 C CNN "Manufacturer" F 5 "0.1\" (2.54mm) 2x8 Pin Header" H 9800 4100 50 0001 C CNN "Comment" 1 9800 4100 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R99 U 1 1 58023EF8 P 9400 7700 F 0 "R99" H 9490 7520 60 0000 R TNN F 1 "330" H 9500 7610 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 9500 7610 60 0001 C CNN F 3 "" H 9500 7610 60 0001 C CNN F 4 "5%" H 9400 7700 50 0001 C CNN "Tolerance" 1 9400 7700 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R98 U 1 1 58023EF7 P 9090 7800 F 0 "R98" H 9220 7520 60 0000 R TNN F 1 "330" H 9230 7610 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 9230 7610 60 0001 C CNN F 3 "" H 9230 7610 60 0001 C CNN F 4 "5%" H 9090 7800 50 0001 C CNN "Tolerance" 1 9090 7800 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R64 U 1 1 58023EF6 P 9400 7900 F 0 "R64" H 9080 7510 60 0000 R TNN F 1 "330" H 9090 7600 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 9090 7600 60 0001 C CNN F 3 "" H 9090 7600 60 0001 C CNN F 4 "5%" H 9400 7900 50 0001 C CNN "Tolerance" 1 9400 7900 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R100 U 1 1 58023EF5 P 9090 8000 F 0 "R100" H 9180 8170 60 0000 R TNN F 1 "330" H 9190 8260 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 9190 8260 60 0001 C CNN F 3 "" H 9190 8260 60 0001 C CNN F 4 "5%" H 9090 8000 50 0001 C CNN "Tolerance" 1 9090 8000 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:MA08-2 SV3 U 1 1 58023EF4 P 9800 6000 F 0 "SV3" H 9980 6630 60 0000 R TNN F 1 "PLD-16" H 9800 6000 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:PLD-16" H 9980 6630 60 0001 C CNN F 3 "" H 9800 6000 50 0001 C CNN F 4 "-" H 9800 6000 50 0001 C CNN "Manufacturer" F 5 "0.1\" (2.54mm) 2x8 Pin Header" H 9800 6000 50 0001 C CNN "Comment" 1 9800 6000 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:C-EUC0402 C121 U 1 1 58023EF3 P 8200 4200 F 0 "C121" H 8280 4010 60 0000 L BNN F 1 "0.1uF" H 8320 4110 60 0000 L BNN F 2 "Cryptech_Alpha_Footprints:C_0402" H 8320 4110 60 0001 C CNN F 3 "" H 8320 4110 60 0001 C CNN F 4 "10%" H 8320 4110 60 0000 C CNN "Tolerance" F 5 "25V" H 8320 4110 60 0000 C CNN "Voltage" F 6 "X7R" H 8320 4110 60 0000 C CNN "Dielectric" 1 8200 4200 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:C-EUC0402 C122 U 1 1 58023EF2 P 8200 6100 F 0 "C122" H 8280 5910 60 0000 L BNN F 1 "0.1uF" H 8330 6010 60 0000 L BNN F 2 "Cryptech_Alpha_Footprints:C_0402" H 8330 6010 60 0001 C CNN F 3 "" H 8330 6010 60 0000 C CNN F 4 "10%" H 8330 6010 60 0000 C CNN "Tolerance" F 5 "25V" H 8330 6010 60 0000 C CNN "Voltage" F 6 "X7R" H 8330 6010 60 0000 C CNN "Dielectric" 1 8200 6100 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED17 U 1 1 58023EF1 P 10000 8000 F 0 "LED17" V 9960 7626 60 0000 R TNN F 1 "LTST-C191TBKT" V 9960 7320 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 9960 7320 60 0001 C CNN F 3 "" H 9960 7320 60 0000 C CNN F 4 "Lite-On" V 10000 8000 50 0001 C CNN "Manufacturer" F 5 "Blue" V 10000 8000 50 0001 C CNN "Comment" 1 10000 8000 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED15 U 1 1 58023EF0 P 9800 7900 F 0 "LED15" V 9760 7326 60 0000 R TNN F 1 "LTST-C191KGKT" V 9760 7020 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 9760 7020 60 0001 C CNN F 3 "" H 9760 7020 60 0000 C CNN F 4 "Lite-On" V 9800 7900 50 0001 C CNN "Manufacturer" F 5 "Green" V 9800 7900 50 0001 C CNN "Comment" 1 9800 7900 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED16 U 1 1 58023EEF P 10000 7800 F 0 "LED16" V 9960 7426 60 0000 R TNN F 1 "LTST-C191KSKT" V 9960 7130 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 9960 7130 60 0001 C CNN F 3 "" H 9960 7130 60 0000 C CNN F 4 "Lite-On" V 10000 7800 50 0001 C CNN "Manufacturer" F 5 "Yellow" V 10000 7800 50 0001 C CNN "Comment" 1 10000 7800 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED14 U 1 1 58023EEE P 9800 7700 F 0 "LED14" V 9760 7126 60 0000 R TNN F 1 "LTST-C191KRKT" V 9760 6820 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 9760 6820 60 0001 C CNN F 3 "" H 9760 6820 60 0000 C CNN F 4 "Lite-On" V 9800 7700 50 0001 C CNN "Manufacturer" F 5 "Red" V 9800 7700 50 0001 C CNN "Comment" 1 9800 7700 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:XC7A200TFBG484_NEW U13 U 5 1 58023EED P 2700 6200 F 0 "U13" H 2290 3190 60 0000 L BNN F 1 "XC7A200T-1FBG484C" H 2700 6200 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 2290 3190 60 0001 C CNN F 3 "" H 2700 6200 50 0001 C CNN 5 2700 6200 1 0 0 -1 $EndComp NoConn ~ 2900 4100 NoConn ~ 2900 4200 NoConn ~ 2900 5000 NoConn ~ 2900 5100 NoConn ~ 2900 6700 NoConn ~ 2900 6900 NoConn ~ 2900 7600 NoConn ~ 2900 7700 NoConn ~ 2900 7800 NoConn ~ 2900 8100 NoConn ~ 2900 8200 NoConn ~ 2900 8400 NoConn ~ 2900 8500 NoConn ~ 2900 8600 NoConn ~ 2900 8700 NoConn ~ 2900 8800 NoConn ~ 2900 8900 NoConn ~ 2900 9000 NoConn ~ 2900 5300 Text GLabel 4100 6200 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_4 NoConn ~ 2900 7200 Wire Wire Line 2900 6200 4100 6200 Text GLabel 4100 7000 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_3 Text GLabel 4100 7100 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_2 Wire Wire Line 2900 6500 4100 6500 Wire Wire Line 2900 6800 4100 6800 Wire Wire Line 2900 7000 4100 7000 Wire Wire Line 2900 7100 4100 7100 Text GLabel 4100 6500 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_1 Text GLabel 4100 6800 2 48 UnSpc ~ 0 ICE40_GPIO_FPGA_0 Connection ~ 3100 3500 Connection ~ 3100 3600 Connection ~ 3100 3700 Connection ~ 3100 3800 Connection ~ 3100 3900 Connection ~ 8200 3600 Connection ~ 8200 5500 Connection ~ 9400 3600 Connection ~ 9400 3800 Connection ~ 9400 4300 Connection ~ 9400 5500 Connection ~ 9400 5700 Connection ~ 9400 6200 Connection ~ 10200 3800 Connection ~ 10200 4300 Connection ~ 10200 5700 Connection ~ 10200 6200 Connection ~ 10300 7800 Connection ~ 10300 7900 Connection ~ 10300 8000 $EndSCHEMATC