From 602b95720caed80004ece2c35374cb97197b0ee0 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Thu, 23 Apr 2020 18:14:52 +0300 Subject: Copy of rev.04 project as-is after Fredrik's conversion script. --- KiCAD/Cryptech Alpha.kicad_pcb | 30530 ++++++++++++++++++ KiCAD/Cryptech Alpha.kicad_pcb-bak | 30742 +++++++++++++++++++ KiCAD/Cryptech Alpha.pro | 30 + KiCAD/Cryptech Alpha.sch | 232 + KiCAD/Cryptech_Alpha.lib | 3156 ++ KiCAD/footprints.pretty/694106301002.kicad_mod | 22 + KiCAD/footprints.pretty/ASF.kicad_mod | 13 + KiCAD/footprints.pretty/B1,27.kicad_mod | 10 + .../BGA484C100P22X22_2300X2300X254.kicad_mod | 498 + KiCAD/footprints.pretty/CRYSTAL_3.2X2.5.kicad_mod | 13 + KiCAD/footprints.pretty/C_0402.kicad_mod | 21 + KiCAD/footprints.pretty/C_0603.kicad_mod | 21 + KiCAD/footprints.pretty/C_0805.kicad_mod | 21 + KiCAD/footprints.pretty/C_1210.kicad_mod | 21 + KiCAD/footprints.pretty/C_D.kicad_mod | 21 + KiCAD/footprints.pretty/DEFAULT.kicad_mod | 19 + KiCAD/footprints.pretty/HDR1X10.kicad_mod | 19 + KiCAD/footprints.pretty/LQFP-32.kicad_mod | 51 + KiCAD/footprints.pretty/LQFP-48.kicad_mod | 67 + KiCAD/footprints.pretty/L_0603.kicad_mod | 21 + KiCAD/footprints.pretty/L_1206.kicad_mod | 21 + KiCAD/footprints.pretty/NDY.kicad_mod | 21 + KiCAD/footprints.pretty/PLD-16.kicad_mod | 35 + KiCAD/footprints.pretty/PLD-6.kicad_mod | 25 + KiCAD/footprints.pretty/PLS-2.kicad_mod | 21 + KiCAD/footprints.pretty/PLS-3.kicad_mod | 22 + KiCAD/footprints.pretty/PLS-6.kicad_mod | 25 + KiCAD/footprints.pretty/PLS-8.kicad_mod | 27 + KiCAD/footprints.pretty/QFN38.kicad_mod | 48 + KiCAD/footprints.pretty/QFN68.kicad_mod | 79 + KiCAD/footprints.pretty/RCLAMP0502A.kicad_mod | 15 + KiCAD/footprints.pretty/README.TXT | 5 + KiCAD/footprints.pretty/R_0402.kicad_mod | 21 + KiCAD/footprints.pretty/SO08.kicad_mod | 17 + KiCAD/footprints.pretty/SO20W.kicad_mod | 29 + .../footprints.pretty/SOIC127P600X175-8N.kicad_mod | 17 + KiCAD/footprints.pretty/SOT-23-5.kicad_mod | 24 + KiCAD/footprints.pretty/SOT-23.kicad_mod | 22 + KiCAD/footprints.pretty/TACTILE_SWITCH.kicad_mod | 15 + KiCAD/footprints.pretty/TSOT-8-23.kicad_mod | 17 + .../TSQFP50P3000X3000X160-208N.kicad_mod | 222 + .../TSSOP50P1180X120-86N.kicad_mod | 100 + KiCAD/footprints.pretty/USB-MINIB.kicad_mod | 30 + KiCAD/footprints.pretty/VD_0603.kicad_mod | 16 + .../WE-SHC_36103205_NO_CREAM.kicad_mod | 25 + KiCAD/footprints.pretty/XTAL3215.kicad_mod | 11 + KiCAD/fp-info-cache | 1 + KiCAD/fp-lib-table | 3 + KiCAD/rev02_00.sch | 26 + KiCAD/rev02_01.sch | 865 + KiCAD/rev02_02.sch | 388 + KiCAD/rev02_03.sch | 489 + KiCAD/rev02_04.sch | 752 + KiCAD/rev02_05.sch | 674 + KiCAD/rev02_06.sch | 1434 + KiCAD/rev02_07.sch | 168 + KiCAD/rev02_08.sch | 245 + KiCAD/rev02_09.sch | 1098 + KiCAD/rev02_10.sch | 1102 + KiCAD/rev02_11.sch | 747 + KiCAD/rev02_12.sch | 430 + KiCAD/rev02_13.sch | 621 + KiCAD/rev02_14.sch | 190 + KiCAD/rev02_15.sch | 583 + KiCAD/rev02_16.sch | 214 + KiCAD/rev02_17.sch | 372 + KiCAD/rev02_18.sch | 815 + KiCAD/rev02_19.sch | 631 + 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3 + KiCAD/wrlshp/ECAF1ED8-FCC0.wrl | 3 + KiCAD/wrlshp/F26EE9BE-B6B0.wrl | 3 + KiCAD/wrlshp/PJ-002A.wrl | 5114 +++ KiCAD/wrlshp/PLS-8.wrl | 6393 ++++ KiCAD/wrlshp/SW3dPS-0402 SMD Capacitor.wrl | 4878 +++ KiCAD/wrlshp/SW3dPS-0402 SMD Resistor.wrl | 2290 ++ KiCAD/wrlshp/SW3dPS-0603 SMD Capacitor.wrl | 3101 ++ KiCAD/wrlshp/SW3dPS-0805 SMD Capacitor.wrl | 7474 +++++ KiCAD/wrlshp/SW3dPS-3-lead sot23-3.wrl | 3544 +++ KiCAD/wrlshp/SW3dPS-CAPC3225.wrl | 279 + KiCAD/wrlshp/SW3dPS-LQFP48.wrl | 15003 +++++++++ KiCAD/wrlshp/SW3dPS-cap_d.wrl | 862 + KiCAD/wrlshp/User Library-Header1x2.wrl | 1600 + KiCAD/wrlshp/User Library-SOT23-5-1.wrl | 6559 ++++ KiCAD/wrlshp/User Library-V0603HD.wrl | 7253 +++++ KiCAD/wrlshp/User Library-V1206HD.wrl | 3627 +++ KiCAD/wrlshp/User Library-sot358-1.wrl | 21215 +++++++++++++ KiCAD/wrlshp/c-1734035-2-e-3d.wrl | 7670 +++++ KiCAD/wrlshp/pin_header_a-sl254-ea-g06mp1.wrl | 6267 ++++ KiCAD/wrlshp/pin_header_aw_108_03-t.wrl | 2113 ++ KiCAD/wrlshp/pin_header_awl254-dg-g06d.wrl | 3410 ++ KiCAD/wrlshp/pin_header_awl254-dg-g16d.wrl | 8591 ++++++ 119 files changed, 199997 insertions(+) create mode 100644 KiCAD/Cryptech Alpha.kicad_pcb create mode 100644 KiCAD/Cryptech Alpha.kicad_pcb-bak create mode 100644 KiCAD/Cryptech Alpha.pro create mode 100644 KiCAD/Cryptech Alpha.sch create mode 100644 KiCAD/Cryptech_Alpha.lib create mode 100644 KiCAD/footprints.pretty/694106301002.kicad_mod create mode 100644 KiCAD/footprints.pretty/ASF.kicad_mod create mode 100644 KiCAD/footprints.pretty/B1,27.kicad_mod create mode 100644 KiCAD/footprints.pretty/BGA484C100P22X22_2300X2300X254.kicad_mod create mode 100644 KiCAD/footprints.pretty/CRYSTAL_3.2X2.5.kicad_mod create mode 100644 KiCAD/footprints.pretty/C_0402.kicad_mod create mode 100644 KiCAD/footprints.pretty/C_0603.kicad_mod create mode 100644 KiCAD/footprints.pretty/C_0805.kicad_mod create mode 100644 KiCAD/footprints.pretty/C_1210.kicad_mod create mode 100644 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create mode 100644 KiCAD/wrlshp/AF13F747-700F.wrl create mode 100644 KiCAD/wrlshp/B280C847-2543.wrl create mode 100644 KiCAD/wrlshp/B3089A96-FA19.wrl create mode 100644 KiCAD/wrlshp/D87FE1D2-D8B7.wrl create mode 100644 KiCAD/wrlshp/ECAF1ED8-FCC0.wrl create mode 100644 KiCAD/wrlshp/F26EE9BE-B6B0.wrl create mode 100644 KiCAD/wrlshp/PJ-002A.wrl create mode 100644 KiCAD/wrlshp/PLS-8.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-0402 SMD Capacitor.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-0402 SMD Resistor.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-0603 SMD Capacitor.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-0805 SMD Capacitor.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-3-lead sot23-3.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-CAPC3225.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-LQFP48.wrl create mode 100644 KiCAD/wrlshp/SW3dPS-cap_d.wrl create mode 100644 KiCAD/wrlshp/User Library-Header1x2.wrl create mode 100644 KiCAD/wrlshp/User Library-SOT23-5-1.wrl create mode 100644 KiCAD/wrlshp/User Library-V0603HD.wrl create mode 100644 KiCAD/wrlshp/User Library-V1206HD.wrl create mode 100644 KiCAD/wrlshp/User Library-sot358-1.wrl create mode 100644 KiCAD/wrlshp/c-1734035-2-e-3d.wrl create mode 100644 KiCAD/wrlshp/pin_header_a-sl254-ea-g06mp1.wrl create mode 100644 KiCAD/wrlshp/pin_header_aw_108_03-t.wrl create mode 100644 KiCAD/wrlshp/pin_header_awl254-dg-g06d.wrl create mode 100644 KiCAD/wrlshp/pin_header_awl254-dg-g16d.wrl (limited to 'KiCAD') diff --git a/KiCAD/Cryptech Alpha.kicad_pcb b/KiCAD/Cryptech Alpha.kicad_pcb new file mode 100644 index 0000000..a57e734 --- /dev/null +++ b/KiCAD/Cryptech Alpha.kicad_pcb @@ -0,0 +1,30530 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3") + + (general + (thickness 1.6) + (drawings 6691) + (tracks 9160) + (zones 0) + (modules 386) + (nets 304) + ) + + (page A4) + (layers + (0 F.Cu signal hide) + (1 In1.Cu power hide) + (2 In2.Cu mixed hide) + (3 In3.Cu power hide) + (4 In4.Cu power hide) + (5 In5.Cu mixed hide) + (6 In6.Cu power hide) + (31 B.Cu signal hide) + (32 B.Adhes user hide) + (33 F.Adhes user hide) + (34 B.Paste user hide) + (35 F.Paste user hide) + (36 B.SilkS user hide) + (37 F.SilkS user hide) + (38 B.Mask user hide) + (39 F.Mask user hide) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) + (42 Eco1.User user hide) + (43 Eco2.User user hide) + (44 Edge.Cuts user hide) + (45 Margin user hide) + (46 B.CrtYd user hide) + (47 F.CrtYd user hide) + (48 B.Fab user hide) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.125) + (zone_clearance 0.0144) + (zone_45_only no) + (trace_min 0.15) + (via_size 0.889) + (via_drill 0.25) + (via_min_size 0.5) + (via_min_drill 0.25) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (edge_width 0.1) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.5 1.5) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements 7FFED33F) + (pcbplotparams + (layerselection 0x01000_7fffff80) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "C:/Users/Paul/YandexDisk/DEV/CrypTech/git/user/shatov/alpha_rev04/NewGerbers/")) + ) + + (net 0 "") + (net 1 Net1) + (net 2 DM_P) + (net 3 DM_N) + (net 4 3V3_BATT) + (net 5 15V_LDO_ENABLE) + (net 6 15V_STABLE) + (net 7 GND) + (net 8 "Net-(C15-Pad2)") + (net 9 AMPLIFIED) + (net 10 ARM_FPGA_CFG_CS_N) + (net 11 ARM_FPGA_CFG_MISO) + (net 12 ARM_FPGA_CFG_MOSI) + (net 13 ARM_FPGA_CFG_SCLK) + (net 14 ARM_LED1) + (net 15 ARM_LED2) + (net 16 ARM_LED3) + (net 17 ARM_LED4) + (net 18 AVR_GPIO_0) + (net 19 AVR_GPIO_1) + (net 20 AVR_GPIO_2) + (net 21 AVR_GPIO_3) + (net 22 AVR_GPIO_4) + (net 23 AVR_GPIO_5) + (net 24 AVR_GPIO_6) + (net 25 AVR_GPIO_7) + (net 26 AVR_GPIO_ARM_0) + (net 27 AVR_GPIO_ARM_1) + (net 28 AVR_GPIO_ARM_2) + (net 29 AVR_GPIO_ARM_3) + (net 30 AVR_GPIO_FPGA_0) + (net 31 AVR_GPIO_FPGA_1) + (net 32 AVR_GPIO_FPGA_2) + (net 33 AVR_GPIO_FPGA_3) + (net 34 AVR_LED1) + (net 35 AVR_LED2) + (net 36 AVR_LED3) + (net 37 AVR_LED4) + (net 38 AVR_PANIC) + (net 39 AVR_RESET) + (net 40 BOOT0) + (net 41 D1_N) + (net 42 D1_P) + (net 43 DIGITIZED_NOISE) + (net 44 FMC_A0) + (net 45 FMC_A1) + (net 46 FMC_A2) + (net 47 FMC_A3) + (net 48 FMC_A4) + (net 49 FMC_A5) + (net 50 FMC_A6) + (net 51 FMC_A7) + (net 52 FMC_A8) + (net 53 FMC_A9) + (net 54 FMC_A10) + (net 55 FMC_A11) + (net 56 FMC_A12) + (net 57 FMC_A13) + (net 58 FMC_A14) + (net 59 FMC_A15) + (net 60 FMC_A16) + (net 61 FMC_A17) + (net 62 FMC_A18) + (net 63 FMC_A19) + (net 64 FMC_A20) + (net 65 FMC_A21) + (net 66 FMC_A22) + (net 67 FMC_A23) + (net 68 FMC_A24) + (net 69 FMC_A25) + (net 70 FMC_CLK) + (net 71 FMC_D0) + (net 72 FMC_D1) + (net 73 FMC_D2) + (net 74 FMC_D3) + (net 75 FMC_D4) + (net 76 FMC_D5) + (net 77 FMC_D6) + (net 78 FMC_D7) + (net 79 FMC_D8) + (net 80 FMC_D9) + (net 81 FMC_D10) + (net 82 FMC_D11) + (net 83 FMC_D12) + (net 84 FMC_D13) + (net 85 FMC_D14) + (net 86 FMC_D15) + (net 87 FMC_D16) + (net 88 FMC_D17) + (net 89 FMC_D18) + (net 90 FMC_D19) + (net 91 FMC_D20) + (net 92 FMC_D21) + (net 93 FMC_D22) + (net 94 FMC_D23) + (net 95 FMC_D24) + (net 96 FMC_D25) + (net 97 FMC_D26) + (net 98 FMC_D27) + (net 99 FMC_D28) + (net 100 FMC_D29) + (net 101 FMC_D30) + (net 102 FMC_D31) + (net 103 FMC_NBL0) + (net 104 FMC_NBL1) + (net 105 FMC_NBL2) + (net 106 FMC_NBL3) + (net 107 FMC_NE1) + (net 108 FMC_NL) + (net 109 FMC_NOE) + (net 110 FMC_NWAIT) + (net 111 FMC_NWE) + (net 112 FMC_SDCKE0) + (net 113 FMC_SDCKE1) + (net 114 FMC_SDCLK) + (net 115 FMC_SDNCAS) + (net 116 FMC_SDNE0) + (net 117 FMC_SDNE1) + (net 118 FMC_SDNRAS) + (net 119 FMC_SDNWE) + (net 120 FPGA_CFG_CS_N1) + (net 121 FPGA_CFG_CS_N) + (net 122 FPGA_CFG_CTRL_ARM_ENA) + (net 123 FPGA_CFG_CTRL_FPGA_DIS) + (net 124 FPGA_CFG_MISO1) + (net 125 FPGA_CFG_MISO) + (net 126 FPGA_CFG_MOSI1) + (net 127 FPGA_CFG_MOSI) + (net 128 FPGA_CFG_SCLK1) + (net 129 FPGA_CFG_SCLK) + (net 130 FPGA_DONE_INT) + (net 131 FPGA_DONE) + (net 132 FPGA_ENTROPY_DISABLE) + (net 133 FPGA_GCLK) + (net 134 FPGA_GPIO_A_0) + (net 135 FPGA_GPIO_A_1) + (net 136 FPGA_GPIO_A_2) + (net 137 FPGA_GPIO_A_3) + (net 138 FPGA_GPIO_A_4) + (net 139 FPGA_GPIO_A_5) + (net 140 FPGA_GPIO_A_6) + (net 141 FPGA_GPIO_A_7) + (net 142 FPGA_GPIO_B_0) + (net 143 FPGA_GPIO_B_1) + (net 144 FPGA_GPIO_B_2) + (net 145 FPGA_GPIO_B_3) + (net 146 FPGA_GPIO_B_4) + (net 147 FPGA_GPIO_B_5) + (net 148 FPGA_GPIO_B_6) + (net 149 FPGA_GPIO_B_7) + (net 150 FPGA_GPIO_LED_0) + (net 151 FPGA_GPIO_LED_1) + (net 152 FPGA_GPIO_LED_2) + (net 153 FPGA_GPIO_LED_3) + (net 154 FPGA_INIT_B_INT1) + (net 155 FPGA_INIT_B_INT) + (net 156 FPGA_INIT_B) + (net 157 FPGA_IRQ_N_0) + (net 158 FPGA_IRQ_N_1) + (net 159 FPGA_IRQ_N_2) + (net 160 FPGA_IRQ_N_3) + (net 161 FPGA_JTAG_TCK) + (net 162 FPGA_JTAG_TDI) + (net 163 FPGA_JTAG_TDO) + (net 164 FPGA_JTAG_TMS) + (net 165 FPGA_M0) + (net 166 FPGA_M1) + (net 167 FPGA_M2) + (net 168 FPGA_PROGRAM_B1) + (net 169 FPGA_PROGRAM_B) + (net 170 FPGA_PROM_CS_N) + (net 171 FPGA_PROM_MISO) + (net 172 FPGA_PROM_MOSI) + (net 173 FPGA_PROM_SCLK) + (net 174 FPGA_PROM_W_N) + (net 175 FPGA_VCCAUX_1V8) + (net 176 FPGA_VCCINT_1V0) + (net 177 FT_CTS) + (net 178 FT_DTR) + (net 179 FT_MGMT_CTS) + (net 180 FT_MGMT_DTR) + (net 181 FT_MGMT_RTS) + (net 182 FT_MGMT_RXD1) + (net 183 FT_MGMT_RXD) + (net 184 FT_MGMT_TXD1) + (net 185 FT_MGMT_TXD) + (net 186 FT_MGMT_VCC3V3) + (net 187 FT_MGMT_VPHY) + (net 188 FT_MGMT_VPLL) + (net 189 FT_MGMT_VREGIN) + (net 190 FT_REF1) + (net 191 FT_REF) + (net 192 FT_RESET1) + (net 193 FT_RESET) + (net 194 FT_RTS) + (net 195 FT_RXD1) + (net 196 FT_RXD) + (net 197 FT_TXD1) + (net 198 FT_TXD) + (net 199 FT_VCC3V3) + (net 200 FT_VCCA1) + (net 201 FT_VCCA) + (net 202 FT_VCCORE1) + (net 203 FT_VCCORE) + (net 204 FT_VPHY) + (net 205 FT_VPLL) + (net 206 FT_VREGIN) + (net 207 KSM_PROM_CS_N) + (net 208 KSM_PROM_MISO) + (net 209 KSM_PROM_MOSI) + (net 210 KSM_PROM_SCLK) + (net 211 MKM_AVR_CS_N) + (net 212 MKM_AVR_MISO) + (net 213 MKM_AVR_MOSI) + (net 214 MKM_AVR_SCK) + (net 215 MKM_CONTROL_AVR_ENA) + (net 216 MKM_CONTROL_FPGA_DIS) + (net 217 MKM_CS_N) + (net 218 MKM_FPGA_CS_N) + (net 219 MKM_FPGA_MISO) + (net 220 MKM_FPGA_MOSI) + (net 221 MKM_FPGA_SCK) + (net 222 MKM_MISO) + (net 223 MKM_MOSI) + (net 224 MKM_SCK) + (net 225 "Net-(C5-Pad1)") + (net 226 "Net-(C11-Pad1)") + (net 227 "Net-(C12-Pad2)") + (net 228 "Net-(C17-Pad2)") + (net 229 "Net-(C70-Pad2)") + (net 230 "Net-(C71-Pad2)") + (net 231 "Net-(C75-Pad2)") + (net 232 "Net-(C78-Pad2)") + (net 233 "Net-(C90-Pad2)") + (net 234 "Net-(C93-Pad2)") + (net 235 "Net-(C115-Pad1)") + (net 236 "Net-(C116-Pad1)") + (net 237 "Net-(C117-Pad1)") + (net 238 "Net-(C117-Pad2)") + (net 239 "Net-(C118-Pad1)") + (net 240 "Net-(C118-Pad2)") + (net 241 "Net-(C207-Pad1)") + (net 242 "Net-(C208-Pad1)") + (net 243 "Net-(C208-Pad2)") + (net 244 "Net-(IC1-Pad3)") + (net 245 "Net-(JP2-Pad2)") + (net 246 "Net-(LED1-Pad1)") + (net 247 "Net-(LED2-Pad1)") + (net 248 "Net-(LED3-Pad1)") + (net 249 "Net-(LED4-Pad1)") + (net 250 "Net-(LED9-Pad1)") + (net 251 "Net-(LED10-Pad1)") + (net 252 "Net-(LED11-Pad1)") + (net 253 "Net-(LED12-Pad1)") + (net 254 "Net-(LED13-Pad1)") + (net 255 "Net-(LED14-Pad1)") + (net 256 "Net-(LED15-Pad1)") + (net 257 "Net-(LED16-Pad1)") + (net 258 "Net-(LED17-Pad1)") + (net 259 "Net-(LED18-Pad1)") + (net 260 "Net-(LED18-Pad2)") + (net 261 "Net-(Q1-Pad1)") + (net 262 "Net-(Q5-Pad1)") + (net 263 "Net-(Q5-Pad3)") + (net 264 "Net-(R1-Pad1)") + (net 265 "Net-(R3-Pad2)") + (net 266 "Net-(R8-Pad1)") + (net 267 "Net-(R32-Pad2)") + (net 268 "Net-(R33-Pad2)") + (net 269 "Net-(R52-Pad1)") + (net 270 "Net-(R53-Pad2)") + (net 271 "Net-(R54-Pad1)") + (net 272 "Net-(R55-Pad2)") + (net 273 "Net-(R65-Pad1)") + (net 274 "Net-(R66-Pad1)") + (net 275 "Net-(R67-Pad1)") + (net 276 NOISE_IN) + (net 277 NOISE_OUT) + (net 278 NRST) + (net 279 OSC_IN) + (net 280 OSC_OUT) + (net 281 POK_VCCAUX) + (net 282 POK_VCCINT) + (net 283 POK_VCCO) + (net 284 PWR_18V) + (net 285 PWR_ENA_VCCAUX) + (net 286 PWR_ENA_VCCINT) + (net 287 PWR_ENA_VCCO) + (net 288 RAW_NOISE) + (net 289 RTC_MFP) + (net 290 RTC_SCL) + (net 291 RTC_SDA) + (net 292 SPI_A_TRISTATE) + (net 293 SPI_B_TRISTATE) + (net 294 SWDCLK) + (net 295 SWDIO) + (net 296 USB_MGMT_N) + (net 297 USB_MGMT_P) + (net 298 USB_N) + (net 299 USB_P) + (net 300 VCAP1) + (net 301 VCAP2) + (net 302 VCC_5V0) + (net 303 VCCO_3V3) + + (net_class Default "This is the default net class." + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net 15V_LDO_ENABLE) + (add_net 15V_STABLE) + (add_net 3V3_BATT) + (add_net AMPLIFIED) + (add_net ARM_FPGA_CFG_CS_N) + (add_net ARM_FPGA_CFG_MISO) + (add_net ARM_FPGA_CFG_MOSI) + (add_net ARM_FPGA_CFG_SCLK) + (add_net ARM_LED1) + (add_net ARM_LED2) + (add_net ARM_LED3) + (add_net ARM_LED4) + (add_net AVR_GPIO_0) + (add_net AVR_GPIO_1) + (add_net AVR_GPIO_2) + (add_net AVR_GPIO_3) + (add_net AVR_GPIO_4) + (add_net AVR_GPIO_5) + (add_net AVR_GPIO_6) + (add_net AVR_GPIO_7) + (add_net AVR_GPIO_ARM_0) + (add_net AVR_GPIO_ARM_1) + (add_net AVR_GPIO_ARM_2) + (add_net AVR_GPIO_ARM_3) + (add_net AVR_GPIO_FPGA_0) + (add_net AVR_GPIO_FPGA_1) + (add_net AVR_GPIO_FPGA_2) + (add_net AVR_GPIO_FPGA_3) + (add_net AVR_LED1) + (add_net AVR_LED2) + (add_net AVR_LED3) + (add_net AVR_LED4) + (add_net AVR_PANIC) + (add_net AVR_RESET) + (add_net BOOT0) + (add_net DIGITIZED_NOISE) + (add_net FPGA_CFG_CS_N) + (add_net FPGA_CFG_CS_N1) + (add_net FPGA_CFG_CTRL_ARM_ENA) + (add_net FPGA_CFG_CTRL_FPGA_DIS) + (add_net FPGA_CFG_MISO) + (add_net FPGA_CFG_MISO1) + (add_net FPGA_CFG_MOSI) + (add_net FPGA_CFG_MOSI1) + (add_net FPGA_CFG_SCLK) + (add_net FPGA_CFG_SCLK1) + (add_net FPGA_DONE) + (add_net FPGA_DONE_INT) + (add_net FPGA_ENTROPY_DISABLE) + (add_net FPGA_GCLK) + (add_net FPGA_GPIO_LED_0) + (add_net FPGA_GPIO_LED_1) + (add_net FPGA_GPIO_LED_2) + (add_net FPGA_GPIO_LED_3) + (add_net FPGA_INIT_B) + (add_net FPGA_INIT_B_INT) + (add_net FPGA_INIT_B_INT1) + (add_net FPGA_IRQ_N_0) + (add_net FPGA_IRQ_N_1) + (add_net FPGA_IRQ_N_2) + (add_net FPGA_IRQ_N_3) + (add_net FPGA_JTAG_TCK) + (add_net FPGA_JTAG_TDI) + (add_net FPGA_JTAG_TDO) + (add_net FPGA_JTAG_TMS) + (add_net FPGA_M0) + (add_net FPGA_M1) + (add_net FPGA_M2) + (add_net FPGA_PROGRAM_B) + (add_net FPGA_PROGRAM_B1) + (add_net FPGA_PROM_CS_N) + (add_net FPGA_PROM_MISO) + (add_net FPGA_PROM_MOSI) + (add_net FPGA_PROM_SCLK) + (add_net FPGA_PROM_W_N) + (add_net FPGA_VCCAUX_1V8) + (add_net FPGA_VCCINT_1V0) + (add_net FT_CTS) + (add_net FT_DTR) + (add_net FT_MGMT_CTS) + (add_net FT_MGMT_DTR) + (add_net FT_MGMT_RTS) + (add_net FT_MGMT_RXD) + (add_net FT_MGMT_RXD1) + (add_net FT_MGMT_TXD) + (add_net FT_MGMT_TXD1) + (add_net FT_MGMT_VCC3V3) + (add_net FT_MGMT_VPHY) + (add_net FT_MGMT_VPLL) + (add_net FT_MGMT_VREGIN) + (add_net FT_REF) + (add_net FT_REF1) + (add_net FT_RESET) + (add_net FT_RESET1) + (add_net FT_RTS) + (add_net FT_RXD) + (add_net FT_RXD1) + (add_net FT_TXD) + (add_net FT_TXD1) + (add_net FT_VCC3V3) + (add_net FT_VCCA) + (add_net FT_VCCA1) + (add_net FT_VCCORE) + (add_net FT_VCCORE1) + (add_net FT_VPHY) + (add_net FT_VPLL) + (add_net FT_VREGIN) + (add_net GND) + (add_net KSM_PROM_CS_N) + (add_net KSM_PROM_MISO) + (add_net KSM_PROM_MOSI) + (add_net KSM_PROM_SCLK) + (add_net MKM_AVR_CS_N) + (add_net MKM_AVR_MISO) + (add_net MKM_AVR_MOSI) + (add_net MKM_AVR_SCK) + (add_net MKM_CONTROL_AVR_ENA) + (add_net MKM_CONTROL_FPGA_DIS) + (add_net MKM_CS_N) + (add_net MKM_FPGA_CS_N) + (add_net MKM_FPGA_MISO) + (add_net MKM_FPGA_MOSI) + (add_net MKM_FPGA_SCK) + (add_net MKM_MISO) + (add_net MKM_MOSI) + (add_net MKM_SCK) + (add_net NOISE_IN) + (add_net NOISE_OUT) + (add_net NRST) + (add_net "Net-(C11-Pad1)") + (add_net "Net-(C115-Pad1)") + (add_net "Net-(C116-Pad1)") + (add_net "Net-(C117-Pad1)") + (add_net "Net-(C117-Pad2)") + (add_net "Net-(C118-Pad1)") + (add_net "Net-(C118-Pad2)") + (add_net "Net-(C12-Pad2)") + (add_net "Net-(C15-Pad2)") + (add_net "Net-(C17-Pad2)") + (add_net "Net-(C207-Pad1)") + (add_net "Net-(C208-Pad1)") + (add_net "Net-(C208-Pad2)") + (add_net "Net-(C5-Pad1)") + (add_net "Net-(C70-Pad2)") + (add_net "Net-(C71-Pad2)") + (add_net "Net-(C75-Pad2)") + (add_net "Net-(C78-Pad2)") + (add_net "Net-(C90-Pad2)") + (add_net "Net-(C93-Pad2)") + (add_net "Net-(IC1-Pad3)") + (add_net "Net-(JP2-Pad2)") + (add_net "Net-(LED1-Pad1)") + (add_net "Net-(LED10-Pad1)") + (add_net "Net-(LED11-Pad1)") + (add_net "Net-(LED12-Pad1)") + (add_net "Net-(LED13-Pad1)") + (add_net "Net-(LED14-Pad1)") + (add_net "Net-(LED15-Pad1)") + (add_net "Net-(LED16-Pad1)") + (add_net "Net-(LED17-Pad1)") + (add_net "Net-(LED18-Pad1)") + (add_net "Net-(LED18-Pad2)") + (add_net "Net-(LED2-Pad1)") + (add_net "Net-(LED3-Pad1)") + (add_net "Net-(LED4-Pad1)") + (add_net "Net-(LED9-Pad1)") + (add_net "Net-(Q1-Pad1)") + (add_net "Net-(Q5-Pad1)") + (add_net "Net-(Q5-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(R3-Pad2)") + (add_net "Net-(R32-Pad2)") + (add_net "Net-(R33-Pad2)") + (add_net "Net-(R52-Pad1)") + (add_net "Net-(R53-Pad2)") + (add_net "Net-(R54-Pad1)") + (add_net "Net-(R55-Pad2)") + (add_net "Net-(R65-Pad1)") + (add_net "Net-(R66-Pad1)") + (add_net "Net-(R67-Pad1)") + (add_net "Net-(R8-Pad1)") + (add_net Net1) + (add_net OSC_IN) + (add_net OSC_OUT) + (add_net POK_VCCAUX) + (add_net POK_VCCINT) + (add_net POK_VCCO) + (add_net PWR_18V) + (add_net PWR_ENA_VCCAUX) + (add_net PWR_ENA_VCCINT) + (add_net PWR_ENA_VCCO) + (add_net RAW_NOISE) + (add_net RTC_MFP) + (add_net RTC_SCL) + (add_net RTC_SDA) + (add_net SPI_A_TRISTATE) + (add_net SPI_B_TRISTATE) + (add_net SWDCLK) + (add_net SWDIO) + (add_net VCAP1) + (add_net VCAP2) + (add_net VCCO_3V3) + (add_net VCC_5V0) + ) + + (net_class FMC FMC + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FMC_A0) + (add_net FMC_A1) + (add_net FMC_A10) + (add_net FMC_A11) + (add_net FMC_A12) + (add_net FMC_A13) + (add_net FMC_A14) + (add_net FMC_A15) + (add_net FMC_A16) + (add_net FMC_A17) + (add_net FMC_A18) + (add_net FMC_A19) + (add_net FMC_A2) + (add_net FMC_A20) + (add_net FMC_A21) + (add_net FMC_A22) + (add_net FMC_A23) + (add_net FMC_A24) + (add_net FMC_A25) + (add_net FMC_A3) + (add_net FMC_A4) + (add_net FMC_A5) + (add_net FMC_A6) + (add_net FMC_A7) + (add_net FMC_A8) + (add_net FMC_A9) + (add_net FMC_CLK) + (add_net FMC_D0) + (add_net FMC_D1) + (add_net FMC_D10) + (add_net FMC_D11) + (add_net FMC_D12) + (add_net FMC_D13) + (add_net FMC_D14) + (add_net FMC_D15) + (add_net FMC_D16) + (add_net FMC_D17) + (add_net FMC_D18) + (add_net FMC_D19) + (add_net FMC_D2) + (add_net FMC_D20) + (add_net FMC_D21) + (add_net FMC_D22) + (add_net FMC_D23) + (add_net FMC_D24) + (add_net FMC_D25) + (add_net FMC_D26) + (add_net FMC_D27) + (add_net FMC_D28) + (add_net FMC_D29) + (add_net FMC_D3) + (add_net FMC_D30) + (add_net FMC_D31) + (add_net FMC_D4) + (add_net FMC_D5) + (add_net FMC_D6) + (add_net FMC_D7) + (add_net FMC_D8) + (add_net FMC_D9) + (add_net FMC_NBL0) + (add_net FMC_NBL1) + (add_net FMC_NBL2) + (add_net FMC_NBL3) + (add_net FMC_NE1) + (add_net FMC_NL) + (add_net FMC_NOE) + (add_net FMC_NWAIT) + (add_net FMC_NWE) + (add_net FMC_SDCKE0) + (add_net FMC_SDCKE1) + (add_net FMC_SDCLK) + (add_net FMC_SDNCAS) + (add_net FMC_SDNE0) + (add_net FMC_SDNE1) + (add_net FMC_SDNRAS) + (add_net FMC_SDNWE) + ) + + (net_class FPGA_GPIO FPGA_GPIO + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FPGA_GPIO_A_0) + (add_net FPGA_GPIO_A_1) + (add_net FPGA_GPIO_A_2) + (add_net FPGA_GPIO_A_3) + (add_net FPGA_GPIO_A_4) + (add_net FPGA_GPIO_A_5) + (add_net FPGA_GPIO_A_6) + (add_net FPGA_GPIO_A_7) + (add_net FPGA_GPIO_B_0) + (add_net FPGA_GPIO_B_1) + (add_net FPGA_GPIO_B_2) + (add_net FPGA_GPIO_B_3) + (add_net FPGA_GPIO_B_4) + (add_net FPGA_GPIO_B_5) + (add_net FPGA_GPIO_B_6) + (add_net FPGA_GPIO_B_7) + ) + + (net_class USB USB + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net D1_N) + (add_net D1_P) + (add_net DM_N) + (add_net DM_P) + (add_net USB_MGMT_N) + (add_net USB_MGMT_P) + (add_net USB_N) + (add_net USB_P) + ) + + (module Cryptech_Alpha_Footprints:_HDR1X10_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 31.5 6) + (path /539EEC0F) + (attr smd) + (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 10-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115)." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 19 AVR_GPIO_1)) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 25 AVR_GPIO_7)) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 24 AVR_GPIO_6)) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 23 AVR_GPIO_5)) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 22 AVR_GPIO_4)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 21 AVR_GPIO_3)) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 18 AVR_GPIO_0)) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.16075 -31.8) + (path /539EEC0F) + (attr smd) + (fp_text reference JP6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -0.00001 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -0.00001 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz -11.80693582267761 5.675121914768218 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -99.0854) + (path /539EEC0F) + (attr smd) + (fp_text reference C1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model 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value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24.4856 -62.8904) + (path /539EEC0F) + (attr smd) + (fp_text reference C207 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 241 "Net-(C207-Pad1)")) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 26.924 -62.8904) + (path /539EEC0F) + (attr smd) + (fp_text reference C208 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 243 "Net-(C208-Pad2)")) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 34.6964 -55.3466) + (path /539EEC0F) + (attr smd) + (fp_text reference C209 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR X5R 6.3V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz -1.249933981227875 0 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 34.7472 -62.4078) + (path /539EEC0F) + (attr smd) + (fp_text reference C210 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR X5R 6.3V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 1.5 90) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24.003 -63.0936) + (path /539EEC0F) + (attr smd) + (fp_text reference C211 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 14.8336 -47.2694) + (path /539EEC0F) + (attr smd) + (fp_text reference C212 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 287 PWR_ENA_VCCO)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30.9118 -76.327) + (path /539EEC0F) + (attr smd) + (fp_text reference C213 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 36 -14.5) + (path /539EEC0F) + (attr smd) + (fp_text reference C214 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 72.9 -16.7) + (path /539EEC0F) + (attr smd) + (fp_text reference C215 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_USB-MINIB_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 65 14.9) + (path /539EEC0F) + (attr smd) + (fp_text reference CN1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "mini USB type B Connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 42 D1_P)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 41 D1_N)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/23D50C2B-5C98.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_USB-MINIB_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 85 14.9) + (path /539EEC0F) + (attr smd) + (fp_text reference CN2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "mini USB type B Connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 3 DM_N)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 2 DM_P)) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/23D50C2B-5C98.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.8548 -89.1794) + (path /539EEC0F) + (attr smd) + (fp_text reference D1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (pad 2 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 8 "Net-(C15-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module 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Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 11.6078 -47.2694) + (path /539EEC0F) + (attr smd) + (fp_text reference D3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 281 POK_VCCAUX)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 287 PWR_ENA_VCCO)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 32.8168 -72.9234) + (path /539EEC0F) + (attr smd) + (fp_text reference D4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 2 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 282 POK_VCCINT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.3512 -15.7226) + (path /539EEC0F) + (attr smd) + (fp_text reference FB1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20.7528 -14.9192) + (path /539EEC0F) + (attr smd) + (fp_text reference FB2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 1 smd rect (at -0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 93.218 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 91.186 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.4528 -84.2772) + (path /539EEC0F) + (attr smd) + (fp_text reference FB5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 7.7978 -33.147) + (path /539EEC0F) + (attr smd) + (fp_text reference FB6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.624 -58.2168) + (path /539EEC0F) + (attr smd) + (fp_text reference FB7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad 1 smd rect (at 0 1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 33.1552 -51.028) + (path /539EEC0F) + (attr smd) + (fp_text reference IC1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 207 KSM_PROM_CS_N)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 208 KSM_PROM_MISO)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 244 "Net-(IC1-Pad3)")) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 KSM_PROM_SCLK)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 209 KSM_PROM_MOSI)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.356 -38.3524) + (path /539EEC0F) + (attr smd) + (fp_text reference IC2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 2 smd rect (at 5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 10 ARM_FPGA_CFG_CS_N)) + (pad 3 smd rect (at 5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_CFG_MISO)) + (pad 4 smd rect (at 5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 13 ARM_FPGA_CFG_SCLK)) + (pad 5 smd rect (at 5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 6 smd rect (at 5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 12 ARM_FPGA_CFG_MOSI)) + (pad 7 smd rect (at 5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 8 smd rect (at 5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 13 smd rect (at -5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 129 FPGA_CFG_SCLK)) + (pad 14 smd rect (at -5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 15 smd rect (at -5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 127 FPGA_CFG_MOSI)) + (pad 16 smd rect (at -5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 17 smd rect (at -5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 18 smd rect (at -5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 19 smd rect (at -5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 20 smd rect (at -5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 9 smd rect (at 5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 10 smd rect (at 5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at -5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 11 ARM_FPGA_CFG_MISO)) + (pad 11 smd rect (at -5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 121 FPGA_CFG_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5368 -25.2832) + (path /539EEC0F) + (attr smd) + (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.0918 -30.464) + (path /539EEC0F) + (attr smd) + (fp_text reference IC4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 11 smd rect (at 5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad 12 smd rect (at 4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 10 smd rect (at 5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 20 smd rect (at -5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at -4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 18 smd rect (at -3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 17 smd rect (at -1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 16 smd rect (at -0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 15 smd rect (at 0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad 14 smd rect (at 1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 13 smd rect (at 3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 221 MKM_FPGA_SCK)) + (pad 8 smd rect (at 3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 7 smd rect (at 1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 6 smd rect (at 0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 smd rect (at -0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 4 smd rect (at -1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 3 smd rect (at -3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 219 MKM_FPGA_MISO)) + (pad 2 smd rect (at -4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 1 smd rect (at -5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 51.816 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 41 D1_N)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 42 D1_P)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 69.1134 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 DM_P)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 3 DM_N)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.78379 -20.4216) + (path /539EEC0F) + (attr smd) + (fp_text reference J1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 278 NRST)) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 295 SWDIO)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 294 SWDCLK)) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl + (offset (xyz 0.006349999904632569 0.08635999870300293 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 360)) + ) + (model wrlshp/670BFB14-85C2.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.04639 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 206 FT_VREGIN)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 299 USB_P)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 298 USB_N)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 195 FT_RXD1)) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 197 FT_TXD1)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.90459 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 296 USB_MGMT_N)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 297 USB_MGMT_P)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_694106301002_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20 18.4) + (path /539EEC0F) + (attr smd) + (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth Power Connector 5.5x2.1mm Barrel" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 284 PWR_18V)) + (model wrlshp/PJ-002A.wrl + (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 180 270)) + ) + (model wrlshp/51D2E761-0F4D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 64.6468 -91.7448) + (path /539EEC0F) + (attr smd) + (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 5 15V_LDO_ENABLE)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.117 -31.1658) + (path /539EEC0F) + (attr smd) + (fp_text reference JP3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 214 MKM_AVR_SCK)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 39 AVR_RESET)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-3_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.67933 1.5) + (path /539EEC0F) + (attr smd) + (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_aw_108_03-t.wrl + (offset (xyz 0.05003799924850464 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/836C6F64-A2E5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 18.25 -29.475) + (path /539EEC0F) + (attr smd) + (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 123 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 246 "Net-(LED1-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 247 "Net-(LED2-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 248 "Net-(LED3-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 43.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 249 "Net-(LED4-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 34.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 250 "Net-(LED9-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 251 "Net-(LED10-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED11 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 252 "Net-(LED11-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 32.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 253 "Net-(LED12-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 254 "Net-(LED13-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 130 FPGA_DONE_INT)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 52.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 255 "Net-(LED14-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 256 "Net-(LED15-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 54.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 257 "Net-(LED16-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 50.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED17 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 258 "Net-(LED17-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 76.13225 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED18 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 259 "Net-(LED18-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 72.452 -95.2388) + (path /539EEC0F) + (attr smd) + (fp_text reference Q1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.3732 -92.7862) + (path /539EEC0F) + (attr smd) + (fp_text reference Q2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (pad 2 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 276 NOISE_IN)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.3 -34.975) + (path /539EEC0F) + (attr smd) + (fp_text reference Q3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Abracon 25MHz 10pF 4-pin 3.2 x 2.5mm crystal" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 280 OSC_OUT)) + (pad 2 smd rect (at -1.0922 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 228 "Net-(C17-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.3064 -73.0504) + (path /539EEC0F) + (attr smd) + (fp_text reference Q4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 155 FPGA_INIT_B_INT)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 156 FPGA_INIT_B)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_ASF_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 67.9704 -84.709) + (path /539EEC0F) + (attr smd) + (fp_text reference Q5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at -1.0922 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -1.0922 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 263 "Net-(Q5-Pad3)")) + (pad 1 smd rect (at 1.1302 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 262 "Net-(Q5-Pad1)")) + (pad 2 smd rect (at 1.1302 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 15.7398 -42.4106) + (path /539EEC0F) + (attr smd) + (fp_text reference Q6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 283 POK_VCCO)) + (pad 2 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.5 -81.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 1%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 264 "Net-(R1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.5 -79.2) + (path /539EEC0F) + (attr smd) + (fp_text reference R2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 1%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 264 "Net-(R1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.7048 -80.8308) + (path /539EEC0F) + (attr smd) + (fp_text reference R3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 265 "Net-(R3-Pad2)")) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 264 "Net-(R1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 64.4906 -82.931) + (path /539EEC0F) + (attr smd) + (fp_text reference R4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 133 FPGA_GCLK)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 263 "Net-(Q5-Pad3)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 71.75 -99.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 132 FPGA_ENTROPY_DISABLE)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 71.75 -98.25) + (path /539EEC0F) + (attr smd) + (fp_text reference R6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer 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0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 47 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R92 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 15 ARM_LED2)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 246 "Net-(LED1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R93 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 248 "Net-(LED3-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 14 ARM_LED1)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 43 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R94 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 17 ARM_LED4)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 247 "Net-(LED2-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R95 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 250 "Net-(LED9-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 35 AVR_LED2)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R96 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 34 AVR_LED1)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 252 "Net-(LED11-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 26 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R97 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 251 "Net-(LED10-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 37 AVR_LED4)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 79 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R98 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 152 FPGA_GPIO_LED_2)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 257 "Net-(LED16-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 77 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R99 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 255 "Net-(LED14-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 153 FPGA_GPIO_LED_3)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 75 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R100 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 150 FPGA_GPIO_LED_0)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 258 "Net-(LED17-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_WE-SHC_36103205_NO_CREAM_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 83.82 -87.7454) + (path /539EEC0F) + (attr smd) + (fp_text reference S1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "WE-SHC Shielding cabinet" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 10.2616 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_TACTILE_SWITCH_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 62.8 -5.3608) + (path /539EEC0F) + (attr smd) + (fp_text reference S2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Tacktile switch" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-8_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 40.3 -1.3) + (path /539EEC0F) + (attr smd) + (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/PLS-8.wrl + (offset (xyz 8.889999866485596 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/A962434E-CFE5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.58299 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 138 FPGA_GPIO_A_4)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 135 FPGA_GPIO_A_1)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 134 FPGA_GPIO_A_0)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 36.79919 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 143 FPGA_GPIO_B_1)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 145 FPGA_GPIO_B_3)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 146 FPGA_GPIO_B_4)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 148 FPGA_GPIO_B_6)) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 149 FPGA_GPIO_B_7)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.2208 -88.1634) + (path /539EEC0F) + (attr smd) + (fp_text reference T1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + (pad 2 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 -0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.201 -82.7532) + (path /539EEC0F) + (attr smd) + (fp_text reference T2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 8 "Net-(C15-Pad2)")) + (pad 2 smd rect (at -0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0 -1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.3158 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.1436 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + ) + + (module Cryptech_Alpha_Footprints:_NDY_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.2758 -78.2828) + (path /539EEC0F) + (attr smd) + (fp_text reference U1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 3 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 265 "Net-(R3-Pad2)")) + (pad 5 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 266 "Net-(R8-Pad1)")) + (pad TP1 smd rect (at -9.525 0 90) (size 9.144 13.3858) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 8 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 225 "Net-(C5-Pad1)")) + (pad 9 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 11 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + ) + + (module Cryptech_Alpha_Footprints:_TSOT-8-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 70.5 -89.75) + (path /539EEC0F) + (attr smd) + (fp_text reference U2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Micropower, Low Noise, 100mA LDO, Linear Regulator" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 5 15V_LDO_ENABLE)) + (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 6 15V_STABLE)) + (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 226 "Net-(C11-Pad1)")) + (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 227 "Net-(C12-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23-5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 77.3684 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference U3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Single Inverter with Schmitt-Trigger Input" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at -1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd rect (at -1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad 3 smd rect (at 1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd rect (at 1.35 0 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (pad 1 smd oval (at 1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/User Library-SOT23-5-1.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/612DFB50-5309.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSQFP50P3000X3000X160-208N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 48.6918 -32.6136) + (path /539EEC0F) + (attr smd) + (fp_text reference U4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 208 smd oval (at -12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 207 smd oval (at -12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 206 smd oval (at -11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 205 smd oval (at -11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 204 smd oval (at -10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 203 smd oval (at -10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 202 smd oval (at -9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 201 smd oval (at -9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 104 FMC_NBL1)) + (pad 200 smd oval (at -8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 103 FMC_NBL0)) + (pad 199 smd oval (at -8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 198 smd oval (at -7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 197 smd oval (at -7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 40 BOOT0)) + (pad 196 smd oval (at -6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 108 FMC_NL)) + (pad 195 smd oval (at -6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 117 FMC_SDNE1)) + (pad 194 smd oval (at -5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 113 FMC_SDCKE1)) + (pad 193 smd oval (at -5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 192 smd oval (at -4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 191 smd oval (at -4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 115 FMC_SDNCAS)) + (pad 190 smd oval (at -3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 17 ARM_LED4)) + (pad 189 smd oval (at -3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 16 ARM_LED3)) + (pad 188 smd oval (at -2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 15 ARM_LED2)) + (pad 187 smd oval (at -2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 14 ARM_LED1)) + (pad 186 smd oval (at -1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 185 smd oval (at -1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 184 smd oval (at -0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 183 smd oval (at -0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_A25)) + (pad 182 smd oval (at 0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_A24)) + (pad 181 smd oval (at 0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 180 smd oval (at 1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 179 smd oval (at 1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 178 smd oval (at 2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 177 smd oval (at 2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 131 FPGA_DONE)) + (pad 176 smd oval (at 3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 175 smd oval (at 3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 160 FPGA_IRQ_N_3)) + (pad 174 smd oval (at 4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 159 FPGA_IRQ_N_2)) + (pad 173 smd oval (at 4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 107 FMC_NE1)) + (pad 172 smd oval (at 5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 110 FMC_NWAIT)) + (pad 171 smd oval (at 5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 170 smd oval (at 6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 169 smd oval (at 6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 111 FMC_NWE)) + (pad 168 smd oval (at 7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 109 FMC_NOE)) + (pad 167 smd oval (at 7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_CLK)) + (pad 166 smd oval (at 8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 165 smd oval (at 8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad 164 smd oval (at 9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad 163 smd oval (at 9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 162 smd oval (at 10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 161 smd oval (at 10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 160 smd oval (at 11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 159 smd oval (at 11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 294 SWDCLK)) + (pad 158 smd oval (at 12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 157 smd oval (at 12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad 156 smd oval (at 14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad 155 smd oval (at 14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad 154 smd oval (at 14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad 153 smd oval (at 14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad 152 smd oval (at 14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad 151 smd oval (at 14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad 150 smd oval (at 14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 149 smd oval (at 14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 148 smd oval (at 14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 301 VCAP2)) + (pad 147 smd oval (at 14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 295 SWDIO)) + (pad 146 smd oval (at 14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 179 FT_MGMT_CTS)) + (pad 145 smd oval (at 14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 181 FT_MGMT_RTS)) + (pad 144 smd oval (at 14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 185 FT_MGMT_TXD)) + (pad 143 smd oval (at 14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 183 FT_MGMT_RXD)) + (pad 142 smd oval (at 14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 180 FT_MGMT_DTR)) + (pad 141 smd oval (at 14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 140 smd oval (at 14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 139 smd oval (at 14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 138 smd oval (at 14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 137 smd oval (at 14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 136 smd oval (at 14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 135 smd oval (at 14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 114 FMC_SDCLK)) + (pad 134 smd oval (at 14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 133 smd oval (at 14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 132 smd oval (at 14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad 131 smd oval (at 14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad 130 smd oval (at 14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_A13)) + (pad 129 smd oval (at 14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad 128 smd oval (at 14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 127 smd oval (at 14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 126 smd oval (at 14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 125 smd oval (at 14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 124 smd oval (at 14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 123 smd oval (at 14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 158 FPGA_IRQ_N_1)) + (pad 122 smd oval (at 14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 157 FPGA_IRQ_N_0)) + (pad 121 smd oval (at 14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 120 smd oval (at 14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 169 FPGA_PROGRAM_B)) + (pad 119 smd oval (at 14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 156 FPGA_INIT_B)) + (pad 118 smd oval (at 14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 117 smd oval (at 14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad 116 smd oval (at 14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad 115 smd oval (at 14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 114 smd oval (at 14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 113 smd oval (at 14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_A18)) + (pad 112 smd oval (at 14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_A17)) + (pad 111 smd oval (at 14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_A16)) + (pad 110 smd oval (at 14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad 109 smd oval (at 14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad 108 smd oval (at 14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad 107 smd oval (at 14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 12 ARM_FPGA_CFG_MOSI)) + (pad 106 smd oval (at 14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 11 ARM_FPGA_CFG_MISO)) + (pad 105 smd oval (at 14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 13 ARM_FPGA_CFG_SCLK)) + (pad 104 smd oval (at 12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 10 ARM_FPGA_CFG_CS_N)) + (pad 103 smd oval (at 12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 102 smd oval (at 11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad 101 smd oval (at 11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad 100 smd oval (at 10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad 99 smd oval (at 10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad 98 smd oval (at 9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad 97 smd oval (at 9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 26 AVR_GPIO_ARM_0)) + (pad 96 smd oval (at 8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 27 AVR_GPIO_ARM_1)) + (pad 95 smd oval (at 8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 94 smd oval (at 7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 93 smd oval (at 7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 92 smd oval (at 6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 300 VCAP1)) + (pad 91 smd oval (at 6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 28 AVR_GPIO_ARM_2)) + (pad 90 smd oval (at 5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 29 AVR_GPIO_ARM_3)) + (pad 89 smd oval (at 5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad 88 smd oval (at 4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad 87 smd oval (at 4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad 86 smd oval (at 3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad 85 smd oval (at 3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad 84 smd oval (at 2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad 83 smd oval (at 2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 82 smd oval (at 1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 81 smd oval (at 1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad 80 smd oval (at 0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad 79 smd oval (at 0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad 78 smd oval (at -0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad 77 smd oval (at -0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad 76 smd oval (at -1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad 75 smd oval (at -1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad 74 smd oval (at -2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad 73 smd oval (at -2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 72 smd oval (at -3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 71 smd oval (at -3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad 70 smd oval (at -4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 118 FMC_SDNRAS)) + (pad 69 smd oval (at -4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 68 smd oval (at -5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 67 smd oval (at -5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 66 smd oval (at -6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 65 smd oval (at -6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 64 smd oval (at -7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 63 smd oval (at -7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 62 smd oval (at -8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 61 smd oval (at -8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 207 KSM_PROM_CS_N)) + (pad 60 smd oval (at -9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 59 smd oval (at -9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 58 smd oval (at -10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 57 smd oval (at -10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at -11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 209 KSM_PROM_MOSI)) + (pad 55 smd oval (at -11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 208 KSM_PROM_MISO)) + (pad 54 smd oval (at -12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 KSM_PROM_SCLK)) + (pad 53 smd oval (at -12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 178 FT_DTR)) + (pad 52 smd oval (at -14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 51 smd oval (at -14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 50 smd oval (at -14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 198 FT_TXD)) + (pad 49 smd oval (at -14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 291 RTC_SDA)) + (pad 48 smd oval (at -14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 290 RTC_SCL)) + (pad 47 smd oval (at -14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 289 RTC_MFP)) + (pad 46 smd oval (at -14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 196 FT_RXD)) + (pad 44 smd oval (at -14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 177 FT_CTS)) + (pad 43 smd oval (at -14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 194 FT_RTS)) + (pad 42 smd oval (at -14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 41 smd oval (at -14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 40 smd oval (at -14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 39 smd oval (at -14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 38 smd oval (at -14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 112 FMC_SDCKE0)) + (pad 37 smd oval (at -14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 116 FMC_SDNE0)) + (pad 36 smd oval (at -14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at -14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FMC_SDNWE)) + (pad 34 smd oval (at -14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 278 NRST)) + (pad 33 smd oval (at -14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 280 OSC_OUT)) + (pad 32 smd oval (at -14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 279 OSC_IN)) + (pad 31 smd oval (at -14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 30 smd oval (at -14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 29 smd oval (at -14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 28 smd oval (at -14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 26 smd oval (at -14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 25 smd oval (at -14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 24 smd oval (at -14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 23 smd oval (at -14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 22 smd oval (at -14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 21 smd oval (at -14.75 2.75 270) (size 0.3 1.2) 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(layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 10 smd oval (at -14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 9 smd oval (at -14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 8 smd oval (at -14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 7 smd oval (at -14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 6 smd oval (at -14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 267 "Net-(R32-Pad2)")) + (pad 5 smd oval (at -14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad 4 smd oval (at -14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad 3 smd oval (at -14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad 2 smd oval (at -14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad 1 smd oval (at -14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (model wrlshp/1B9BC620-BA33.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.1704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 44 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 45 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 95 FMC_D24)) + (pad 46 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 96 FMC_D25)) + (pad 48 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 97 FMC_D26)) + (pad 49 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 50 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 98 FMC_D27)) + (pad 51 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 99 FMC_D28)) + (pad 52 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 53 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 100 FMC_D29)) + (pad 54 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 101 FMC_D30)) + (pad 55 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 56 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 102 FMC_D31)) + (pad 57 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 58 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 59 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 106 FMC_NBL3)) + (pad 60 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 47 FMC_A3)) + (pad 61 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 48 FMC_A4)) + (pad 62 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 49 FMC_A5)) + (pad 63 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 50 FMC_A6)) + (pad 64 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 51 FMC_A7)) + (pad 65 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 52 FMC_A8)) + (pad 66 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 53 FMC_A9)) + (pad 67 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 112 FMC_SDCKE0)) + (pad 68 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 114 FMC_SDCLK)) + (pad 69 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 56 FMC_A12)) + (pad 70 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 71 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 104 FMC_NBL1)) + (pad 72 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 73 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 74 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 79 FMC_D8)) + (pad 75 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 76 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 80 FMC_D9)) + (pad 77 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 81 FMC_D10)) + (pad 78 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 79 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 82 FMC_D11)) + (pad 80 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 83 FMC_D12)) + (pad 81 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 82 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 84 FMC_D13)) + (pad 83 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 85 FMC_D14)) + (pad 84 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 85 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 86 FMC_D15)) + (pad 86 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 94 FMC_D23)) + (pad 41 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 40 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 93 FMC_D22)) + (pad 39 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 92 FMC_D21)) + (pad 38 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 91 FMC_D20)) + (pad 36 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 90 FMC_D19)) + (pad 35 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 34 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 89 FMC_D18)) + (pad 33 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 88 FMC_D17)) + (pad 32 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 31 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 87 FMC_D16)) + (pad 30 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 28 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 105 FMC_NBL2)) + (pad 27 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 46 FMC_A2)) + (pad 26 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 45 FMC_A1)) + (pad 25 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 44 FMC_A0)) + (pad 24 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 54 FMC_A10)) + (pad 23 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 59 FMC_A15)) + (pad 22 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 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GND)) + (pad 11 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 77 FMC_D6)) + (pad 10 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 76 FMC_D5)) + (pad 9 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 75 FMC_D4)) + (pad 7 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 74 FMC_D3)) + (pad 6 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 73 FMC_D2)) + (pad 4 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 72 FMC_D1)) + (pad 3 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 71 FMC_D0)) + (pad 1 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.6704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad 3 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad 5 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad 6 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad 8 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad 9 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad 11 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad 12 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad 14 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 16 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 103 FMC_NBL0)) + (pad 17 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FMC_SDNWE)) + (pad 18 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 115 FMC_SDNCAS)) + (pad 19 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 118 FMC_SDNRAS)) + (pad 20 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 117 FMC_SDNE1)) + (pad 21 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad 23 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad 24 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad 25 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad 26 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad 27 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad 28 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 29 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 30 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 31 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad 32 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad 34 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad 35 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 36 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad 37 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad 38 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 39 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad 40 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad 41 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad 43 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 86 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 85 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad 84 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 83 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad 82 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad 81 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 80 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad 79 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad 78 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 77 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad 76 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad 75 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 74 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad 73 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 72 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 71 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 104 FMC_NBL1)) + (pad 70 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 69 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad 68 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 114 FMC_SDCLK)) + (pad 67 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 113 FMC_SDCKE1)) + (pad 66 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad 64 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad 63 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad 62 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 61 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 60 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 59 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 58 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 57 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad 55 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 54 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 53 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 52 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 51 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 50 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad 49 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 48 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad 47 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad 46 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 45 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad 44 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.6 -43.45) + (path /539EEC0F) + (attr smd) + (fp_text reference U7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RTCC, I2C, 1K EE, 64B SRAM, 8SOIC" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 smd rect (at 2.6924 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 7 smd rect (at 2.6924 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 289 RTC_MFP)) + (pad 6 smd rect (at 2.6924 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 290 RTC_SCL)) + (pad 5 smd rect (at 2.6924 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 291 RTC_SDA)) + (pad 4 smd rect (at -2.7178 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -2.7178 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 2 smd rect (at -2.7178 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + (pad 1 smd rect (at -2.7178 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 13.8186 -9.636) + (path /539EEC0F) + (attr smd) + (fp_text reference U8 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 48 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 46 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 45 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 41 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 40 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 39 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 38 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 203 FT_VCCORE)) + (pad 37 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 201 FT_VCCA)) + (pad 36 smd rect (at -4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 35 smd rect (at -4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 34 smd rect (at -4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 193 FT_RESET)) + (pad 33 smd rect (at -4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at -4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at -4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at -4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at -4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at -4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 23 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 21 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 178 FT_DTR)) + (pad 16 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 177 FT_CTS)) + (pad 15 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 194 FT_RTS)) + (pad 14 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 195 FT_RXD1)) + (pad 13 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 197 FT_TXD1)) + (pad 12 smd rect (at 4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 11 smd rect (at 4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 8 smd rect (at 4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 7 smd rect (at 4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 6 smd rect (at 4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 5 smd rect (at 4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 191 FT_REF)) + (pad 4 smd rect (at 4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (pad 2 smd rect (at 4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 1 smd rect (at 4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.3854 -17.8496) + (path /539EEC0F) + (attr smd) + (fp_text reference U9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 190 FT_REF1)) + (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 181 FT_MGMT_RTS)) + (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 179 FT_MGMT_CTS)) + (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 180 FT_MGMT_DTR)) + (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 192 FT_RESET1)) + (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 200 FT_VCCA1)) + (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 202 FT_VCCORE1)) + (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-32_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 53.0832 -38.55) + (path /539EEC0F) + (attr smd) + (fp_text reference U10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "IC, MCU, 8KB, FLASH, 20MHZ, TQFP-32" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 smd rect (at -2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 21 AVR_GPIO_3)) + (pad 3 smd rect (at -1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 22 AVR_GPIO_4)) + (pad 4 smd rect (at -0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 5 smd rect (at 0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 23 AVR_GPIO_5)) + (pad 7 smd rect (at 2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 24 AVR_GPIO_6)) + (pad 8 smd rect (at 2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 25 AVR_GPIO_7)) + (pad 9 smd rect (at 4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 34 AVR_LED1)) + (pad 10 smd rect (at 4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 35 AVR_LED2)) + (pad 11 smd rect (at 4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 36 AVR_LED3)) + (pad 12 smd rect (at 4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 37 AVR_LED4)) + (pad 13 smd rect (at 4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + (pad 14 smd rect (at 4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 15 smd rect (at 4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + (pad 16 smd rect (at 4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 17 smd rect (at 2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 26 AVR_GPIO_ARM_0)) + (pad 18 smd rect (at 2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at 1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 27 AVR_GPIO_ARM_1)) + (pad 20 smd rect (at 0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 28 AVR_GPIO_ARM_2)) + (pad 21 smd rect (at -0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 29 AVR_GPIO_ARM_3)) + (pad 23 smd rect (at -2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad 24 smd rect (at -2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad 25 smd rect (at -4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad 26 smd rect (at -4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad 27 smd rect (at -4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 28 smd rect (at -4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 29 smd rect (at -4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 39 AVR_RESET)) + (pad 30 smd rect (at -4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 31 smd rect (at -4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 18 AVR_GPIO_0)) + (pad 32 smd rect (at -4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 19 AVR_GPIO_1)) + (model "wrlshp/User Library-sot358-1.wrl" + (offset (xyz 0 -0.01066799983978271 0.7000011294870376)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/590BE70C-A1C3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.4418 -30.718) + (path /539EEC0F) + (attr smd) + (fp_text reference U12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "64K SPI Bus Low-Power Serial SRAM,SOIC-8" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 217 MKM_CS_N)) + (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 222 MKM_MISO)) + (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 223 MKM_MOSI)) + (pad 6 smd rect (at 0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 224 MKM_SCK)) + (pad 7 smd rect (at -0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 268 "Net-(R33-Pad2)")) + (pad 8 smd rect (at -1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 4 3V3_BATT)) + ) + + (module Cryptech_Alpha_Footprints:_BGA484C100P22X22_2300X2300X254_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.4534 -68.8848) + (path /539EEC0F) + (attr smd) + (fp_text reference U13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Xilinx FPGA: XC7A200TFBG484" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_A24)) + (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 153 FPGA_GPIO_LED_3)) + (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_A25)) + (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_A16)) + (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_A17)) + (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 111 FMC_NWE)) + (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_A18)) + (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 110 FMC_NWAIT)) + (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 219 MKM_FPGA_MISO)) + (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 152 FPGA_GPIO_LED_2)) + (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 108 FMC_NL)) + (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 109 FMC_NOE)) + (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_CLK)) + (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 107 FMC_NE1)) + (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 221 MKM_FPGA_SCK)) + (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_A13)) + (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 273 "Net-(R65-Pad1)")) + (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 154 FPGA_INIT_B_INT1)) + (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 165 FPGA_M0)) + (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 166 FPGA_M1)) + (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 167 FPGA_M2)) + (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 150 FPGA_GPIO_LED_0)) + (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 120 FPGA_CFG_CS_N1)) + (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 151 FPGA_GPIO_LED_1)) + (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 124 FPGA_CFG_MISO1)) + (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_CFG_MOSI1)) + (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 168 FPGA_PROGRAM_B1)) + (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + 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0.45) (layers B.Cu B.Paste B.Mask)) + (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 149 FPGA_GPIO_B_7)) + (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 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(layers B.Cu B.Paste B.Mask)) + (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 132 FPGA_ENTROPY_DISABLE)) + (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (model wrlshp/041B98A5-F02D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 35.4584 -76.5556) + (path /539EEC0F) + (attr smd) + (fp_text reference U14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad PAD39 smd oval (at 0 1.26 180) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 38 smd oval (at -1.905 -3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at -1.905 -2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at -1.905 -2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at -1.905 -1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 34 smd oval (at -1.905 -1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 33 smd oval (at -1.905 -0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 32 smd oval (at -1.905 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -1.905 0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 238 "Net-(C117-Pad2)")) + (pad 30 smd oval (at -1.905 1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 235 "Net-(C115-Pad1)")) + (pad 29 smd oval (at -1.905 1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 270 "Net-(R53-Pad2)")) + (pad 28 smd oval (at -1.905 2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 281 POK_VCCAUX)) + (pad 27 smd oval (at -1.905 2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 26 smd oval (at -1.905 3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 269 "Net-(R52-Pad1)")) + (pad 25 smd oval (at -1.27 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at -0.762 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at -0.254 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 0.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 0.75 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at 1.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 19 smd oval (at 1.9 3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 18 smd oval (at 1.9 2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at 1.9 2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at 1.9 1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at 1.9 1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at 1.9 0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at 1.9 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 12 smd oval (at 1.9 -0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 11 smd oval (at 1.9 -1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 10 smd oval (at 1.9 -1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 9 smd oval (at 1.9 -2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 8 smd oval (at 1.9 -2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 7 smd oval (at 1.9 -3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 6 smd oval (at 1.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 5 smd oval (at 0.75 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 4 smd oval (at 0.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at -0.254 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at -0.762 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd oval (at -1.27 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 10.8458 -41.0972) + (path /539EEC0F) + (attr smd) + (fp_text reference U15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 1.27 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at 0.762 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at 0.254 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd oval (at -0.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 5 smd oval (at -0.75 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 6 smd oval (at -1.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 7 smd oval (at -1.9 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 8 smd oval (at -1.9 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 9 smd oval (at -1.9 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 10 smd oval (at -1.9 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 11 smd oval (at -1.9 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 12 smd oval (at -1.9 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at -1.9 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at -1.9 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at -1.9 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at -1.9 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 18 smd oval (at -1.9 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 19 smd oval (at -1.9 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at -1.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 21 smd oval (at -0.75 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 22 smd oval (at -0.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 0.254 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.762 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 1.27 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at 1.905 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 271 "Net-(R54-Pad1)")) + (pad 27 smd oval (at 1.905 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 287 PWR_ENA_VCCO)) + (pad 28 smd oval (at 1.905 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 283 POK_VCCO)) + (pad 29 smd oval (at 1.905 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 272 "Net-(R55-Pad2)")) + (pad 30 smd oval (at 1.905 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 236 "Net-(C116-Pad1)")) + (pad 31 smd oval (at 1.905 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 240 "Net-(C118-Pad2)")) + (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at 1.905 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 34 smd oval (at 1.905 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at 1.905 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at 1.905 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at 1.905 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 38 smd oval (at 1.905 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad PAD39 smd oval (at 0 -1.26) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_QFN68_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.9842 -57.4802) + (path /539EEC0F) + (attr smd) + (fp_text reference U16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 5.5 -3.5052 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd oval (at 5.5 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd oval (at 5.5 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd oval (at 5.5 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.5 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 6 smd oval (at 5.5 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 7 smd oval (at 5.5 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 9 smd oval (at 5.5 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 10 smd oval (at 5.5 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 11 smd oval (at 5.5 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 12 smd oval (at 5.5 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 13 smd oval (at 5.5 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 14 smd oval (at 5.5 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at 5.5 3.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 16 smd oval (at 4.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 17 smd oval (at 4 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 18 smd oval (at 3.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 19 smd oval (at 3 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 20 smd oval (at 2.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 2 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 1.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 1 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 0 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at -0.508 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -1.016 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 28 smd oval (at -1.524 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 29 smd oval (at -2.0066 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 30 smd oval (at -2.5146 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -3.0226 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 32 smd oval (at -3.5052 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -4.0132 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 34 smd oval (at -4.5212 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 35 smd oval (at -5.5118 3.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 36 smd oval (at -5.5118 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 37 smd oval (at -5.5118 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 38 smd oval (at -5.5118 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 39 smd oval (at -5.5118 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 40 smd oval (at -5.5118 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 41 smd oval (at -5.5118 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 43 smd oval (at -5.5118 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 44 smd oval (at -5.5118 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -5.5118 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 46 smd oval (at -5.5118 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 47 smd oval (at -5.5118 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 48 smd oval (at -5.5118 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 49 smd oval (at -5.5118 -3.5052) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 50 smd oval (at -4.5212 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 51 smd oval (at -4.0132 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 274 "Net-(R66-Pad1)")) + (pad 52 smd oval (at -3.5052 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 53 smd oval (at -3.0226 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 54 smd oval (at -2.5146 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 282 POK_VCCINT)) + (pad 55 smd oval (at -2.0066 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 56 smd oval (at -1.524 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 243 "Net-(C208-Pad2)")) + (pad 57 smd oval (at -1.016 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 58 smd oval (at -0.508 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 59 smd oval (at 0 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 241 "Net-(C207-Pad1)")) + (pad 60 smd oval (at 0.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 61 smd oval (at 1 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 62 smd oval (at 1.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 63 smd oval (at 2 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 275 "Net-(R67-Pad1)")) + (pad 64 smd oval (at 2.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 65 smd oval (at 3 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 66 smd oval (at 3.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 67 smd oval (at 4 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 68 smd oval (at 4.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD69 smd oval (at -2.175 0.625 90) (size 5.35 2.35) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD70 smd oval (at 3.55 -2.65 180) (size 2.5 1.3) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_XTAL3215_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 19.275 -45.6) + (path /539EEC0F) + (attr smd) + (fp_text reference X1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 32.768kHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 23.075 -5.5) + (path /539EEC0F) + (attr smd) + (fp_text reference Y1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.8382 -1.1176 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 2 smd rect (at -0.8382 1.0922 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0.8636 1.0922 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (pad 4 smd rect (at 0.8636 -1.1176 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.525 -8.8) + (path /539EEC0F) + (attr smd) + (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.4 -62.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R35 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 167 FPGA_M2)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -59.1757) + (path /539EEC0F) + (attr smd) + (fp_text reference R36 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 166 FPGA_M1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -60.4076) + (path /539EEC0F) + (attr smd) + (fp_text reference R37 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer 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(min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 74.1705 -38.3265) (xy 76.6705 -38.3265) (xy 76.6705 -40.8265) (xy 74.1705 -40.8265) + ) + ) + ) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 5E9DD908) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 28.88413 -59.75513) (xy 30.18413 -59.75513) (xy 30.18413 -60.50513) (xy 28.88413 -60.50513) + ) + ) + ) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 5E9DD905) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 23.23427 -57.22519) (xy 24.40927 -57.22519) (xy 24.40927 -58.83019) (xy 23.23427 -58.83019) + ) + ) + ) + (zone (net 0) (net_name "") (layer B.Paste) (tstamp 5E9DD902) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 23.23427 -54.90021) (xy 24.40927 -54.90021) (xy 24.40927 -56.50521) (xy 23.23427 -56.50521) + ) + ) + ) +) diff --git a/KiCAD/Cryptech Alpha.kicad_pcb-bak b/KiCAD/Cryptech Alpha.kicad_pcb-bak new file mode 100644 index 0000000..9cd0e72 --- /dev/null +++ b/KiCAD/Cryptech Alpha.kicad_pcb-bak @@ -0,0 +1,30742 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.5-52549c5~86~ubuntu18.04.1) + + (general + (thickness 1.6) + (drawings 6691) + (tracks 9160) + (zones 0) + (modules 386) + (nets 304) + ) + + (page A4) + (layers + (0 F.Cu signal) + (1 In1.Cu power hide) + (2 In2.Cu mixed hide) + (3 In3.Cu power hide) + (4 In4.Cu power hide) + (5 In5.Cu mixed hide) + (6 In6.Cu power hide) + (31 B.Cu signal hide) + (32 B.Adhes user hide) + (33 F.Adhes user hide) + (34 B.Paste user hide) + (35 F.Paste user hide) + (36 B.SilkS user hide) + (37 F.SilkS user hide) + (38 B.Mask user hide) + (39 F.Mask user hide) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) + (42 Eco1.User user hide) + (43 Eco2.User user hide) + (44 Edge.Cuts user hide) + (45 Margin user hide) + (46 B.CrtYd user hide) + (47 F.CrtYd user hide) + (48 B.Fab user hide) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.125) + (zone_clearance 0.0144) + (zone_45_only no) + (trace_min 0.15) + (via_size 0.889) + (via_drill 0.25) + (via_min_size 0.5) + (via_min_drill 0.25) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (edge_width 0.1) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.5 1.5) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements 7FFED33F) + (pcbplotparams + (layerselection 0x00030_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "GerberOutput/")) + ) + + (net 0 "") + (net 1 Net1) + (net 2 DM_P) + (net 3 DM_N) + (net 4 3V3_BATT) + (net 5 15V_LDO_ENABLE) + (net 6 15V_STABLE) + (net 7 GND) + (net 8 "Net-(C15-Pad2)") + (net 9 AMPLIFIED) + (net 10 ARM_FPGA_CFG_CS_N) + (net 11 ARM_FPGA_CFG_MISO) + (net 12 ARM_FPGA_CFG_MOSI) + (net 13 ARM_FPGA_CFG_SCLK) + (net 14 ARM_LED1) + (net 15 ARM_LED2) + (net 16 ARM_LED3) + (net 17 ARM_LED4) + (net 18 AVR_GPIO_0) + (net 19 AVR_GPIO_1) + (net 20 AVR_GPIO_2) + (net 21 AVR_GPIO_3) + (net 22 AVR_GPIO_4) + (net 23 AVR_GPIO_5) + (net 24 AVR_GPIO_6) + (net 25 AVR_GPIO_7) + (net 26 AVR_GPIO_ARM_0) + (net 27 AVR_GPIO_ARM_1) + (net 28 AVR_GPIO_ARM_2) + (net 29 AVR_GPIO_ARM_3) + (net 30 AVR_GPIO_FPGA_0) + (net 31 AVR_GPIO_FPGA_1) + (net 32 AVR_GPIO_FPGA_2) + (net 33 AVR_GPIO_FPGA_3) + (net 34 AVR_LED1) + (net 35 AVR_LED2) + (net 36 AVR_LED3) + (net 37 AVR_LED4) + (net 38 AVR_PANIC) + (net 39 AVR_RESET) + (net 40 BOOT0) + (net 41 D1_N) + (net 42 D1_P) + (net 43 DIGITIZED_NOISE) + (net 44 FMC_A0) + (net 45 FMC_A1) + (net 46 FMC_A2) + (net 47 FMC_A3) + (net 48 FMC_A4) + (net 49 FMC_A5) + (net 50 FMC_A6) + (net 51 FMC_A7) + (net 52 FMC_A8) + (net 53 FMC_A9) + (net 54 FMC_A10) + (net 55 FMC_A11) + (net 56 FMC_A12) + (net 57 FMC_A13) + (net 58 FMC_A14) + (net 59 FMC_A15) + (net 60 FMC_A16) + (net 61 FMC_A17) + (net 62 FMC_A18) + (net 63 FMC_A19) + (net 64 FMC_A20) + (net 65 FMC_A21) + (net 66 FMC_A22) + (net 67 FMC_A23) + (net 68 FMC_A24) + (net 69 FMC_A25) + (net 70 FMC_CLK) + (net 71 FMC_D0) + (net 72 FMC_D1) + (net 73 FMC_D2) + (net 74 FMC_D3) + (net 75 FMC_D4) + (net 76 FMC_D5) + (net 77 FMC_D6) + (net 78 FMC_D7) + (net 79 FMC_D8) + (net 80 FMC_D9) + (net 81 FMC_D10) + (net 82 FMC_D11) + (net 83 FMC_D12) + (net 84 FMC_D13) + (net 85 FMC_D14) + (net 86 FMC_D15) + (net 87 FMC_D16) + (net 88 FMC_D17) + (net 89 FMC_D18) + (net 90 FMC_D19) + (net 91 FMC_D20) + (net 92 FMC_D21) + (net 93 FMC_D22) + (net 94 FMC_D23) + (net 95 FMC_D24) + (net 96 FMC_D25) + (net 97 FMC_D26) + (net 98 FMC_D27) + (net 99 FMC_D28) + (net 100 FMC_D29) + (net 101 FMC_D30) + (net 102 FMC_D31) + (net 103 FMC_NBL0) + (net 104 FMC_NBL1) + (net 105 FMC_NBL2) + (net 106 FMC_NBL3) + (net 107 FMC_NE1) + (net 108 FMC_NL) + (net 109 FMC_NOE) + (net 110 FMC_NWAIT) + (net 111 FMC_NWE) + (net 112 FMC_SDCKE0) + (net 113 FMC_SDCKE1) + (net 114 FMC_SDCLK) + (net 115 FMC_SDNCAS) + (net 116 FMC_SDNE0) + (net 117 FMC_SDNE1) + (net 118 FMC_SDNRAS) + (net 119 FMC_SDNWE) + (net 120 FPGA_CFG_CS_N1) + (net 121 FPGA_CFG_CS_N) + (net 122 FPGA_CFG_CTRL_ARM_ENA) + (net 123 FPGA_CFG_CTRL_FPGA_DIS) + (net 124 FPGA_CFG_MISO1) + (net 125 FPGA_CFG_MISO) + (net 126 FPGA_CFG_MOSI1) + (net 127 FPGA_CFG_MOSI) + (net 128 FPGA_CFG_SCLK1) + (net 129 FPGA_CFG_SCLK) + (net 130 FPGA_DONE_INT) + (net 131 FPGA_DONE) + (net 132 FPGA_ENTROPY_DISABLE) + (net 133 FPGA_GCLK) + (net 134 FPGA_GPIO_A_0) + (net 135 FPGA_GPIO_A_1) + (net 136 FPGA_GPIO_A_2) + (net 137 FPGA_GPIO_A_3) + (net 138 FPGA_GPIO_A_4) + (net 139 FPGA_GPIO_A_5) + (net 140 FPGA_GPIO_A_6) + (net 141 FPGA_GPIO_A_7) + (net 142 FPGA_GPIO_B_0) + (net 143 FPGA_GPIO_B_1) + (net 144 FPGA_GPIO_B_2) + (net 145 FPGA_GPIO_B_3) + (net 146 FPGA_GPIO_B_4) + (net 147 FPGA_GPIO_B_5) + (net 148 FPGA_GPIO_B_6) + (net 149 FPGA_GPIO_B_7) + (net 150 FPGA_GPIO_LED_0) + (net 151 FPGA_GPIO_LED_1) + (net 152 FPGA_GPIO_LED_2) + (net 153 FPGA_GPIO_LED_3) + (net 154 FPGA_INIT_B_INT1) + (net 155 FPGA_INIT_B_INT) + (net 156 FPGA_INIT_B) + (net 157 FPGA_IRQ_N_0) + (net 158 FPGA_IRQ_N_1) + (net 159 FPGA_IRQ_N_2) + (net 160 FPGA_IRQ_N_3) + (net 161 FPGA_JTAG_TCK) + (net 162 FPGA_JTAG_TDI) + (net 163 FPGA_JTAG_TDO) + (net 164 FPGA_JTAG_TMS) + (net 165 FPGA_M0) + (net 166 FPGA_M1) + (net 167 FPGA_M2) + (net 168 FPGA_PROGRAM_B1) + (net 169 FPGA_PROGRAM_B) + (net 170 FPGA_PROM_CS_N) + (net 171 FPGA_PROM_MISO) + (net 172 FPGA_PROM_MOSI) + (net 173 FPGA_PROM_SCLK) + (net 174 FPGA_PROM_W_N) + (net 175 FPGA_VCCAUX_1V8) + (net 176 FPGA_VCCINT_1V0) + (net 177 FT_CTS) + (net 178 FT_DTR) + (net 179 FT_MGMT_CTS) + (net 180 FT_MGMT_DTR) + (net 181 FT_MGMT_RTS) + (net 182 FT_MGMT_RXD1) + (net 183 FT_MGMT_RXD) + (net 184 FT_MGMT_TXD1) + (net 185 FT_MGMT_TXD) + (net 186 FT_MGMT_VCC3V3) + (net 187 FT_MGMT_VPHY) + (net 188 FT_MGMT_VPLL) + (net 189 FT_MGMT_VREGIN) + (net 190 FT_REF1) + (net 191 FT_REF) + (net 192 FT_RESET1) + (net 193 FT_RESET) + (net 194 FT_RTS) + (net 195 FT_RXD1) + (net 196 FT_RXD) + (net 197 FT_TXD1) + (net 198 FT_TXD) + (net 199 FT_VCC3V3) + (net 200 FT_VCCA1) + (net 201 FT_VCCA) + (net 202 FT_VCCORE1) + (net 203 FT_VCCORE) + (net 204 FT_VPHY) + (net 205 FT_VPLL) + (net 206 FT_VREGIN) + (net 207 KSM_PROM_CS_N) + (net 208 KSM_PROM_MISO) + (net 209 KSM_PROM_MOSI) + (net 210 KSM_PROM_SCLK) + (net 211 MKM_AVR_CS_N) + (net 212 MKM_AVR_MISO) + (net 213 MKM_AVR_MOSI) + (net 214 MKM_AVR_SCK) + (net 215 MKM_CONTROL_AVR_ENA) + (net 216 MKM_CONTROL_FPGA_DIS) + (net 217 MKM_CS_N) + (net 218 MKM_FPGA_CS_N) + (net 219 MKM_FPGA_MISO) + (net 220 MKM_FPGA_MOSI) + (net 221 MKM_FPGA_SCK) + (net 222 MKM_MISO) + (net 223 MKM_MOSI) + (net 224 MKM_SCK) + (net 225 "Net-(C5-Pad1)") + (net 226 "Net-(C11-Pad1)") + (net 227 "Net-(C12-Pad2)") + (net 228 "Net-(C17-Pad2)") + (net 229 "Net-(C70-Pad2)") + (net 230 "Net-(C71-Pad2)") + (net 231 "Net-(C75-Pad2)") + (net 232 "Net-(C78-Pad2)") + (net 233 "Net-(C90-Pad2)") + (net 234 "Net-(C93-Pad2)") + (net 235 "Net-(C115-Pad1)") + (net 236 "Net-(C116-Pad1)") + (net 237 "Net-(C117-Pad1)") + (net 238 "Net-(C117-Pad2)") + (net 239 "Net-(C118-Pad1)") + (net 240 "Net-(C118-Pad2)") + (net 241 "Net-(C207-Pad1)") + (net 242 "Net-(C208-Pad1)") + (net 243 "Net-(C208-Pad2)") + (net 244 "Net-(IC1-Pad3)") + (net 245 "Net-(JP2-Pad2)") + (net 246 "Net-(LED1-Pad1)") + (net 247 "Net-(LED2-Pad1)") + (net 248 "Net-(LED3-Pad1)") + (net 249 "Net-(LED4-Pad1)") + (net 250 "Net-(LED9-Pad1)") + (net 251 "Net-(LED10-Pad1)") + (net 252 "Net-(LED11-Pad1)") + (net 253 "Net-(LED12-Pad1)") + (net 254 "Net-(LED13-Pad1)") + (net 255 "Net-(LED14-Pad1)") + (net 256 "Net-(LED15-Pad1)") + (net 257 "Net-(LED16-Pad1)") + (net 258 "Net-(LED17-Pad1)") + (net 259 "Net-(LED18-Pad1)") + (net 260 "Net-(LED18-Pad2)") + (net 261 "Net-(Q1-Pad1)") + (net 262 "Net-(Q5-Pad1)") + (net 263 "Net-(Q5-Pad3)") + (net 264 "Net-(R1-Pad1)") + (net 265 "Net-(R3-Pad2)") + (net 266 "Net-(R8-Pad1)") + (net 267 "Net-(R32-Pad2)") + (net 268 "Net-(R33-Pad2)") + (net 269 "Net-(R52-Pad1)") + (net 270 "Net-(R53-Pad2)") + (net 271 "Net-(R54-Pad1)") + (net 272 "Net-(R55-Pad2)") + (net 273 "Net-(R65-Pad1)") + (net 274 "Net-(R66-Pad1)") + (net 275 "Net-(R67-Pad1)") + (net 276 NOISE_IN) + (net 277 NOISE_OUT) + (net 278 NRST) + (net 279 OSC_IN) + (net 280 OSC_OUT) + (net 281 POK_VCCAUX) + (net 282 POK_VCCINT) + (net 283 POK_VCCO) + (net 284 PWR_18V) + (net 285 PWR_ENA_VCCAUX) + (net 286 PWR_ENA_VCCINT) + (net 287 PWR_ENA_VCCO) + (net 288 RAW_NOISE) + (net 289 RTC_MFP) + (net 290 RTC_SCL) + (net 291 RTC_SDA) + (net 292 SPI_A_TRISTATE) + (net 293 SPI_B_TRISTATE) + (net 294 SWDCLK) + (net 295 SWDIO) + (net 296 USB_MGMT_N) + (net 297 USB_MGMT_P) + (net 298 USB_N) + (net 299 USB_P) + (net 300 VCAP1) + (net 301 VCAP2) + (net 302 VCC_5V0) + (net 303 VCCO_3V3) + + (net_class Default "This is the default net class." + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net 15V_LDO_ENABLE) + (add_net 15V_STABLE) + (add_net 3V3_BATT) + (add_net AMPLIFIED) + (add_net ARM_FPGA_CFG_CS_N) + (add_net ARM_FPGA_CFG_MISO) + (add_net ARM_FPGA_CFG_MOSI) + (add_net ARM_FPGA_CFG_SCLK) + (add_net ARM_LED1) + (add_net ARM_LED2) + (add_net ARM_LED3) + (add_net ARM_LED4) + (add_net AVR_GPIO_0) + (add_net AVR_GPIO_1) + (add_net AVR_GPIO_2) + (add_net AVR_GPIO_3) + (add_net AVR_GPIO_4) + (add_net AVR_GPIO_5) + (add_net AVR_GPIO_6) + (add_net AVR_GPIO_7) + (add_net AVR_GPIO_ARM_0) + (add_net AVR_GPIO_ARM_1) + (add_net AVR_GPIO_ARM_2) + (add_net AVR_GPIO_ARM_3) + (add_net AVR_GPIO_FPGA_0) + (add_net AVR_GPIO_FPGA_1) + (add_net AVR_GPIO_FPGA_2) + (add_net AVR_GPIO_FPGA_3) + (add_net AVR_LED1) + (add_net AVR_LED2) + (add_net AVR_LED3) + (add_net AVR_LED4) + (add_net AVR_PANIC) + (add_net AVR_RESET) + (add_net BOOT0) + (add_net DIGITIZED_NOISE) + (add_net FPGA_CFG_CS_N) + (add_net FPGA_CFG_CS_N1) + (add_net FPGA_CFG_CTRL_ARM_ENA) + (add_net FPGA_CFG_CTRL_FPGA_DIS) + (add_net FPGA_CFG_MISO) + (add_net FPGA_CFG_MISO1) + (add_net FPGA_CFG_MOSI) + (add_net FPGA_CFG_MOSI1) + (add_net FPGA_CFG_SCLK) + (add_net FPGA_CFG_SCLK1) + (add_net FPGA_DONE) + (add_net FPGA_DONE_INT) + (add_net FPGA_ENTROPY_DISABLE) + (add_net FPGA_GCLK) + (add_net FPGA_GPIO_LED_0) + (add_net FPGA_GPIO_LED_1) + (add_net FPGA_GPIO_LED_2) + (add_net FPGA_GPIO_LED_3) + (add_net FPGA_INIT_B) + (add_net FPGA_INIT_B_INT) + (add_net FPGA_INIT_B_INT1) + (add_net FPGA_IRQ_N_0) + (add_net FPGA_IRQ_N_1) + (add_net FPGA_IRQ_N_2) + (add_net FPGA_IRQ_N_3) + (add_net FPGA_JTAG_TCK) + (add_net FPGA_JTAG_TDI) + (add_net FPGA_JTAG_TDO) + (add_net FPGA_JTAG_TMS) + (add_net FPGA_M0) + (add_net FPGA_M1) + (add_net FPGA_M2) + (add_net FPGA_PROGRAM_B) + (add_net FPGA_PROGRAM_B1) + (add_net FPGA_PROM_CS_N) + (add_net FPGA_PROM_MISO) + (add_net FPGA_PROM_MOSI) + (add_net FPGA_PROM_SCLK) + (add_net FPGA_PROM_W_N) + (add_net FPGA_VCCAUX_1V8) + (add_net FPGA_VCCINT_1V0) + (add_net FT_CTS) + (add_net FT_DTR) + (add_net FT_MGMT_CTS) + (add_net FT_MGMT_DTR) + (add_net FT_MGMT_RTS) + (add_net FT_MGMT_RXD) + (add_net FT_MGMT_RXD1) + (add_net FT_MGMT_TXD) + (add_net FT_MGMT_TXD1) + (add_net FT_MGMT_VCC3V3) + (add_net FT_MGMT_VPHY) + (add_net FT_MGMT_VPLL) + (add_net FT_MGMT_VREGIN) + (add_net FT_REF) + (add_net FT_REF1) + (add_net FT_RESET) + (add_net FT_RESET1) + (add_net FT_RTS) + (add_net FT_RXD) + (add_net FT_RXD1) + (add_net FT_TXD) + (add_net FT_TXD1) + (add_net FT_VCC3V3) + (add_net FT_VCCA) + (add_net FT_VCCA1) + (add_net FT_VCCORE) + (add_net FT_VCCORE1) + (add_net FT_VPHY) + (add_net FT_VPLL) + (add_net FT_VREGIN) + (add_net GND) + (add_net KSM_PROM_CS_N) + (add_net KSM_PROM_MISO) + (add_net KSM_PROM_MOSI) + (add_net KSM_PROM_SCLK) + (add_net MKM_AVR_CS_N) + (add_net MKM_AVR_MISO) + (add_net MKM_AVR_MOSI) + (add_net MKM_AVR_SCK) + (add_net MKM_CONTROL_AVR_ENA) + (add_net MKM_CONTROL_FPGA_DIS) + (add_net MKM_CS_N) + (add_net MKM_FPGA_CS_N) + (add_net MKM_FPGA_MISO) + (add_net MKM_FPGA_MOSI) + (add_net MKM_FPGA_SCK) + (add_net MKM_MISO) + (add_net MKM_MOSI) + (add_net MKM_SCK) + (add_net NOISE_IN) + (add_net NOISE_OUT) + (add_net NRST) + (add_net "Net-(C11-Pad1)") + (add_net "Net-(C115-Pad1)") + (add_net "Net-(C116-Pad1)") + (add_net "Net-(C117-Pad1)") + (add_net "Net-(C117-Pad2)") + (add_net "Net-(C118-Pad1)") + (add_net "Net-(C118-Pad2)") + (add_net "Net-(C12-Pad2)") + (add_net "Net-(C15-Pad2)") + (add_net "Net-(C17-Pad2)") + (add_net "Net-(C207-Pad1)") + (add_net "Net-(C208-Pad1)") + (add_net "Net-(C208-Pad2)") + (add_net "Net-(C5-Pad1)") + (add_net "Net-(C70-Pad2)") + (add_net "Net-(C71-Pad2)") + (add_net "Net-(C75-Pad2)") + (add_net "Net-(C78-Pad2)") + (add_net "Net-(C90-Pad2)") + (add_net "Net-(C93-Pad2)") + (add_net "Net-(IC1-Pad3)") + (add_net "Net-(JP2-Pad2)") + (add_net "Net-(LED1-Pad1)") + (add_net "Net-(LED10-Pad1)") + (add_net "Net-(LED11-Pad1)") + (add_net "Net-(LED12-Pad1)") + (add_net "Net-(LED13-Pad1)") + (add_net "Net-(LED14-Pad1)") + (add_net "Net-(LED15-Pad1)") + (add_net "Net-(LED16-Pad1)") + (add_net "Net-(LED17-Pad1)") + (add_net "Net-(LED18-Pad1)") + (add_net "Net-(LED18-Pad2)") + (add_net "Net-(LED2-Pad1)") + (add_net "Net-(LED3-Pad1)") + (add_net "Net-(LED4-Pad1)") + (add_net "Net-(LED9-Pad1)") + (add_net "Net-(Q1-Pad1)") + (add_net "Net-(Q5-Pad1)") + (add_net "Net-(Q5-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(R3-Pad2)") + (add_net "Net-(R32-Pad2)") + (add_net "Net-(R33-Pad2)") + (add_net "Net-(R52-Pad1)") + (add_net "Net-(R53-Pad2)") + (add_net "Net-(R54-Pad1)") + (add_net "Net-(R55-Pad2)") + (add_net "Net-(R65-Pad1)") + (add_net "Net-(R66-Pad1)") + (add_net "Net-(R67-Pad1)") + (add_net "Net-(R8-Pad1)") + (add_net Net1) + (add_net OSC_IN) + (add_net OSC_OUT) + (add_net POK_VCCAUX) + (add_net POK_VCCINT) + (add_net POK_VCCO) + (add_net PWR_18V) + (add_net PWR_ENA_VCCAUX) + (add_net PWR_ENA_VCCINT) + (add_net PWR_ENA_VCCO) + (add_net RAW_NOISE) + (add_net RTC_MFP) + (add_net RTC_SCL) + (add_net RTC_SDA) + (add_net SPI_A_TRISTATE) + (add_net SPI_B_TRISTATE) + (add_net SWDCLK) + (add_net SWDIO) + (add_net VCAP1) + (add_net VCAP2) + (add_net VCCO_3V3) + (add_net VCC_5V0) + ) + + (net_class Default "This is the default net class." + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net 15V_LDO_ENABLE) + (add_net 15V_STABLE) + (add_net 3V3_BATT) + (add_net AMPLIFIED) + (add_net ARM_FPGA_CFG_CS_N) + (add_net ARM_FPGA_CFG_MISO) + (add_net ARM_FPGA_CFG_MOSI) + (add_net ARM_FPGA_CFG_SCLK) + (add_net ARM_LED1) + (add_net ARM_LED2) + (add_net ARM_LED3) + (add_net ARM_LED4) + (add_net AVR_GPIO_0) + (add_net AVR_GPIO_1) + (add_net AVR_GPIO_2) + (add_net AVR_GPIO_3) + (add_net AVR_GPIO_4) + (add_net AVR_GPIO_5) + (add_net AVR_GPIO_6) + (add_net AVR_GPIO_7) + (add_net AVR_GPIO_ARM_0) + (add_net AVR_GPIO_ARM_1) + (add_net AVR_GPIO_ARM_2) + (add_net AVR_GPIO_ARM_3) + (add_net AVR_GPIO_FPGA_0) + (add_net AVR_GPIO_FPGA_1) + (add_net AVR_GPIO_FPGA_2) + (add_net AVR_GPIO_FPGA_3) + (add_net AVR_LED1) + (add_net AVR_LED2) + (add_net AVR_LED3) + (add_net AVR_LED4) + (add_net AVR_PANIC) + (add_net AVR_RESET) + (add_net BOOT0) + (add_net DIGITIZED_NOISE) + (add_net FPGA_CFG_CS_N) + (add_net FPGA_CFG_CS_N1) + (add_net FPGA_CFG_CTRL_ARM_ENA) + (add_net FPGA_CFG_CTRL_FPGA_DIS) + (add_net FPGA_CFG_MISO) + (add_net FPGA_CFG_MISO1) + (add_net FPGA_CFG_MOSI) + (add_net FPGA_CFG_MOSI1) + (add_net FPGA_CFG_SCLK) + (add_net FPGA_CFG_SCLK1) + (add_net FPGA_DONE) + (add_net FPGA_DONE_INT) + (add_net FPGA_ENTROPY_DISABLE) + (add_net FPGA_GCLK) + (add_net FPGA_GPIO_LED_0) + (add_net FPGA_GPIO_LED_1) + (add_net FPGA_GPIO_LED_2) + (add_net FPGA_GPIO_LED_3) + (add_net FPGA_INIT_B) + (add_net FPGA_INIT_B_INT) + (add_net FPGA_INIT_B_INT1) + (add_net FPGA_IRQ_N_0) + (add_net FPGA_IRQ_N_1) + (add_net FPGA_IRQ_N_2) + (add_net FPGA_IRQ_N_3) + (add_net FPGA_JTAG_TCK) + (add_net FPGA_JTAG_TDI) + (add_net FPGA_JTAG_TDO) + (add_net FPGA_JTAG_TMS) + (add_net FPGA_M0) + (add_net FPGA_M1) + (add_net FPGA_M2) + (add_net FPGA_PROGRAM_B) + (add_net FPGA_PROGRAM_B1) + (add_net FPGA_PROM_CS_N) + (add_net FPGA_PROM_MISO) + (add_net FPGA_PROM_MOSI) + (add_net FPGA_PROM_SCLK) + (add_net FPGA_PROM_W_N) + (add_net FPGA_VCCAUX_1V8) + (add_net FPGA_VCCINT_1V0) + (add_net FT_CTS) + (add_net FT_DTR) + (add_net FT_MGMT_CTS) + (add_net FT_MGMT_DTR) + (add_net FT_MGMT_RTS) + (add_net FT_MGMT_RXD) + (add_net FT_MGMT_RXD1) + (add_net FT_MGMT_TXD) + (add_net FT_MGMT_TXD1) + (add_net FT_MGMT_VCC3V3) + (add_net FT_MGMT_VPHY) + (add_net FT_MGMT_VPLL) + (add_net FT_MGMT_VREGIN) + (add_net FT_REF) + (add_net FT_REF1) + (add_net FT_RESET) + (add_net FT_RESET1) + (add_net FT_RTS) + (add_net FT_RXD) + (add_net FT_RXD1) + (add_net FT_TXD) + (add_net FT_TXD1) + (add_net FT_VCC3V3) + (add_net FT_VCCA) + (add_net FT_VCCA1) + (add_net FT_VCCORE) + (add_net FT_VCCORE1) + (add_net FT_VPHY) + (add_net FT_VPLL) + (add_net FT_VREGIN) + (add_net GND) + (add_net KSM_PROM_CS_N) + (add_net KSM_PROM_MISO) + (add_net KSM_PROM_MOSI) + (add_net KSM_PROM_SCLK) + (add_net MKM_AVR_CS_N) + (add_net MKM_AVR_MISO) + (add_net MKM_AVR_MOSI) + (add_net MKM_AVR_SCK) + (add_net MKM_CONTROL_AVR_ENA) + (add_net MKM_CONTROL_FPGA_DIS) + (add_net MKM_CS_N) + (add_net MKM_FPGA_CS_N) + (add_net MKM_FPGA_MISO) + (add_net MKM_FPGA_MOSI) + (add_net MKM_FPGA_SCK) + (add_net MKM_MISO) + (add_net MKM_MOSI) + (add_net MKM_SCK) + (add_net NOISE_IN) + (add_net NOISE_OUT) + (add_net NRST) + (add_net "Net-(C11-Pad1)") + (add_net "Net-(C115-Pad1)") + (add_net "Net-(C116-Pad1)") + (add_net "Net-(C117-Pad1)") + (add_net "Net-(C117-Pad2)") + (add_net "Net-(C118-Pad1)") + (add_net "Net-(C118-Pad2)") + (add_net "Net-(C12-Pad2)") + (add_net "Net-(C15-Pad2)") + (add_net "Net-(C17-Pad2)") + (add_net "Net-(C207-Pad1)") + (add_net "Net-(C208-Pad1)") + (add_net "Net-(C208-Pad2)") + (add_net "Net-(C5-Pad1)") + (add_net "Net-(C70-Pad2)") + (add_net "Net-(C71-Pad2)") + (add_net "Net-(C75-Pad2)") + (add_net "Net-(C78-Pad2)") + (add_net "Net-(C90-Pad2)") + (add_net "Net-(C93-Pad2)") + (add_net "Net-(IC1-Pad3)") + (add_net "Net-(JP2-Pad2)") + (add_net "Net-(LED1-Pad1)") + (add_net "Net-(LED10-Pad1)") + (add_net "Net-(LED11-Pad1)") + (add_net "Net-(LED12-Pad1)") + (add_net "Net-(LED13-Pad1)") + (add_net "Net-(LED14-Pad1)") + (add_net "Net-(LED15-Pad1)") + (add_net "Net-(LED16-Pad1)") + (add_net "Net-(LED17-Pad1)") + (add_net "Net-(LED18-Pad1)") + (add_net "Net-(LED18-Pad2)") + (add_net "Net-(LED2-Pad1)") + (add_net "Net-(LED3-Pad1)") + (add_net "Net-(LED4-Pad1)") + (add_net "Net-(LED9-Pad1)") + (add_net "Net-(Q1-Pad1)") + (add_net "Net-(Q5-Pad1)") + (add_net "Net-(Q5-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(R3-Pad2)") + (add_net "Net-(R32-Pad2)") + (add_net "Net-(R33-Pad2)") + (add_net "Net-(R52-Pad1)") + (add_net "Net-(R53-Pad2)") + (add_net "Net-(R54-Pad1)") + (add_net "Net-(R55-Pad2)") + (add_net "Net-(R65-Pad1)") + (add_net "Net-(R66-Pad1)") + (add_net "Net-(R67-Pad1)") + (add_net "Net-(R8-Pad1)") + (add_net Net1) + (add_net OSC_IN) + (add_net OSC_OUT) + (add_net POK_VCCAUX) + (add_net POK_VCCINT) + (add_net POK_VCCO) + (add_net PWR_18V) + (add_net PWR_ENA_VCCAUX) + (add_net PWR_ENA_VCCINT) + (add_net PWR_ENA_VCCO) + (add_net RAW_NOISE) + (add_net RTC_MFP) + (add_net RTC_SCL) + (add_net RTC_SDA) + (add_net SPI_A_TRISTATE) + (add_net SPI_B_TRISTATE) + (add_net SWDCLK) + (add_net SWDIO) + (add_net VCAP1) + (add_net VCAP2) + (add_net VCCO_3V3) + (add_net VCC_5V0) + ) + + (net_class FMC FMC + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FMC_A0) + (add_net FMC_A1) + (add_net FMC_A10) + (add_net FMC_A11) + (add_net FMC_A12) + (add_net FMC_A13) + (add_net FMC_A14) + (add_net FMC_A15) + (add_net FMC_A16) + (add_net FMC_A17) + (add_net FMC_A18) + (add_net FMC_A19) + (add_net FMC_A2) + (add_net FMC_A20) + (add_net FMC_A21) + (add_net FMC_A22) + (add_net FMC_A23) + (add_net FMC_A24) + (add_net FMC_A25) + (add_net FMC_A3) + (add_net FMC_A4) + (add_net FMC_A5) + (add_net FMC_A6) + (add_net FMC_A7) + (add_net FMC_A8) + (add_net FMC_A9) + (add_net FMC_CLK) + (add_net FMC_D0) + (add_net FMC_D1) + (add_net FMC_D10) + (add_net FMC_D11) + (add_net FMC_D12) + (add_net FMC_D13) + (add_net FMC_D14) + (add_net FMC_D15) + (add_net FMC_D16) + (add_net FMC_D17) + (add_net FMC_D18) + (add_net FMC_D19) + (add_net FMC_D2) + (add_net FMC_D20) + (add_net FMC_D21) + (add_net FMC_D22) + (add_net FMC_D23) + (add_net FMC_D24) + (add_net FMC_D25) + (add_net FMC_D26) + (add_net FMC_D27) + (add_net FMC_D28) + (add_net FMC_D29) + (add_net FMC_D3) + (add_net FMC_D30) + (add_net FMC_D31) + (add_net FMC_D4) + (add_net FMC_D5) + (add_net FMC_D6) + (add_net FMC_D7) + (add_net FMC_D8) + (add_net FMC_D9) + (add_net FMC_NBL0) + (add_net FMC_NBL1) + (add_net FMC_NBL2) + (add_net FMC_NBL3) + (add_net FMC_NE1) + (add_net FMC_NL) + (add_net FMC_NOE) + (add_net FMC_NWAIT) + (add_net FMC_NWE) + (add_net FMC_SDCKE0) + (add_net FMC_SDCKE1) + (add_net FMC_SDCLK) + (add_net FMC_SDNCAS) + (add_net FMC_SDNE0) + (add_net FMC_SDNE1) + (add_net FMC_SDNRAS) + (add_net FMC_SDNWE) + ) + + (net_class FPGA_GPIO FPGA_GPIO + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FPGA_GPIO_A_0) + (add_net FPGA_GPIO_A_1) + (add_net FPGA_GPIO_A_2) + (add_net FPGA_GPIO_A_3) + (add_net FPGA_GPIO_A_4) + (add_net FPGA_GPIO_A_5) + (add_net FPGA_GPIO_A_6) + (add_net FPGA_GPIO_A_7) + (add_net FPGA_GPIO_B_0) + (add_net FPGA_GPIO_B_1) + (add_net FPGA_GPIO_B_2) + (add_net FPGA_GPIO_B_3) + (add_net FPGA_GPIO_B_4) + (add_net FPGA_GPIO_B_5) + (add_net FPGA_GPIO_B_6) + (add_net FPGA_GPIO_B_7) + ) + + (net_class USB USB + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net D1_N) + (add_net D1_P) + (add_net DM_N) + (add_net DM_P) + (add_net USB_MGMT_N) + (add_net USB_MGMT_P) + (add_net USB_N) + (add_net USB_P) + ) + + (module Cryptech_Alpha_Footprints:_HDR1X10_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 31.5 6) + (path /539EEC0F) + (attr smd) + (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 10-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115)." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 19 AVR_GPIO_1)) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 25 AVR_GPIO_7)) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 24 AVR_GPIO_6)) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 23 AVR_GPIO_5)) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 22 AVR_GPIO_4)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 21 AVR_GPIO_3)) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 18 AVR_GPIO_0)) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.16075 -31.8) + (path /539EEC0F) + (attr smd) + (fp_text reference JP6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -0.00001 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -0.00001 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz -11.80693582267761 5.675121914768218 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -99.0854) + (path /539EEC0F) + (attr smd) + (fp_text reference C1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -94.0689) + (path /539EEC0F) + (attr smd) + (fp_text reference C2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -89.0524) + (path /539EEC0F) + (attr smd) + (fp_text reference C3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 26.1 -84.7) + (path /539EEC0F) + (attr smd) + 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360 90)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24.003 -63.0936) + (path /539EEC0F) + (attr smd) + (fp_text reference C211 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module 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Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.3512 -15.7226) + (path /539EEC0F) + (attr smd) + (fp_text reference FB1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20.7528 -14.9192) + (path /539EEC0F) + (attr smd) + (fp_text reference FB2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 1 smd rect (at -0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 93.218 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 91.186 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.4528 -84.2772) + (path /539EEC0F) + (attr smd) + (fp_text reference FB5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 7.7978 -33.147) + (path /539EEC0F) + (attr smd) + (fp_text reference FB6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.624 -58.2168) + (path /539EEC0F) + (attr smd) + (fp_text reference FB7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad 1 smd rect (at 0 1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 33.1552 -51.028) + (path /539EEC0F) + (attr smd) + (fp_text reference IC1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 207 KSM_PROM_CS_N)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 208 KSM_PROM_MISO)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 244 "Net-(IC1-Pad3)")) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 KSM_PROM_SCLK)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 209 KSM_PROM_MOSI)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.356 -38.3524) + (path /539EEC0F) + (attr smd) + (fp_text reference IC2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 2 smd rect (at 5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 10 ARM_FPGA_CFG_CS_N)) + (pad 3 smd rect (at 5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_CFG_MISO)) + (pad 4 smd rect (at 5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 13 ARM_FPGA_CFG_SCLK)) + (pad 5 smd rect (at 5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 6 smd rect (at 5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 12 ARM_FPGA_CFG_MOSI)) + (pad 7 smd rect (at 5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 8 smd rect (at 5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 13 smd rect (at -5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 129 FPGA_CFG_SCLK)) + (pad 14 smd rect (at -5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 15 smd rect (at -5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 127 FPGA_CFG_MOSI)) + (pad 16 smd rect (at -5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 17 smd rect (at -5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 18 smd rect (at -5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 19 smd rect (at -5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 20 smd rect (at -5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 9 smd rect (at 5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 10 smd rect (at 5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at -5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 11 ARM_FPGA_CFG_MISO)) + (pad 11 smd rect (at -5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 121 FPGA_CFG_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5368 -25.2832) + (path /539EEC0F) + (attr smd) + (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.0918 -30.464) + (path /539EEC0F) + (attr smd) + (fp_text reference IC4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 11 smd rect (at 5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad 12 smd rect (at 4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 10 smd rect (at 5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 20 smd rect (at -5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at -4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 18 smd rect (at -3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 17 smd rect (at -1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 16 smd rect (at -0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 15 smd rect (at 0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad 14 smd rect (at 1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 13 smd rect (at 3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 221 MKM_FPGA_SCK)) + (pad 8 smd rect (at 3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 7 smd rect (at 1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 6 smd rect (at 0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 smd rect (at -0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 4 smd rect (at -1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 3 smd rect (at -3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 219 MKM_FPGA_MISO)) + (pad 2 smd rect (at -4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 1 smd rect (at -5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 51.816 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 41 D1_N)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 42 D1_P)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 69.1134 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 DM_P)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 3 DM_N)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.78379 -20.4216) + (path /539EEC0F) + (attr smd) + (fp_text reference J1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 278 NRST)) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 295 SWDIO)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 294 SWDCLK)) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl + (offset (xyz 0.006349999904632569 0.08635999870300293 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 360)) + ) + (model wrlshp/670BFB14-85C2.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.04639 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 206 FT_VREGIN)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 299 USB_P)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 298 USB_N)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 195 FT_RXD1)) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 197 FT_TXD1)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.90459 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 296 USB_MGMT_N)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 297 USB_MGMT_P)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_694106301002_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20 18.4) + (path /539EEC0F) + (attr smd) + (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth Power Connector 5.5x2.1mm Barrel" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 284 PWR_18V)) + (model wrlshp/PJ-002A.wrl + (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 180 270)) + ) + (model wrlshp/51D2E761-0F4D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 64.6468 -91.7448) + (path /539EEC0F) + (attr smd) + (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 5 15V_LDO_ENABLE)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.117 -31.1658) + (path /539EEC0F) + (attr smd) + (fp_text reference JP3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 214 MKM_AVR_SCK)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 39 AVR_RESET)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-3_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.67933 1.5) + (path /539EEC0F) + (attr smd) + (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_aw_108_03-t.wrl + (offset (xyz 0.05003799924850464 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/836C6F64-A2E5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 18.25 -29.475) + (path /539EEC0F) + (attr smd) + (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 123 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 246 "Net-(LED1-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 247 "Net-(LED2-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 248 "Net-(LED3-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 43.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 249 "Net-(LED4-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 34.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 250 "Net-(LED9-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 251 "Net-(LED10-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED11 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 252 "Net-(LED11-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 32.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 253 "Net-(LED12-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 254 "Net-(LED13-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 130 FPGA_DONE_INT)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 52.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 255 "Net-(LED14-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 256 "Net-(LED15-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 54.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 257 "Net-(LED16-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 50.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED17 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 258 "Net-(LED17-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 76.13225 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED18 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 259 "Net-(LED18-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 72.452 -95.2388) + (path /539EEC0F) + (attr smd) + (fp_text reference Q1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.3732 -92.7862) + (path /539EEC0F) + (attr smd) + (fp_text reference Q2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (pad 2 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 276 NOISE_IN)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.3 -34.975) + (path /539EEC0F) + (attr smd) + (fp_text reference Q3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Abracon 25MHz 10pF 4-pin 3.2 x 2.5mm crystal" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 280 OSC_OUT)) + (pad 2 smd rect (at -1.0922 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 228 "Net-(C17-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.3064 -73.0504) + (path /539EEC0F) + (attr smd) + (fp_text reference Q4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 155 FPGA_INIT_B_INT)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 156 FPGA_INIT_B)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_ASF_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 67.9704 -84.709) + (path /539EEC0F) + (attr smd) + (fp_text reference Q5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at -1.0922 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -1.0922 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 263 "Net-(Q5-Pad3)")) + (pad 1 smd rect (at 1.1302 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 262 "Net-(Q5-Pad1)")) + (pad 2 smd rect (at 1.1302 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 15.7398 -42.4106) + (path /539EEC0F) + (attr smd) + (fp_text reference Q6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 283 POK_VCCO)) + (pad 2 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.5 -81.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 1%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 264 "Net-(R1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 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B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 64.4906 -82.931) + (path /539EEC0F) + (attr smd) + (fp_text reference R4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 133 FPGA_GCLK)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 263 "Net-(Q5-Pad3)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 71.75 -99.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 132 FPGA_ENTROPY_DISABLE)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 71.75 -98.25) + (path /539EEC0F) + (attr smd) + (fp_text reference R6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 71 -89.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 5 15V_LDO_ENABLE)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.5778 -73.1774) + (path /539EEC0F) + (attr smd) + (fp_text reference R8 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 1%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 266 "Net-(R8-Pad1)")) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (model 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0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 47 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R92 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 15 ARM_LED2)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 246 "Net-(LED1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R93 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 248 "Net-(LED3-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 14 ARM_LED1)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 43 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R94 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 17 ARM_LED4)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 247 "Net-(LED2-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R95 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 250 "Net-(LED9-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 35 AVR_LED2)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R96 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 34 AVR_LED1)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 252 "Net-(LED11-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 26 -7.5) + (path /539EEC0F) + (attr smd) + (fp_text reference R97 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 251 "Net-(LED10-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 37 AVR_LED4)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 79 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R98 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 152 FPGA_GPIO_LED_2)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 257 "Net-(LED16-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 77 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R99 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 255 "Net-(LED14-Pad1)")) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 153 FPGA_GPIO_LED_3)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 75 -7) + (path /539EEC0F) + (attr smd) + (fp_text reference R100 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 150 FPGA_GPIO_LED_0)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 258 "Net-(LED17-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_WE-SHC_36103205_NO_CREAM_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 83.82 -87.7454) + (path /539EEC0F) + (attr smd) + (fp_text reference S1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "WE-SHC Shielding cabinet" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 10.2616 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_TACTILE_SWITCH_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 62.8 -5.3608) + (path /539EEC0F) + (attr smd) + (fp_text reference S2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Tacktile switch" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-8_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 40.3 -1.3) + (path /539EEC0F) + (attr smd) + (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/PLS-8.wrl + (offset (xyz 8.889999866485596 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/A962434E-CFE5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.58299 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 138 FPGA_GPIO_A_4)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 135 FPGA_GPIO_A_1)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 134 FPGA_GPIO_A_0)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 36.79919 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 143 FPGA_GPIO_B_1)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 145 FPGA_GPIO_B_3)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 146 FPGA_GPIO_B_4)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 148 FPGA_GPIO_B_6)) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 149 FPGA_GPIO_B_7)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.2208 -88.1634) + (path /539EEC0F) + (attr smd) + (fp_text reference T1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + (pad 2 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 -0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.201 -82.7532) + (path /539EEC0F) + (attr smd) + (fp_text reference T2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 8 "Net-(C15-Pad2)")) + (pad 2 smd rect (at -0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0 -1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.3158 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.1436 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + ) + + (module Cryptech_Alpha_Footprints:_NDY_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.2758 -78.2828) + (path /539EEC0F) + (attr smd) + (fp_text reference U1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 3 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 265 "Net-(R3-Pad2)")) + (pad 5 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 266 "Net-(R8-Pad1)")) + (pad TP1 smd rect (at -9.525 0 90) (size 9.144 13.3858) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 8 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 225 "Net-(C5-Pad1)")) + (pad 9 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 11 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + ) + + (module Cryptech_Alpha_Footprints:_TSOT-8-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 70.5 -89.75) + (path /539EEC0F) + (attr smd) + (fp_text reference U2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Micropower, Low Noise, 100mA LDO, Linear Regulator" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 5 15V_LDO_ENABLE)) + (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 6 15V_STABLE)) + (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 226 "Net-(C11-Pad1)")) + (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 227 "Net-(C12-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23-5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 77.3684 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference U3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Single Inverter with Schmitt-Trigger Input" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at -1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd rect (at -1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad 3 smd rect (at 1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd rect (at 1.35 0 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (pad 1 smd oval (at 1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/User Library-SOT23-5-1.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/612DFB50-5309.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSQFP50P3000X3000X160-208N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 48.6918 -32.6136) + (path /539EEC0F) + (attr smd) + (fp_text reference U4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 208 smd oval (at -12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 207 smd oval (at -12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 206 smd oval (at -11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 205 smd oval (at -11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 204 smd oval (at -10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 203 smd oval (at -10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 202 smd oval (at -9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 201 smd oval (at -9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 104 FMC_NBL1)) + (pad 200 smd oval (at -8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 103 FMC_NBL0)) + (pad 199 smd oval (at -8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 198 smd oval (at -7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 197 smd oval (at -7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 40 BOOT0)) + (pad 196 smd oval (at -6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 108 FMC_NL)) + (pad 195 smd oval (at -6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 117 FMC_SDNE1)) + (pad 194 smd oval (at -5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 113 FMC_SDCKE1)) + (pad 193 smd oval (at -5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 192 smd oval (at -4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 191 smd oval (at -4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 115 FMC_SDNCAS)) + (pad 190 smd oval (at -3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 17 ARM_LED4)) + (pad 189 smd oval (at -3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 16 ARM_LED3)) + (pad 188 smd oval (at -2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 15 ARM_LED2)) + (pad 187 smd oval (at -2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 14 ARM_LED1)) + (pad 186 smd oval (at -1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 185 smd oval (at -1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 184 smd oval (at -0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 183 smd oval (at -0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_A25)) + (pad 182 smd oval (at 0.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_A24)) + (pad 181 smd oval (at 0.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 180 smd oval (at 1.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 179 smd oval (at 1.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 178 smd oval (at 2.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 177 smd oval (at 2.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 131 FPGA_DONE)) + (pad 176 smd oval (at 3.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 175 smd oval (at 3.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 160 FPGA_IRQ_N_3)) + (pad 174 smd oval (at 4.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 159 FPGA_IRQ_N_2)) + (pad 173 smd oval (at 4.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 107 FMC_NE1)) + (pad 172 smd oval (at 5.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 110 FMC_NWAIT)) + (pad 171 smd oval (at 5.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 170 smd oval (at 6.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 169 smd oval (at 6.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 111 FMC_NWE)) + (pad 168 smd oval (at 7.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 109 FMC_NOE)) + (pad 167 smd oval (at 7.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_CLK)) + (pad 166 smd oval (at 8.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 165 smd oval (at 8.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad 164 smd oval (at 9.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad 163 smd oval (at 9.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 162 smd oval (at 10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 161 smd oval (at 10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 160 smd oval (at 11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 159 smd oval (at 11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 294 SWDCLK)) + (pad 158 smd oval (at 12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 157 smd oval (at 12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad 156 smd oval (at 14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad 155 smd oval (at 14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad 154 smd oval (at 14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad 153 smd oval (at 14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad 152 smd oval (at 14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad 151 smd oval (at 14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad 150 smd oval (at 14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 149 smd oval (at 14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 148 smd oval (at 14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 301 VCAP2)) + (pad 147 smd oval (at 14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 295 SWDIO)) + (pad 146 smd oval (at 14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 179 FT_MGMT_CTS)) + (pad 145 smd oval (at 14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 181 FT_MGMT_RTS)) + (pad 144 smd oval (at 14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 185 FT_MGMT_TXD)) + (pad 143 smd oval (at 14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 183 FT_MGMT_RXD)) + (pad 142 smd oval (at 14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 180 FT_MGMT_DTR)) + (pad 141 smd oval (at 14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 140 smd oval (at 14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 139 smd oval (at 14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 138 smd oval (at 14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 137 smd oval (at 14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 136 smd oval (at 14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 135 smd oval (at 14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 114 FMC_SDCLK)) + (pad 134 smd oval (at 14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 133 smd oval (at 14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 132 smd oval (at 14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad 131 smd oval (at 14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad 130 smd oval (at 14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_A13)) + (pad 129 smd oval (at 14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad 128 smd oval (at 14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 127 smd oval (at 14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 126 smd oval (at 14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 125 smd oval (at 14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 124 smd oval (at 14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 123 smd oval (at 14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 158 FPGA_IRQ_N_1)) + (pad 122 smd oval (at 14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 157 FPGA_IRQ_N_0)) + (pad 121 smd oval (at 14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 120 smd oval (at 14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 169 FPGA_PROGRAM_B)) + (pad 119 smd oval (at 14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 156 FPGA_INIT_B)) + (pad 118 smd oval (at 14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 117 smd oval (at 14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad 116 smd oval (at 14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad 115 smd oval (at 14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 114 smd oval (at 14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 113 smd oval (at 14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_A18)) + (pad 112 smd oval (at 14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_A17)) + (pad 111 smd oval (at 14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_A16)) + (pad 110 smd oval (at 14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad 109 smd oval (at 14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad 108 smd oval (at 14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad 107 smd oval (at 14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 12 ARM_FPGA_CFG_MOSI)) + (pad 106 smd oval (at 14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 11 ARM_FPGA_CFG_MISO)) + (pad 105 smd oval (at 14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 13 ARM_FPGA_CFG_SCLK)) + (pad 104 smd oval (at 12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 10 ARM_FPGA_CFG_CS_N)) + (pad 103 smd oval (at 12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 102 smd oval (at 11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad 101 smd oval (at 11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad 100 smd oval (at 10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad 99 smd oval (at 10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad 98 smd oval (at 9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad 97 smd oval (at 9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 26 AVR_GPIO_ARM_0)) + (pad 96 smd oval (at 8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 27 AVR_GPIO_ARM_1)) + (pad 95 smd oval (at 8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 94 smd oval (at 7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 93 smd oval (at 7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 92 smd oval (at 6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 300 VCAP1)) + (pad 91 smd oval (at 6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 28 AVR_GPIO_ARM_2)) + (pad 90 smd oval (at 5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 29 AVR_GPIO_ARM_3)) + (pad 89 smd oval (at 5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad 88 smd oval (at 4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad 87 smd oval (at 4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad 86 smd oval (at 3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad 85 smd oval (at 3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad 84 smd oval (at 2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad 83 smd oval (at 2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 82 smd oval (at 1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 81 smd oval (at 1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad 80 smd oval (at 0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad 79 smd oval (at 0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad 78 smd oval (at -0.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad 77 smd oval (at -0.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad 76 smd oval (at -1.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad 75 smd oval (at -1.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad 74 smd oval (at -2.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad 73 smd oval (at -2.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 72 smd oval (at -3.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 71 smd oval (at -3.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad 70 smd oval (at -4.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 118 FMC_SDNRAS)) + (pad 69 smd oval (at -4.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 68 smd oval (at -5.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 67 smd oval (at -5.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 66 smd oval (at -6.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 65 smd oval (at -6.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 64 smd oval (at -7.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 63 smd oval (at -7.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 62 smd oval (at -8.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 61 smd oval (at -8.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 207 KSM_PROM_CS_N)) + (pad 60 smd oval (at -9.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 59 smd oval (at -9.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 58 smd oval (at -10.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 57 smd oval (at -10.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at -11.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 209 KSM_PROM_MOSI)) + (pad 55 smd oval (at -11.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 208 KSM_PROM_MISO)) + (pad 54 smd oval (at -12.25 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 210 KSM_PROM_SCLK)) + (pad 53 smd oval (at -12.75 -14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 178 FT_DTR)) + (pad 52 smd oval (at -14.75 -12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 51 smd oval (at -14.75 -12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 50 smd oval (at -14.75 -11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 198 FT_TXD)) + (pad 49 smd oval (at -14.75 -11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 291 RTC_SDA)) + (pad 48 smd oval (at -14.75 -10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 290 RTC_SCL)) + (pad 47 smd oval (at -14.75 -10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 289 RTC_MFP)) + (pad 46 smd oval (at -14.75 -9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -14.75 -9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 196 FT_RXD)) + (pad 44 smd oval (at -14.75 -8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 177 FT_CTS)) + (pad 43 smd oval (at -14.75 -8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 194 FT_RTS)) + (pad 42 smd oval (at -14.75 -7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 41 smd oval (at -14.75 -7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 40 smd oval (at -14.75 -6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 39 smd oval (at -14.75 -6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 38 smd oval (at -14.75 -5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 112 FMC_SDCKE0)) + (pad 37 smd oval (at -14.75 -5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 116 FMC_SDNE0)) + (pad 36 smd oval (at -14.75 -4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at -14.75 -4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FMC_SDNWE)) + (pad 34 smd oval (at -14.75 -3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 278 NRST)) + (pad 33 smd oval (at -14.75 -3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 280 OSC_OUT)) + (pad 32 smd oval (at -14.75 -2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 279 OSC_IN)) + (pad 31 smd oval (at -14.75 -2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 30 smd oval (at -14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 29 smd oval (at -14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 28 smd oval (at -14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 26 smd oval (at -14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 25 smd oval (at -14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 24 smd oval (at -14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 23 smd oval (at -14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 22 smd oval (at -14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 21 smd oval (at -14.75 2.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 123 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 20 smd oval (at -14.75 3.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 19 smd oval (at -14.75 3.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 18 smd oval (at -14.75 4.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad 17 smd oval (at -14.75 4.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad 16 smd oval (at -14.75 5.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad 15 smd oval (at -14.75 5.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 14 smd oval (at -14.75 6.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at -14.75 6.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 12 smd oval (at -14.75 7.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad 11 smd oval (at -14.75 7.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 10 smd oval (at -14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 9 smd oval (at -14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 8 smd oval (at -14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 7 smd oval (at -14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 6 smd oval (at -14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 267 "Net-(R32-Pad2)")) + (pad 5 smd oval (at -14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad 4 smd oval (at -14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad 3 smd oval (at -14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad 2 smd oval (at -14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad 1 smd oval (at -14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (model wrlshp/1B9BC620-BA33.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.1704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 44 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 45 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 95 FMC_D24)) + (pad 46 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 96 FMC_D25)) + (pad 48 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 97 FMC_D26)) + (pad 49 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 50 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 98 FMC_D27)) + (pad 51 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 99 FMC_D28)) + (pad 52 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 53 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 100 FMC_D29)) + (pad 54 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 101 FMC_D30)) + (pad 55 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 56 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 102 FMC_D31)) + (pad 57 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 58 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 59 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 106 FMC_NBL3)) + (pad 60 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 47 FMC_A3)) + (pad 61 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 48 FMC_A4)) + (pad 62 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 49 FMC_A5)) + (pad 63 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 50 FMC_A6)) + (pad 64 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 51 FMC_A7)) + (pad 65 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 52 FMC_A8)) + (pad 66 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 53 FMC_A9)) + (pad 67 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 112 FMC_SDCKE0)) + (pad 68 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 114 FMC_SDCLK)) + (pad 69 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 56 FMC_A12)) + (pad 70 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 71 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 104 FMC_NBL1)) + (pad 72 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 73 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 74 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 79 FMC_D8)) + (pad 75 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 76 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 80 FMC_D9)) + (pad 77 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 81 FMC_D10)) + (pad 78 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 79 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 82 FMC_D11)) + (pad 80 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 83 FMC_D12)) + (pad 81 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 82 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 84 FMC_D13)) + (pad 83 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 85 FMC_D14)) + (pad 84 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 85 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 86 FMC_D15)) + (pad 86 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 94 FMC_D23)) + (pad 41 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 40 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 93 FMC_D22)) + (pad 39 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 92 FMC_D21)) + (pad 38 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 91 FMC_D20)) + (pad 36 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 90 FMC_D19)) + (pad 35 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 34 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 89 FMC_D18)) + (pad 33 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 88 FMC_D17)) + (pad 32 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 31 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 87 FMC_D16)) + (pad 30 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 28 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 105 FMC_NBL2)) + (pad 27 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 46 FMC_A2)) + (pad 26 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 45 FMC_A1)) + (pad 25 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 44 FMC_A0)) + (pad 24 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 54 FMC_A10)) + (pad 23 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 59 FMC_A15)) + (pad 22 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 58 FMC_A14)) + (pad 21 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 55 FMC_A11)) + (pad 20 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 116 FMC_SDNE0)) + (pad 19 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 118 FMC_SDNRAS)) + (pad 18 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 115 FMC_SDNCAS)) + (pad 17 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 119 FMC_SDNWE)) + (pad 16 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 103 FMC_NBL0)) + (pad 15 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 14 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 78 FMC_D7)) + (pad 12 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 11 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 77 FMC_D6)) + (pad 10 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 76 FMC_D5)) + (pad 9 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 75 FMC_D4)) + (pad 7 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 74 FMC_D3)) + (pad 6 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 73 FMC_D2)) + (pad 4 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 72 FMC_D1)) + (pad 3 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 71 FMC_D0)) + (pad 1 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.6704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad 3 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad 5 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad 6 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad 8 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad 9 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad 11 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad 12 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad 14 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 16 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 103 FMC_NBL0)) + (pad 17 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FMC_SDNWE)) + (pad 18 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 115 FMC_SDNCAS)) + (pad 19 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 118 FMC_SDNRAS)) + (pad 20 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 117 FMC_SDNE1)) + (pad 21 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad 23 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad 24 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad 25 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad 26 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad 27 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad 28 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 29 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 30 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 31 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad 32 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad 34 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad 35 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 36 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad 37 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad 38 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 39 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad 40 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad 41 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad 43 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 86 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 85 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad 84 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 83 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad 82 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad 81 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 80 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad 79 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad 78 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 77 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad 76 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad 75 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 74 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad 73 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 72 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 71 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 104 FMC_NBL1)) + (pad 70 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 69 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad 68 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 114 FMC_SDCLK)) + (pad 67 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 113 FMC_SDCKE1)) + (pad 66 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad 64 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad 63 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad 62 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 61 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 60 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 59 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 58 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 57 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad 55 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 54 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 53 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 52 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 51 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 50 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad 49 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 48 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad 47 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad 46 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 45 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad 44 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.6 -43.45) + (path /539EEC0F) + (attr smd) + (fp_text reference U7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RTCC, I2C, 1K EE, 64B SRAM, 8SOIC" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 smd rect (at 2.6924 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 7 smd rect (at 2.6924 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 289 RTC_MFP)) + (pad 6 smd rect (at 2.6924 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 290 RTC_SCL)) + (pad 5 smd rect (at 2.6924 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 291 RTC_SDA)) + (pad 4 smd rect (at -2.7178 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -2.7178 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 2 smd rect (at -2.7178 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + (pad 1 smd rect (at -2.7178 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 13.8186 -9.636) + (path /539EEC0F) + (attr smd) + (fp_text reference U8 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 48 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 46 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 45 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 41 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 40 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 39 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 38 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 203 FT_VCCORE)) + (pad 37 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 201 FT_VCCA)) + (pad 36 smd rect (at -4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 35 smd rect (at -4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 34 smd rect (at -4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 193 FT_RESET)) + (pad 33 smd rect (at -4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at -4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at -4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at -4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at -4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at -4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 23 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 21 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 178 FT_DTR)) + (pad 16 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 177 FT_CTS)) + (pad 15 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 194 FT_RTS)) + (pad 14 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 195 FT_RXD1)) + (pad 13 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 197 FT_TXD1)) + (pad 12 smd rect (at 4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 11 smd rect (at 4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 8 smd rect (at 4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 7 smd rect (at 4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 6 smd rect (at 4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 5 smd rect (at 4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 191 FT_REF)) + (pad 4 smd rect (at 4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (pad 2 smd rect (at 4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 1 smd rect (at 4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.3854 -17.8496) + (path /539EEC0F) + (attr smd) + (fp_text reference U9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 190 FT_REF1)) + (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 181 FT_MGMT_RTS)) + (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 179 FT_MGMT_CTS)) + (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 180 FT_MGMT_DTR)) + (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 192 FT_RESET1)) + (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 200 FT_VCCA1)) + (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 202 FT_VCCORE1)) + (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-32_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 53.0832 -38.55) + (path /539EEC0F) + (attr smd) + (fp_text reference U10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "IC, MCU, 8KB, FLASH, 20MHZ, TQFP-32" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 smd rect (at -2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 21 AVR_GPIO_3)) + (pad 3 smd rect (at -1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 22 AVR_GPIO_4)) + (pad 4 smd rect (at -0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 5 smd rect (at 0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 23 AVR_GPIO_5)) + (pad 7 smd rect (at 2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 24 AVR_GPIO_6)) + (pad 8 smd rect (at 2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 25 AVR_GPIO_7)) + (pad 9 smd rect (at 4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 34 AVR_LED1)) + (pad 10 smd rect (at 4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 35 AVR_LED2)) + (pad 11 smd rect (at 4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 36 AVR_LED3)) + (pad 12 smd rect (at 4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 37 AVR_LED4)) + (pad 13 smd rect (at 4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + (pad 14 smd rect (at 4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 15 smd rect (at 4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + (pad 16 smd rect (at 4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 17 smd rect (at 2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 26 AVR_GPIO_ARM_0)) + (pad 18 smd rect (at 2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at 1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 27 AVR_GPIO_ARM_1)) + (pad 20 smd rect (at 0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 28 AVR_GPIO_ARM_2)) + (pad 21 smd rect (at -0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 29 AVR_GPIO_ARM_3)) + (pad 23 smd rect (at -2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad 24 smd rect (at -2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad 25 smd rect (at -4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad 26 smd rect (at -4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad 27 smd rect (at -4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 28 smd rect (at -4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 29 smd rect (at -4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 39 AVR_RESET)) + (pad 30 smd rect (at -4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 31 smd rect (at -4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 18 AVR_GPIO_0)) + (pad 32 smd rect (at -4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 19 AVR_GPIO_1)) + (model "wrlshp/User Library-sot358-1.wrl" + (offset (xyz 0 -0.01066799983978271 0.7000011294870376)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/590BE70C-A1C3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.4418 -30.718) + (path /539EEC0F) + (attr smd) + (fp_text reference U12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "64K SPI Bus Low-Power Serial SRAM,SOIC-8" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 217 MKM_CS_N)) + (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 222 MKM_MISO)) + (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 223 MKM_MOSI)) + (pad 6 smd rect (at 0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 224 MKM_SCK)) + (pad 7 smd rect (at -0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 268 "Net-(R33-Pad2)")) + (pad 8 smd rect (at -1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 4 3V3_BATT)) + ) + + (module Cryptech_Alpha_Footprints:_BGA484C100P22X22_2300X2300X254_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.4534 -68.8848) + (path /539EEC0F) + (attr smd) + (fp_text reference U13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Xilinx FPGA: XC7A200TFBG484" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_A24)) + (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 153 FPGA_GPIO_LED_3)) + (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_A25)) + (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_A16)) + (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_A17)) + (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 111 FMC_NWE)) + (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_A18)) + (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 110 FMC_NWAIT)) + (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 219 MKM_FPGA_MISO)) + (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 152 FPGA_GPIO_LED_2)) + (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 108 FMC_NL)) + (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 109 FMC_NOE)) + (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_CLK)) + (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 107 FMC_NE1)) + (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 221 MKM_FPGA_SCK)) + (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_A13)) + (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 273 "Net-(R65-Pad1)")) + (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 154 FPGA_INIT_B_INT1)) + (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 165 FPGA_M0)) + (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 166 FPGA_M1)) + (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 167 FPGA_M2)) + (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 150 FPGA_GPIO_LED_0)) + (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 120 FPGA_CFG_CS_N1)) + (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 151 FPGA_GPIO_LED_1)) + (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 124 FPGA_CFG_MISO1)) + (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_CFG_MOSI1)) + (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 168 FPGA_PROGRAM_B1)) + (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 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0.45) (layers B.Cu B.Paste B.Mask)) + (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J16 smd circle (at -4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J15 smd circle (at -3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad J14 smd circle (at -2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu 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0.45) (layers B.Cu B.Paste B.Mask)) + (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 149 FPGA_GPIO_B_7)) + (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 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(size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 132 FPGA_ENTROPY_DISABLE)) + (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (model wrlshp/041B98A5-F02D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 35.4584 -76.5556) + (path /539EEC0F) + (attr smd) + (fp_text reference U14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad PAD39 smd oval (at 0 1.26 180) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 38 smd oval (at -1.905 -3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at -1.905 -2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at -1.905 -2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at -1.905 -1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 34 smd oval (at -1.905 -1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 33 smd oval (at -1.905 -0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 32 smd oval (at -1.905 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -1.905 0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 238 "Net-(C117-Pad2)")) + (pad 30 smd oval (at -1.905 1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 235 "Net-(C115-Pad1)")) + (pad 29 smd oval (at -1.905 1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 270 "Net-(R53-Pad2)")) + (pad 28 smd oval (at -1.905 2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 281 POK_VCCAUX)) + (pad 27 smd oval (at -1.905 2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 26 smd oval (at -1.905 3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 269 "Net-(R52-Pad1)")) + (pad 25 smd oval (at -1.27 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at -0.762 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at -0.254 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 0.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 0.75 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at 1.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 19 smd oval (at 1.9 3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 18 smd oval (at 1.9 2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at 1.9 2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at 1.9 1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at 1.9 1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at 1.9 0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at 1.9 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 12 smd oval (at 1.9 -0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 11 smd oval (at 1.9 -1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 10 smd oval (at 1.9 -1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 9 smd oval (at 1.9 -2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 8 smd oval (at 1.9 -2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 7 smd oval (at 1.9 -3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 6 smd oval (at 1.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 5 smd oval (at 0.75 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 4 smd oval (at 0.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at -0.254 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at -0.762 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd oval (at -1.27 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 10.8458 -41.0972) + (path /539EEC0F) + (attr smd) + (fp_text reference U15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 1.27 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at 0.762 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at 0.254 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd oval (at -0.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 5 smd oval (at -0.75 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 6 smd oval (at -1.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 7 smd oval (at -1.9 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 8 smd oval (at -1.9 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 9 smd oval (at -1.9 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 10 smd oval (at -1.9 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 11 smd oval (at -1.9 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 12 smd oval (at -1.9 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at -1.9 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at -1.9 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at -1.9 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at -1.9 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 18 smd oval (at -1.9 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 19 smd oval (at -1.9 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at -1.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 21 smd oval (at -0.75 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 22 smd oval (at -0.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 0.254 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.762 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 1.27 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at 1.905 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 271 "Net-(R54-Pad1)")) + (pad 27 smd oval (at 1.905 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 287 PWR_ENA_VCCO)) + (pad 28 smd oval (at 1.905 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 283 POK_VCCO)) + (pad 29 smd oval (at 1.905 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 272 "Net-(R55-Pad2)")) + (pad 30 smd oval (at 1.905 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 236 "Net-(C116-Pad1)")) + (pad 31 smd oval (at 1.905 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 240 "Net-(C118-Pad2)")) + (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at 1.905 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 34 smd oval (at 1.905 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at 1.905 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at 1.905 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at 1.905 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 38 smd oval (at 1.905 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad PAD39 smd oval (at 0 -1.26) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_QFN68_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.9842 -57.4802) + (path /539EEC0F) + (attr smd) + (fp_text reference U16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 5.5 -3.5052 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd oval (at 5.5 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd oval (at 5.5 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd oval (at 5.5 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.5 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 6 smd oval (at 5.5 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 7 smd oval (at 5.5 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 9 smd oval (at 5.5 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 10 smd oval (at 5.5 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 11 smd oval (at 5.5 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 12 smd oval (at 5.5 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 13 smd oval (at 5.5 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 14 smd oval (at 5.5 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at 5.5 3.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 16 smd oval (at 4.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 17 smd oval (at 4 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 18 smd oval (at 3.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 19 smd oval (at 3 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 20 smd oval (at 2.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 2 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 1.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 1 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 0 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at -0.508 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -1.016 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 28 smd oval (at -1.524 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 29 smd oval (at -2.0066 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 30 smd oval (at -2.5146 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -3.0226 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 32 smd oval (at -3.5052 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -4.0132 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 34 smd oval (at -4.5212 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 35 smd oval (at -5.5118 3.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 36 smd oval (at -5.5118 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 37 smd oval (at -5.5118 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 38 smd oval (at -5.5118 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 39 smd oval (at -5.5118 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 40 smd oval (at -5.5118 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 41 smd oval (at -5.5118 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 43 smd oval (at -5.5118 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 44 smd oval (at -5.5118 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -5.5118 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 46 smd oval (at -5.5118 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 47 smd oval (at -5.5118 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 48 smd oval (at -5.5118 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 49 smd oval (at -5.5118 -3.5052) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 50 smd oval (at -4.5212 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 51 smd oval (at -4.0132 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 274 "Net-(R66-Pad1)")) + (pad 52 smd oval (at -3.5052 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 53 smd oval (at -3.0226 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 54 smd oval (at -2.5146 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 282 POK_VCCINT)) + (pad 55 smd oval (at -2.0066 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 56 smd oval (at -1.524 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 243 "Net-(C208-Pad2)")) + (pad 57 smd oval (at -1.016 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 58 smd oval (at -0.508 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 59 smd oval (at 0 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 241 "Net-(C207-Pad1)")) + (pad 60 smd oval (at 0.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 61 smd oval (at 1 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 62 smd oval (at 1.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 63 smd oval (at 2 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 275 "Net-(R67-Pad1)")) + (pad 64 smd oval (at 2.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 65 smd oval (at 3 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 66 smd oval (at 3.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 67 smd oval (at 4 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 68 smd oval (at 4.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD69 smd oval (at -2.175 0.625 90) (size 5.35 2.35) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD70 smd oval (at 3.55 -2.65 180) (size 2.5 1.3) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_XTAL3215_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 19.275 -45.6) + (path /539EEC0F) + (attr smd) + (fp_text reference X1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 32.768kHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 23.075 -5.5) + (path /539EEC0F) + (attr smd) + (fp_text reference Y1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.8382 -1.1176 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 2 smd rect (at -0.8382 1.0922 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0.8636 1.0922 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (pad 4 smd rect (at 0.8636 -1.1176 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.525 -8.8) + (path /539EEC0F) + (attr smd) + (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.4 -62.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R35 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 167 FPGA_M2)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -59.1757) + (path /539EEC0F) + (attr smd) + (fp_text reference R36 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 166 FPGA_M1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -60.4076) + (path /539EEC0F) + (attr smd) + (fp_text reference R37 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer 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-80 -40 80 -20 0 1 10 f +P 2 0 1 10 0 -80 0 -100 +P 2 0 1 10 0 -20 0 0 +X 1 1 0 100 100 D 1 1 0 1 P +X 2 2 0 -200 100 U 1 1 0 1 P +ENDDRAW +ENDDEF +# +# C-EUC1210 +# +DEF C-EUC1210 IC 0 40 Y Y 1 F N +F0 "C" 80 -190 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -80 -80 80 -60 0 1 10 f +S -80 -40 80 -20 0 1 10 f +P 2 0 1 10 0 -80 0 -100 +P 2 0 1 10 0 -20 0 0 +X 1 1 0 100 100 D 1 1 0 1 P +X 2 2 0 -200 100 U 1 1 0 1 P +ENDDRAW +ENDDEF +# +# CP_E-035X080 +# +DEF CP_E-035X080 IC 0 40 Y Y 1 F N +F0 "C" 120 20 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -120 0 98 0 374 1 1 20 N -22 0 -42 59 +A -120 10 98 -382 -4 1 1 20 N -42 -50 -22 9 +P 2 0 1 10 -100 0 -20 0 +P 2 0 1 10 -20 0 -20 0 +P 2 0 1 10 20 -60 20 0 +P 2 0 1 10 20 0 20 70 +P 2 0 1 10 100 0 20 0 +X + 1 100 0 10 L 1 1 0 1 P +X - 2 -100 0 10 R 1 1 0 1 P +ENDDRAW +ENDDEF +# +# CRYSTALTHIN +# +DEF CRYSTALTHIN IC 0 40 Y Y 1 F N +F0 "Y" -100 120 60 H V L BNN +F1 "CRYSTALTHIN" 820 140 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -40 -70 -40 0 +P 2 0 1 10 -40 0 -100 0 +P 2 0 1 10 -40 0 -40 70 +P 2 0 1 10 -10 -60 -10 60 +P 2 0 1 10 -10 60 20 60 +P 2 0 1 10 20 -60 -10 -60 +P 2 0 1 10 20 60 20 -60 +P 2 0 1 10 40 -70 40 0 +P 2 0 1 10 40 0 40 70 +P 2 0 1 10 40 0 100 0 +X 1 1 -100 0 10 R 1 1 0 1 P +X 2 2 -100 -100 100 R 1 1 0 1 P +X 3 3 100 0 10 L 1 1 0 1 P +X 4 4 100 -100 100 L 1 1 0 1 P +ENDDRAW +ENDDEF +# +# EN5364QI +# +DEF EN5364QI IC 0 40 Y Y 1 F N +F0 "U" -450 2320 60 H V L BNN +F1 "EN5364QI" 110 2330 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -600 -1600 -600 2300 +P 2 0 1 10 -600 2300 700 2300 +P 2 0 1 10 700 -1600 -600 -1600 +P 2 0 1 10 700 2300 700 -1600 +X PGND 1 300 -1800 200 U 1 70 0 1 W +X VOUT 10 900 1600 200 L 70 70 0 1 W +X VOUT 11 900 1500 200 L 70 70 0 1 W +X VOUT 12 900 1400 200 L 70 70 0 1 W +X VOUT 13 900 1300 200 L 70 70 0 1 W +X NC 14 900 -1000 200 L 1 70 0 1 P +X NC 15 900 -1000 200 L 70 70 0 1 P +X NC 16 900 -1000 200 L 70 70 0 1 P +X NC 17 900 -1000 200 L 70 70 0 1 P +X NC 18 900 -1000 200 L 70 70 0 1 P +X NC 19 900 -1000 200 L 70 70 0 1 P +X PGND 2 300 -1800 200 U 70 70 0 1 W +X NC 20 900 -1000 200 L 70 70 0 1 P +X NC 21 900 -1000 200 L 70 70 0 1 P +X NC 22 900 -1000 200 L 70 70 0 1 P +X NC 23 900 -1000 200 L 70 70 0 1 P +X NC 24 900 -1000 200 L 70 70 0 1 P +X NC 25 900 -1000 200 L 70 70 0 1 P +X NC 26 900 -1000 200 L 70 70 0 1 P +X PGND 27 300 -1800 200 U 70 70 0 1 W +X PGND 28 300 -1800 200 U 70 70 0 1 W +X PGND 29 300 -1800 200 U 70 70 0 1 W +X PGND 3 300 -1800 200 U 70 70 0 1 W +X PGND 30 300 -1800 200 U 70 70 0 1 W +X PGND 31 300 -1800 200 U 70 70 0 1 W +X PGND 32 300 -1800 200 U 70 70 0 1 W +X PGND 33 300 -1800 200 U 70 70 0 1 W +X PVIN 34 -800 2200 200 R 70 70 0 1 W +X PVIN 35 -800 2100 200 R 70 70 0 1 W +X PVIN 36 -800 2000 200 R 70 70 0 1 W +X PVIN 37 -800 1900 200 R 70 70 0 1 W +X PVIN 38 -800 1800 200 R 70 70 0 1 W +X PVIN 39 -800 1700 200 R 70 70 0 1 W +X PGND 4 300 -1800 200 U 70 70 0 1 W +X PVIN 40 -800 1600 200 R 70 70 0 1 W +X PVIN 41 -800 1500 200 R 70 70 0 1 W +X PVIN 42 -800 1400 200 R 70 70 0 1 W +X PVIN 43 -800 1300 200 R 70 70 0 1 W +X NC 44 900 -1000 200 L 70 70 0 1 P +X NC 45 900 -1000 200 L 70 70 0 1 P +X NC 46 900 -1000 200 L 70 70 0 1 P +X NC 47 900 -1000 200 L 70 70 0 1 P +X S_OUT 48 900 -400 200 L 70 70 0 1 O +X S_IN 49 -800 100 200 R 70 70 0 1 P +X VOUT 5 900 2100 200 L 70 70 0 1 w +X M/S 50 -800 300 200 R 70 70 0 1 P +X EN_PB 51 -800 700 200 R 70 70 0 1 P +X ENABLE 52 -800 900 200 R 70 70 0 1 P +X AVIN 53 -800 1100 200 R 70 70 0 1 W +X POK 54 900 -1400 200 L 70 70 0 1 O +X AGND 55 -200 -1800 200 U 70 70 0 1 W +X VFB 56 900 700 200 L 70 70 0 1 P +X EAOUT 57 900 -600 200 L 70 70 0 1 O +X OCP_ADJ 58 -800 -1000 200 R 70 70 0 1 P +X SS 59 -800 -1400 200 R 70 70 0 1 P +X VOUT 6 900 2000 200 L 70 70 0 1 W +X S_DELAY 60 -800 -100 200 R 70 70 0 1 P +X MAR1 61 -800 -300 200 R 70 70 0 1 P +X MAR2 62 -800 -500 200 R 70 70 0 1 P +X VSENSE 63 900 100 200 L 70 70 0 1 P +X PGND 64 300 -1800 200 U 70 70 0 1 W +X PGND 65 300 -1800 200 U 70 70 0 1 W +X PGND 66 300 -1800 200 U 70 70 0 1 W +X PGND 67 300 -1800 200 U 70 70 0 1 W +X PGND 68 300 -1800 200 U 70 70 0 1 W +X VOUT 7 900 1900 200 L 70 70 0 1 W +X VOUT 8 900 1800 200 L 70 70 0 1 W +X VOUT 9 900 1700 200 L 70 70 0 1 W +X PGND PAD69 300 -1800 200 U 70 70 0 1 W +X PGND PAD70 300 -1800 200 U 70 70 0 1 W +ENDDRAW +ENDDEF +# +# EN6347QI +# +DEF EN6347QI IC 0 40 Y Y 1 F N +F0 "U" -360 1090 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -600 -900 600 -900 +P 2 0 1 10 -600 1000 -600 -900 +P 2 0 1 10 600 -900 600 1000 +P 2 0 1 10 600 1000 -600 1000 +X NC 1 800 -300 200 L 70 70 0 1 P +X VOUT 10 800 400 200 L 70 70 0 1 W +X VOUT 11 800 300 200 L 70 70 0 1 W +X NC 12 800 -300 200 L 70 70 0 1 P +X PGND 13 200 -1100 200 U 1 70 0 1 W +X PGND 14 200 -1100 200 U 1 70 0 1 W +X PGND 15 200 -1100 200 U 1 70 0 1 W +X PGND 16 200 -1100 200 U 1 70 0 1 W +X PGND 17 200 -1100 200 U 1 70 0 1 W +X PGND 18 200 -1100 200 U 1 70 0 1 W +X PVIN 19 -800 900 200 R 70 70 0 1 W +X NC 2 800 -300 200 L 70 70 0 1 P +X PVIN 20 -800 800 200 R 70 70 0 1 W +X PVIN 21 -800 700 200 R 70 70 0 1 W +X NC 22 800 -300 200 L 70 70 0 1 P +X NC 23 800 -300 200 L 70 70 0 1 P +X NC 24 800 -300 200 L 70 70 0 1 P +X NC 25 800 -300 200 L 70 70 0 1 P +X LLM/SYNC 26 -800 -100 200 R 70 70 0 1 P +X ENABLE 27 -800 300 200 R 70 70 0 1 P +X POK 28 800 -700 200 L 70 70 0 1 O +X RLLM 29 -800 -300 200 R 70 70 0 1 P +X NC 3 800 -300 200 L 70 70 0 1 P +X SS 30 -800 -700 200 R 70 70 0 1 P +X VFB 31 800 100 200 L 70 70 0 1 P +X AGND 32 -300 -1100 200 U 70 70 0 1 W +X AVIN 33 -800 500 200 R 70 70 0 1 W +X NC 34 800 -300 200 L 70 70 0 1 P +X NC 35 800 -300 200 L 70 70 0 1 P +X NC 36 800 -300 200 L 70 70 0 1 P +X NC 37 800 -300 200 L 70 70 0 1 P +X NC 38 800 -300 200 L 70 70 0 1 P +X NC 4 800 -300 200 L 70 70 0 1 P +X VOUT 5 800 900 200 L 70 70 0 1 w +X VOUT 6 800 800 200 L 70 70 0 1 W +X VOUT 7 800 700 200 L 70 70 0 1 W +X VOUT 8 800 600 200 L 70 70 0 1 W +X VOUT 9 800 500 200 L 70 70 0 1 W +X PGND PAD39 200 -1100 200 U 1 70 0 1 W +ENDDRAW +ENDDEF +# +# FERRITE_0603MP +# +DEF FERRITE_0603MP IC 0 40 Y Y 1 F N +F0 "FB" -80 -170 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -50 -40 50 -40 +P 2 0 1 10 -50 30 -50 -40 +P 2 0 1 10 50 -40 50 30 +P 2 0 1 10 50 30 -50 30 +X P$1 1 -100 0 100 R 1 1 0 1 P +X P$2 2 100 0 100 L 1 1 0 1 P +ENDDRAW +ENDDEF +# +# FPGA_VCCAUX_1V8 +# +DEF FPGA_VCCAUX_1V8 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FPGA_VCCAUX_1V8" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FPGA_VCCAUX_1V8 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FPGA_VCCINT_1V0 +# +DEF FPGA_VCCINT_1V0 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FPGA_VCCINT_1V0" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FPGA_VCCINT_1V0 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT232H_SERIAL +# +DEF FT232H_SERIAL IC 0 40 Y Y 1 F N +F0 "U" 1120 1210 60 H V L BNN +F1 "FT232H_SERIAL" -1120 1520 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -900 -1300 900 -1300 +P 2 0 1 10 -900 1300 -900 -1300 +P 2 0 1 10 900 -1300 900 1300 +P 2 0 1 10 900 1300 -900 1300 +X XCSI 1 -1100 -700 200 R 70 70 0 1 P +X GND 10 -100 -1500 200 U 70 70 0 1 W +X GND 11 0 -1500 200 U 70 70 0 1 W +X VCCIO 12 0 1500 200 D 70 70 0 1 W +X TXD 13 1100 1200 200 L 70 70 0 1 O +X RXD 14 1100 1100 200 L 70 70 0 1 P +X RTS# 15 1100 1000 200 L 70 70 0 1 O +X CTS# 16 1100 900 200 L 70 70 0 1 P +X DTR# 17 1100 800 200 L 70 70 0 1 O +X DSR# 18 1100 700 200 L 70 70 0 1 P +X DCD# 19 1100 600 200 L 70 70 0 1 P +X XCSO 2 -1100 -1000 200 R 70 70 0 1 P +X RI# 20 1100 500 200 L 70 70 0 1 P +X TXDEN 21 1100 300 200 L 70 70 0 1 O +X GND 22 100 -1500 200 U 70 70 0 1 W +X GND 23 200 -1500 200 U 70 70 0 1 W +X VCCIO 24 100 1500 200 D 70 70 0 1 W +X ACBUS1 25 1100 200 200 L 70 70 0 1 P +X ACBUS2 26 1100 100 200 L 70 70 0 1 P +X RXLED# 27 1100 0 200 L 70 70 0 1 O +X TXLED# 28 1100 -100 200 L 70 70 0 1 O +X ACBUS5 29 1100 -200 200 L 70 70 0 1 P +X VPHY 3 -200 1500 200 D 70 70 0 1 W +X ACBUS6 30 1100 -300 200 L 70 70 0 1 P +X PWRSAV# 31 1100 -400 200 L 70 70 0 1 P +X ACBUS8 32 1100 -500 200 L 70 70 0 1 P +X ACBUS9 33 1100 -600 200 L 70 70 0 1 P +X ~RESET 34 -1100 300 200 R 70 70 0 1 P +X GND 35 300 -1500 200 U 70 70 0 1 W +X GND 36 400 -1500 200 U 70 70 0 1 W +X VCCA 37 -1100 800 200 R 70 70 0 1 w +X VCCORE 38 -1100 900 200 R 70 70 0 1 w +X VCCD 39 -1100 1000 200 R 70 70 0 1 w +X AGND 4 -400 -1500 200 U 70 70 0 1 W +X VREGIN 40 -1100 1200 200 R 70 70 0 1 W +X AGND 41 -200 -1500 200 U 70 70 0 1 W +X TEST 42 -1100 -1200 200 R 70 70 0 1 P +X EEDATA 43 -1100 -500 200 R 70 70 0 1 P +X EECLK 44 -1100 -400 200 R 70 70 0 1 O +X EECS 45 -1100 -300 200 R 70 70 0 1 O +X VCCIO 46 200 1500 200 D 70 70 0 1 W +X GND 47 500 -1500 200 U 70 70 0 1 W +X GND 48 600 -1500 200 U 70 70 0 1 W +X REF 5 -1100 100 200 R 70 70 0 1 P +X DM 6 -1100 600 200 R 70 70 0 1 P +X DP 7 -1100 500 200 R 70 70 0 1 P +X VPLL 8 -100 1500 200 D 70 70 0 1 W +X AGND 9 -300 -1500 200 U 70 70 0 1 W +ENDDRAW +ENDDEF +# +# FT_MGMT_VCC3V3 +# +DEF FT_MGMT_VCC3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_MGMT_VCC3V3" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_MGMT_VCC3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_MGMT_VPHY +# +DEF FT_MGMT_VPHY #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_MGMT_VPHY" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_MGMT_VPHY 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_MGMT_VPLL +# +DEF FT_MGMT_VPLL #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_MGMT_VPLL" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_MGMT_VPLL 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_MGMT_VREGIN +# +DEF FT_MGMT_VREGIN #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_MGMT_VREGIN" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_MGMT_VREGIN 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_VCC3V3 +# +DEF FT_VCC3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_VCC3V3" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_VCC3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_VPHY +# +DEF FT_VPHY #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_VPHY" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_VPHY 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_VPLL +# +DEF FT_VPLL #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_VPLL" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_VPLL 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# FT_VREGIN +# +DEF FT_VREGIN #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "FT_VREGIN" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X FT_VREGIN 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# IS45S32160F +# +DEF IS45S32160F IC 0 40 Y Y 1 F N +F0 "U" 1220 2110 60 H V L BNN +F1 "IS45S32160F" -1360 2250 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -1100 -2200 -1100 2200 +P 2 0 1 10 -1100 2200 1100 2200 +P 2 0 1 10 1100 -2200 -1100 -2200 +P 2 0 1 10 1100 2200 1100 -2200 +X VDD 1 -600 2300 100 D 70 70 0 1 W +X DQ5 10 1200 1500 100 L 70 70 0 1 P +X DQ6 11 1200 1400 100 L 70 70 0 1 P +X VSSQ 12 -500 -2300 100 U 70 70 0 1 W +X DQ7 13 1200 1300 100 L 70 70 0 1 P +X VDD 15 -500 2300 100 D 70 70 0 1 W +X DQM0 16 1200 -1300 100 L 70 70 0 1 P +X ~WE 17 -1200 -1900 100 R 70 70 0 1 P +X ~CAS 18 -1200 200 100 R 70 70 0 1 P +X ~RAS 19 -1200 100 100 R 70 70 0 1 P +X DQ0 2 1200 2000 100 L 70 70 0 1 P +X ~CS 20 -1200 -1400 100 R 70 70 0 1 P +X A11 21 -1200 900 100 R 70 70 0 1 P +X BA0 22 -1200 500 100 R 70 70 0 1 P +X BA1 23 -1200 400 100 R 70 70 0 1 P +X A10 24 -1200 1000 100 R 70 70 0 1 P +X A0 25 -1200 2000 100 R 70 70 0 1 P +X A1 26 -1200 1900 100 R 70 70 0 1 P +X A2 27 -1200 1800 100 R 70 70 0 1 P +X DQM2 28 1200 -1500 100 L 70 70 0 1 P +X VDD 29 -400 2300 100 D 70 70 0 1 W +X VDDQ 3 -100 2300 100 D 70 70 0 1 W +X DQ16 31 1200 400 100 L 70 70 0 1 P +X VSSQ 32 -400 -2300 100 U 70 70 0 1 W +X DQ17 33 1200 300 100 L 70 70 0 1 P +X DQ18 34 1200 200 100 L 70 70 0 1 P +X VDDQ 35 0 2300 100 D 70 70 0 1 W +X DQ19 36 1200 100 100 L 70 70 0 1 P +X DQ20 37 1200 0 100 L 70 70 0 1 P +X VSSQ 38 -300 -2300 100 U 70 70 0 1 W +X DQ21 39 1200 -100 100 L 70 70 0 1 P +X DQ1 4 1200 1900 100 L 70 70 0 1 P +X DQ22 40 1200 -200 100 L 70 70 0 1 P +X VDDQ 41 100 2300 100 D 70 70 0 1 W +X DQ23 42 1200 -300 100 L 70 70 0 1 P +X VDD 43 -300 2300 100 D 70 70 0 1 W +X VSS 44 300 -2300 100 U 70 70 0 1 W +X DQ24 45 1200 -400 100 L 70 70 0 1 P +X VSSQ 46 -200 -2300 100 U 70 70 0 1 W +X DQ25 47 1200 -500 100 L 70 70 0 1 P +X DQ26 48 1200 -600 100 L 70 70 0 1 P +X VDDQ 49 200 2300 100 D 70 70 0 1 W +X DQ2 5 1200 1800 100 L 70 70 0 1 P +X DQ27 50 1200 -700 100 L 70 70 0 1 P +X DQ28 51 1200 -800 100 L 70 70 0 1 P +X VSSQ 52 -100 -2300 100 U 70 70 0 1 W +X DQ29 53 1200 -900 100 L 70 70 0 1 P +X DQ30 54 1200 -1000 100 L 70 70 0 1 P +X VDDQ 55 300 2300 100 D 70 70 0 1 W +X DQ31 56 1200 -1100 100 L 70 70 0 1 P +X VSS 58 400 -2300 100 U 70 70 0 1 W +X DQM3 59 1200 -1600 100 L 70 70 0 1 P +X VSSQ 6 -600 -2300 100 U 70 70 0 1 W +X A3 60 -1200 1700 100 R 70 70 0 1 P +X A4 61 -1200 1600 100 R 70 70 0 1 P +X A5 62 -1200 1500 100 R 70 70 0 1 P +X A6 63 -1200 1400 100 R 70 70 0 1 P +X A7 64 -1200 1300 100 R 70 70 0 1 P +X A8 65 -1200 1200 100 R 70 70 0 1 P +X A9 66 -1200 1100 100 R 70 70 0 1 P +X CKE 67 -1200 -900 100 R 70 70 0 1 P +X CLK 68 -1200 -400 100 R 70 70 0 1 P +X A12 69 -1200 800 100 R 70 70 0 1 P +X DQ3 7 1200 1700 100 L 70 70 0 1 P +X DQM1 71 1200 -1400 100 L 70 70 0 1 P +X VSS 72 500 -2300 100 U 70 70 0 1 W +X DQ8 74 1200 1200 100 L 70 70 0 1 P +X VDDQ 75 400 2300 100 D 70 70 0 1 W +X DQ9 76 1200 1100 100 L 70 70 0 1 P +X DQ10 77 1200 1000 100 L 70 70 0 1 P +X VSSQ 78 0 -2300 100 U 70 70 0 1 W +X DQ11 79 1200 900 100 L 70 70 0 1 P +X DQ4 8 1200 1600 100 L 70 70 0 1 P +X DQ12 80 1200 800 100 L 70 70 0 1 P +X VDDQ 81 500 2300 100 D 70 70 0 1 W +X DQ13 82 1200 700 100 L 70 70 0 1 P +X DQ14 83 1200 600 100 L 70 70 0 1 P +X VSSQ 84 100 -2300 100 U 70 70 0 1 W +X DQ15 85 1200 500 100 L 70 70 0 1 P +X VSS 86 600 -2300 100 U 70 70 0 1 W +ENDDRAW +ENDDEF +# +# JP1Q +# +DEF JP1Q IC 0 40 Y Y 1 F N +F0 "JP" -230 -210 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -80 -200 70 -200 +P 2 0 1 10 -80 200 -80 -200 +P 2 0 1 10 0 -200 0 -150 +P 2 0 1 10 0 -150 0 -100 +P 2 0 1 10 0 150 0 100 +P 2 0 1 10 0 200 0 150 +P 2 0 1 10 70 -200 70 200 +P 2 0 1 10 70 200 -80 200 +X 1 1 0 -300 100 U 70 1 0 1 P +X 2 2 0 300 100 D 70 1 0 1 P +ENDDRAW +ENDDEF +# +# LEDCHIP-LED0603 +# +DEF LEDCHIP-LED0603 IC 0 40 Y Y 1 F N +F0 "LED" 630 -30 60 H V L BNN +F1 "LEDCHIP-LED0603" 1240 -40 60 V V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -140 -80 -80 -30 +P 2 0 1 10 -130 -130 -80 -70 +P 2 0 1 10 -50 -100 0 -100 +P 2 0 1 10 -50 0 0 -100 +P 2 0 1 10 -50 0 0 0 +P 2 0 1 10 0 -100 0 0 +P 2 0 1 10 0 -100 50 -100 +P 2 0 1 10 0 -100 50 0 +P 2 0 1 10 0 0 50 0 +P 4 0 1 10 -140 -80 -120 -50 -100 -70 -140 -80 F +P 4 0 1 10 -130 -130 -120 -90 -100 -110 -130 -130 F +X A 1 0 100 100 D 1 1 0 1 P +X C 2 0 -200 100 U 1 1 0 1 P +ENDDRAW +ENDDEF +# +# LMZ13608 +# +DEF LMZ13608 IC 0 40 Y Y 1 F N +F0 "U" -710 910 60 H V L BNN +F1 "LMZ13608" -500 900 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -700 -900 700 -900 +P 2 0 1 10 -700 900 -700 -900 +P 2 0 1 10 700 -900 700 900 +P 2 0 1 10 700 900 -700 900 +X VIN 1 -900 700 200 R 70 70 0 1 W +X VOUT 10 900 700 200 L 70 70 0 1 w +X VOUT 11 900 600 200 L 70 70 0 1 W +X VIN 2 -900 600 200 R 70 70 0 1 W +X AGND 3 100 -1100 200 U 70 70 0 1 W +X EN 4 -900 100 200 R 70 70 0 1 P +X AGND 5 200 -1100 200 U 70 70 0 1 W +X AGND 6 300 -1100 200 U 70 70 0 1 W +X FB 7 900 -100 200 L 70 70 0 1 P +X SS/TRK 8 -900 -700 200 R 70 70 0 1 P +X NC 9 900 -700 200 L 70 70 0 1 P +X PGND TP1 -100 -1100 200 U 70 70 0 1 W +ENDDRAW +ENDDEF +# +# LT3060ITS8-15 +# +DEF LT3060ITS8-15 IC 0 40 Y Y 1 F N +F0 "U" -410 410 60 H V L BNN +F1 "LT3060ITS8-15" -410 -710 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -600 -400 400 +P 2 0 1 10 400 -600 -400 -600 +P 2 0 1 10 400 -600 400 400 +P 2 0 1 10 400 400 -400 400 +X ~SHDN 1 -600 0 200 R 70 70 0 1 P +X GND 2 -600 -300 200 R 70 70 0 1 W +X GND 3 -600 -400 200 R 70 70 0 1 W +X GND 4 -600 -500 200 R 70 70 0 1 W +X IN 5 -600 300 200 R 70 70 0 1 W +X OUT 6 600 300 200 L 70 70 0 1 w +X ADJ 7 600 0 200 L 70 70 0 1 P +X REF/BYP 8 600 -300 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# M03LOCK +# +DEF M03LOCK IC 0 40 Y Y 1 F N +F0 "JP" -180 -330 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -100 -200 -100 200 +P 2 0 1 10 -100 -200 150 -200 +P 2 0 1 10 100 -100 50 -100 +P 2 0 1 10 100 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450 -300 0 1 10 f +S 440 -300 450 -300 0 1 10 f +S 440 -280 450 -280 0 1 10 f +P 34 0 1 20 60 -150 80 -140 130 -180 170 -140 130 -90 150 -40 220 -30 220 20 150 30 130 80 170 130 130 170 80 130 30 150 20 220 -30 220 -40 150 -90 130 -140 170 -180 130 -140 80 -160 30 -230 20 -230 -30 -160 -40 -140 -90 -180 -140 -140 -180 -90 -140 -60 -150 -30 -70 -80 0 20 -70 60 -150 F +ENDDRAW +ENDDEF +# +# POWER_JACKSMD +# +DEF POWER_JACKSMD IC 0 40 Y Y 1 F N +F0 "JP" -410 330 60 H V L BNN +F1 "POWER_JACKSMD" -410 -30 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 270 0 330 0 1 10 f +P 2 0 1 10 -300 200 -400 100 +P 2 0 1 10 -200 100 -300 200 +P 2 0 1 10 -100 100 -200 100 +P 2 0 1 10 -100 200 -100 100 +P 2 0 1 10 0 100 -100 100 +P 2 0 1 10 0 200 -100 200 +X PWR 1 100 300 100 L 1 1 0 1 W +X GND 2 100 100 100 L 1 1 0 1 W +X GNDBREAK 3 100 200 100 L 1 1 0 1 W +ENDDRAW +ENDDEF +# +# PWR_18V +# +DEF PWR_18V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "PWR_18V" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X PWR_18V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# R-EU_R0402 +# +DEF R-EU_R0402 IC 0 40 Y Y 1 F N +F0 "R" -150 50 60 H V L BNN +F1 "R-EU_R0402" 150 -150 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -100 30 -100 -40 +P 2 0 1 10 -100 30 100 30 +P 2 0 1 10 -100 40 -100 -30 +P 2 0 1 10 -100 40 100 40 +P 2 0 1 10 100 -40 -100 -40 +P 2 0 1 10 100 -30 -100 -30 +P 2 0 1 10 100 30 100 -40 +P 2 0 1 10 100 40 100 -30 +X 1 1 -200 0 100 R 1 1 0 1 P +X 2 2 200 0 100 L 1 1 0 1 P +ENDDRAW +ENDDEF +# +# R-EU_R0603 +# +DEF R-EU_R0603 IC 0 40 Y Y 1 F N +F0 "R" -110 370 60 H V L BNN +F1 "R-EU_R0603" 70 370 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -100 40 -100 -30 +P 2 0 1 10 -100 40 100 40 +P 2 0 1 10 100 -30 -100 -30 +P 2 0 1 10 100 40 100 -30 +X 1 1 -200 0 100 R 1 1 0 1 P +X 2 2 200 0 100 L 1 1 0 1 P +ENDDRAW +ENDDEF +# +# RCLAMP0502ASC-89 +# +DEF RCLAMP0502ASC-89 IC 0 40 Y Y 1 F N +F0 "IC" -410 -310 60 H V L BNN +F1 "RCLAMP0502ASC-89" -400 -330 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -200 400 -200 +P 2 0 1 10 -400 200 -400 -200 +P 2 0 1 10 400 -200 400 200 +P 2 0 1 10 400 200 -400 200 +X OUT1 1 500 100 100 L 70 70 0 1 O +X GND 2 500 0 100 L 70 70 0 1 W +X OUT2 3 500 -100 100 L 70 70 0 1 O +X IN2 4 -500 -100 100 R 70 70 0 1 P +X VCC 5 -500 0 100 R 70 70 0 1 W +X IN1 6 -500 100 100 R 70 70 0 1 P +ENDDRAW +ENDDEF +# +# STM32-SWD +# +DEF STM32-SWD IC 0 40 Y Y 1 F N +F0 "J" -150 430 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -300 -400 200 -400 +P 2 0 1 10 -300 300 -300 -400 +P 2 0 1 10 200 -400 200 300 +P 2 0 1 10 200 300 -300 300 +X VCC 1 400 -300 200 L 70 70 0 1 W +X SWDCLK 2 400 -200 200 L 70 70 0 1 P +X GND 3 400 -100 200 L 70 70 0 1 W +X SWDIO 4 400 0 200 L 70 70 0 1 P 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PK2 128 1500 -1900 100 L 70 70 0 1 P +X PI11 13 1500 800 100 L 70 70 0 1 P +X FMC_INT2/PG6 133 1500 2200 100 L 70 70 0 1 P +X FMC_INT3/PG7 134 1500 2100 100 L 70 70 0 1 P +X PC6 138 -1600 -2400 100 R 70 70 0 1 P +X PC7 139 -1600 -2500 100 R 70 70 0 1 P +X SDIO_D0/PC8 140 -1600 100 100 R 70 70 0 1 P +X SDIO_D1/PC9 141 -1600 0 100 R 70 70 0 1 P +X PA8 142 -1600 2200 100 R 70 70 0 1 P +X USART1_TX/PA9 143 -1600 2100 100 R 70 70 0 1 P +X USART1_RX/PA10 144 -1600 2000 100 R 70 70 0 1 P +X USART1_CTS/PA11 145 -1600 1800 100 R 70 70 0 1 P +X USART1_RTS/PA12 146 -1600 1900 100 R 70 70 0 1 P +X SDIO_D2/PC10 161 -1600 -100 100 R 70 70 0 1 P +X SDIO_D3/PC11 162 -1600 -200 100 R 70 70 0 1 P +X SDIO_CK/PC12 163 -1600 200 100 R 70 70 0 1 P +X SDIO_CMD/PD2 166 -1600 300 100 R 70 70 0 1 P +X PJ12 174 1500 -1100 100 L 70 70 0 1 P +X PJ13 175 1500 -1200 100 L 70 70 0 1 P +X PJ14 176 1500 -1300 100 L 70 70 0 1 P +X PJ15 177 1500 -1400 100 L 70 70 0 1 P +X FMC_NE2/FMC_NCE3/PG9 178 1500 2000 100 L 70 70 0 1 P +X FMC_NCE4_1/FMC_NE3/PG10 179 1500 1900 100 L 70 70 0 1 P +X FMC_NCE4_2/PG11 180 1500 1800 100 L 70 70 0 1 P +X FMC_NE4/PG12 181 1500 1700 100 L 70 70 0 1 P +X PK3 186 1500 -2000 100 L 70 70 0 1 P +X PK4 187 1500 -2100 100 L 70 70 0 1 P +X PK5 188 1500 -2200 100 L 70 70 0 1 P +X PK6 189 1500 -2300 100 L 70 70 0 1 P +X PI12 19 1500 700 100 L 70 70 0 1 P +X PK7 190 1500 -2400 100 L 70 70 0 1 P +X PB8/I2C1_SCL 198 -1600 -1400 100 R 70 70 0 1 P +X PB9/I2C1_SDA 199 -1600 -1500 100 R 70 70 0 1 P +X PI13 20 1500 600 100 L 70 70 0 1 P +X PI14 21 1500 500 100 L 70 70 0 1 P +X FMC_NIORD/PF6 27 1500 2900 100 L 70 70 0 1 P +X FMC_NREG/PF7 28 1500 2800 100 L 70 70 0 1 P +X FMC_NIOWR/PF8 29 1500 2700 100 L 70 70 0 1 P +X FMC_CD/PF9 30 1500 2600 100 L 70 70 0 1 P +X FMC_INTR/PF10 31 1500 2500 100 L 70 70 0 1 P +X PC1 36 -1600 -2100 100 R 70 70 0 1 P +X USART2_CTS/WKUP/PA0 43 -1600 2500 100 R 70 70 0 1 P +X USART2_RTS/PA1 44 -1600 2600 100 R 70 70 0 1 P +X USART2_TX/PA2 45 -1600 2800 100 R 70 70 0 1 P +X FMC_SDCKE0/PH2 46 1500 1400 100 L 70 70 0 1 P +X PH3 47 -1600 -700 100 R 70 70 0 1 P +X I2C2_SCL/PH4 48 -1600 -600 100 R 70 70 0 1 P +X I2C2_SDA/PH5 49 -1600 -500 100 R 70 70 0 1 P +X USART2_RX/PA3 50 -1600 2700 100 R 70 70 0 1 P +X PA4 53 -1600 2900 100 R 70 70 0 1 P +X SPI1_SCK/PA5 54 -1600 800 100 R 70 70 0 1 P +X SPI1_MISO/PA6 55 -1600 700 100 R 70 70 0 1 P +X SPI1_MOSI/PA7 56 -1600 600 100 R 70 70 0 1 P +X PC4 57 -1600 -2200 100 R 70 70 0 1 P +X PC5 58 -1600 -2300 100 R 70 70 0 1 P +X PB0 61 -1600 900 100 R 70 70 0 1 P +X PB1 62 -1600 -1300 100 R 70 70 0 1 P +X PI15 64 1500 400 100 L 70 70 0 1 P +X PJ0 65 1500 100 100 L 70 70 0 1 P +X PJ1 66 1500 0 100 L 70 70 0 1 P +X PJ2 67 1500 -100 100 L 70 70 0 1 P +X PJ3 68 1500 -200 100 L 70 70 0 1 P +X PJ4 69 1500 -300 100 L 70 70 0 1 P +X PI8 7 1500 900 100 L 70 70 0 1 P +X PC13 8 -1600 -2600 100 R 70 70 0 1 P +X PC14 9 -1600 -2700 100 R 70 70 0 1 P +X PB10 90 -1600 -1600 100 R 70 70 0 1 P +X PB11 91 -1600 -1700 100 R 70 70 0 1 P +X PJ5 95 1500 -400 100 L 70 70 0 1 P +X FMC_SDNE1/PH6 96 1500 1300 100 L 70 70 0 1 P +X FMC_SDCKE1/PH7 97 1500 1200 100 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# STM32F429BIT6_2 +# +DEF STM32F429BIT6_2 IC 0 40 Y Y 1 F N +F0 "U" -1110 -1010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -1100 -900 -1100 800 +P 2 0 1 10 1000 -900 -1100 -900 +P 2 0 1 10 1000 -900 1000 800 +P 2 0 1 10 1000 800 -1100 800 +X PA13/JTMS-SWDIO 147 1100 100 100 L 70 70 0 1 P +X PA14/JTCK-SWCLK 159 1100 200 100 L 70 70 0 1 P +X PA15/JTDI 160 1100 -200 100 L 70 70 0 1 P +X PB3/JTDO/TRACESWO 192 1100 -400 100 L 70 70 0 1 P +X PB4/NJTRST 193 1100 -300 100 L 70 70 0 1 P +X BOOT0 197 -1200 -700 100 R 70 70 0 1 P +X PDR_ON 203 -1200 400 100 R 70 70 0 1 P +X OSC_IN/PH0 32 -1200 0 100 R 70 70 0 1 P +X OSC_OUT/PH1 33 -1200 -100 100 R 70 70 0 1 P +X NRST 34 1100 300 100 L 70 70 0 1 P +X VREF+ 41 -1200 600 100 R 70 70 0 1 W +X PB2/BOOT1 63 -1200 -500 100 R 70 70 0 1 P +ENDDRAW +ENDDEF +# +# STM32F429BIT6_3 +# +DEF STM32F429BIT6_3 IC 0 40 Y Y 1 F N +F0 "U" -710 -1610 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -700 1500 -700 -1400 +P 2 0 1 10 700 -1400 -700 -1400 +P 2 0 1 10 700 -1400 700 1500 +P 2 0 1 10 700 1500 -700 1500 +X VDD 103 -800 -100 100 R 70 70 0 1 W +X VSS 114 800 -300 100 L 70 70 0 1 W +X VDD 115 -800 -300 100 R 70 70 0 1 W +X VDD 124 -800 -400 100 R 70 70 0 1 W +X VSS 125 800 -400 100 L 70 70 0 1 W +X VSS 136 800 -500 100 L 70 70 0 1 W +X VDD 137 -800 -500 100 R 70 70 0 1 W +X VSS 14 800 700 100 L 70 70 0 1 W +X VCAP2 148 100 1600 100 D 70 70 0 1 P +X VSS 149 800 -600 100 L 70 70 0 1 W +X VDD 15 -800 800 100 R 70 70 0 1 W +X VDD 150 -800 -600 100 R 70 70 0 1 W +X VDD 158 -800 -1100 100 R 70 70 0 1 W +X VSS 170 800 -800 100 L 70 70 0 1 W +X VDD 171 -800 -1000 100 R 70 70 0 1 W +X VSS 184 800 -900 100 L 70 70 0 1 W +X VDD 185 -800 -900 100 R 70 70 0 1 W +X VSS 202 800 -1000 100 L 70 70 0 1 W +X VDD 204 -800 -800 100 R 70 70 0 1 W +X VSS 25 800 600 100 L 70 70 0 1 W +X VDD 26 -800 700 100 R 70 70 0 1 W +X VDD 39 -800 600 100 R 70 70 0 1 W +X VSSA 40 800 1000 100 L 70 70 0 1 W +X VDDA 42 -800 1000 100 R 70 70 0 1 W +X VSS 51 800 500 100 L 70 70 0 1 W +X VDD 52 -800 500 100 R 70 70 0 1 W +X VDD 59 -800 300 100 R 70 70 0 1 W +X VBAT 6 -800 1200 100 R 70 70 0 1 W +X VSS 60 800 300 100 L 70 70 0 1 W +X VSS 72 800 200 100 L 70 70 0 1 W +X VDD 73 -800 200 100 R 70 70 0 1 W +X VSS 82 800 100 100 L 70 70 0 1 W +X VDD 83 -800 100 100 R 70 70 0 1 W +X VCAP1 92 -100 1600 100 D 70 70 0 1 P +X VSS 93 800 0 100 L 70 70 0 1 W +X VDD 94 -800 0 100 R 70 70 0 1 W +ENDDRAW +ENDDEF +# +# STM32F429BIT6_4 +# +DEF STM32F429BIT6_4 IC 0 40 Y Y 1 F N +F0 "U" -1210 -2810 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -1200 2400 -1200 -2700 +P 2 0 1 10 -1200 2400 1000 2400 +P 2 0 1 10 1000 -2700 -1200 -2700 +P 2 0 1 10 1000 2400 1000 -2700 +X FMC_A23/PE2 1 -1300 -200 100 R 70 70 0 1 P +X PH10/FMC_D18 100 1100 300 100 L 70 70 0 1 P +X PH11/FMC_D19 101 1100 200 100 L 70 70 0 1 P +X PH12/FMC_D20 102 1100 100 100 L 70 70 0 1 P +X PD8/FMC_D13 108 1100 800 100 L 70 70 0 1 P +X PD9/FMC_D14 109 1100 700 100 L 70 70 0 1 P +X PI9/FMC_D30 11 1100 -900 100 L 70 70 0 1 P +X PD10/FMC_D15 110 1100 600 100 L 70 70 0 1 P +X FMC_A16/PD11 111 -1300 500 100 R 70 70 0 1 P +X FMC_A17/PD12 112 -1300 400 100 R 70 70 0 1 P +X FMC_A18/PD13 113 -1300 300 100 R 70 70 0 1 P +X PD14/FMC_D0 116 1100 2100 100 L 70 70 0 1 P +X PD15/FMC_D1 117 1100 2000 100 L 70 70 0 1 P +X PI10/FMC_D31 12 1100 -1000 100 L 70 70 0 1 P +X FMC_A12/PG2 129 -1300 900 100 R 70 70 0 1 P +X FMC_A13/PG3 130 -1300 800 100 R 70 70 0 1 P +X FMC_A14/PG4 131 -1300 700 100 R 70 70 0 1 P +X FMC_A15/PG5 132 -1300 600 100 R 70 70 0 1 P +X PG8/FMC_SDCLK 135 1100 -1300 100 L 70 70 0 1 P +X PH13/FMC_D21 151 1100 0 100 L 70 70 0 1 P +X PH14/FMC_D22 152 1100 -100 100 L 70 70 0 1 P +X PH15/FMC_D23 153 1100 -200 100 L 70 70 0 1 P +X PI0/FMC_D24 154 1100 -300 100 L 70 70 0 1 P +X PI1/FMC_D25 155 1100 -400 100 L 70 70 0 1 P +X PI2/FMC_D26 156 1100 -500 100 L 70 70 0 1 P +X PI3/FMC_D27 157 1100 -600 100 L 70 70 0 1 P +X FMC_A0/PF0 16 -1300 2100 100 R 70 70 0 1 P +X PD0/FMC_D2 164 1100 1900 100 L 70 70 0 1 P +X PD1/FMC_D3 165 1100 1800 100 L 70 70 0 1 P +X FMC_CLK/PD3 167 -1300 -1600 100 R 70 70 0 1 P +X FMC_NOE/PD4 168 -1300 -1700 100 R 70 70 0 1 P +X FMC_NWE/PD5 169 -1300 -1800 100 R 70 70 0 1 P +X FMC_A1/PF1 17 -1300 2000 100 R 70 70 0 1 P +X FMC_NWAIT/PD6 172 -1300 -1900 100 R 70 70 0 1 P +X FMC_NE1/PD7 173 -1300 -2000 100 R 70 70 0 1 P +X FMC_A2/PF2 18 -1300 1900 100 R 70 70 0 1 P +X FMC_A24/PG13 182 -1300 -300 100 R 70 70 0 1 P +X FMC_A25/PG14 183 -1300 -400 100 R 70 70 0 1 P +X PG15/FMC_SDNCAS 191 1100 -2200 100 L 70 70 0 1 P +X PB5/FMC_SDCKE1 194 1100 -2000 100 L 70 70 0 1 P +X PB6/FMC_SDNE1 195 1100 -1700 100 L 70 70 0 1 P +X FMC_NL/PB7 196 -1300 -1300 100 R 70 70 0 1 P +X FMC_A19/PE3 2 -1300 200 100 R 70 70 0 1 P +X FMC_NBL0/PE0 200 -1300 -700 100 R 70 70 0 1 P +X FMC_NBL1/PE1 201 -1300 -800 100 R 70 70 0 1 P +X FMC_NBL2/PI4 205 -1300 -900 100 R 70 70 0 1 P +X FMC_NBL3/PI5 206 -1300 -1000 100 R 70 70 0 1 P +X PI6/FMC_D28 207 1100 -700 100 L 70 70 0 1 P +X PI7/FMC_D29 208 1100 -800 100 L 70 70 0 1 P +X FMC_A3/PF3 22 -1300 1800 100 R 70 70 0 1 P +X FMC_A4/PF4 23 -1300 1700 100 R 70 70 0 1 P +X FMC_A5/PF5 24 -1300 1600 100 R 70 70 0 1 P +X FMC_A20/PE4 3 -1300 100 100 R 70 70 0 1 P +X PC0/FMC_SDNWE 35 1100 -1400 100 L 70 70 0 1 P +X PC2/FMC_SDNE0 37 1100 -1600 100 L 70 70 0 1 P +X PC3/FMC_SDCKE0 38 1100 -1900 100 L 70 70 0 1 P +X FMC_A21/PE5 4 -1300 0 100 R 70 70 0 1 P +X FMC_A22/PE6 5 -1300 -100 100 R 70 70 0 1 P +X PF11/FMC_SDNRAS 70 1100 -2300 100 L 70 70 0 1 P +X FMC_A6/PF12 71 -1300 1500 100 R 70 70 0 1 P +X FMC_A7/PF13 74 -1300 1400 100 R 70 70 0 1 P +X FMC_A8/PF14 75 -1300 1300 100 R 70 70 0 1 P +X FMC_A9/PF15 76 -1300 1200 100 R 70 70 0 1 P +X FMC_A10/PG0 77 -1300 1100 100 R 70 70 0 1 P +X FMC_A11/PG1 78 -1300 1000 100 R 70 70 0 1 P +X PE7/FMC_D4 79 1100 1700 100 L 70 70 0 1 P +X PE8/FMC_D5 80 1100 1600 100 L 70 70 0 1 P +X PE9/FMC_D6 81 1100 1500 100 L 70 70 0 1 P +X PE10/FMC_D7 84 1100 1400 100 L 70 70 0 1 P +X PE11/FMC_D8 85 1100 1300 100 L 70 70 0 1 P +X PE12/FMC_D9 86 1100 1200 100 L 70 70 0 1 P +X PE13/FMC_D10 87 1100 1100 100 L 70 70 0 1 P +X PE14/FMC_D11 88 1100 1000 100 L 70 70 0 1 P +X PE15/FMC_D12 89 1100 900 100 L 70 70 0 1 P +X PH8/FMC_D16 98 1100 500 100 L 70 70 0 1 P +X PH9/FMC_D17 99 1100 400 100 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# TACTILE_SWITCH +# +DEF TACTILE_SWITCH IC 0 40 Y Y 1 F N +F0 "S" 620 110 60 H V L BNN +F1 "TACTILE_SWITCH" -300 470 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -200 0 25 0 1200 1 1 10 N -175 0 -212 21 +A -200 0 25 1200 -1200 1 1 10 N -212 21 -212 -21 +A -200 0 25 -1200 0 1 1 10 N -212 -21 -175 0 +A 100 0 25 0 1200 1 1 10 N 125 0 87 21 +A 100 0 25 1200 -1200 1 1 10 N 87 21 87 -21 +A 100 0 25 -1200 0 1 1 10 N 87 -21 125 0 +P 2 0 1 10 -400 -200 400 -200 +P 2 0 1 10 -400 200 -400 -200 +P 2 0 1 10 -300 -200 -300 0 +P 2 0 1 10 -300 0 -300 200 +P 2 0 1 10 -200 0 -300 0 +P 2 0 1 10 0 100 -200 0 +P 2 0 1 10 300 -200 300 0 +P 2 0 1 10 300 0 100 0 +P 2 0 1 10 300 0 300 200 +P 2 0 1 10 400 -200 400 200 +P 2 0 1 10 400 200 -400 200 +X A1 A1 -300 400 200 D 70 1 0 1 P +X A2 A2 -300 -400 200 U 70 1 0 1 P +X B1 B1 300 400 200 D 70 1 0 1 P +X B2 B2 300 -400 200 U 70 1 0 1 P +X G1 G1 600 100 200 L 70 1 0 1 W +X G2 G2 600 -100 200 L 70 1 0 1 W +ENDDRAW +ENDDEF +# +# TPB1,27 +# +DEF TPB1,27 IC 0 40 Y Y 1 F N +F0 "TP" -100 -300 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -30 -30 0 -60 +P 2 0 1 10 0 -60 30 -30 +P 2 0 1 10 0 0 -30 -30 +P 2 0 1 10 30 -30 0 0 +X TP TP 0 -100 100 U 1 1 0 1 P +ENDDRAW +ENDDEF +# +# USBMINIB +# +DEF USBMINIB IC 0 40 Y Y 1 F N +F0 "CN" -420 -410 60 H V L BNN +F1 "USBMINIB" -420 310 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -240 120 8 0 1200 1 1 30 N -232 120 -244 126 +A -240 120 8 1200 -1200 1 1 30 N -244 126 -244 113 +A -240 120 8 -1200 0 1 1 30 N -244 113 -232 120 +A -60 60 20 0 1200 1 1 30 N -40 60 -70 77 +A -60 60 20 1200 -1200 1 1 30 N -70 77 -70 42 +A -60 60 20 -1200 0 1 1 30 N -70 42 -40 60 +S -290 -20 -240 30 0 1 10 f +P 2 0 1 10 -400 -300 -400 300 +P 2 0 1 10 -400 300 -410 300 +P 2 0 1 10 -360 60 -320 30 +P 2 0 1 10 -350 60 -330 70 +P 2 0 1 10 -340 50 -340 60 +P 2 0 1 10 -330 40 -340 50 +P 2 0 1 10 -330 70 -330 40 +P 2 0 1 10 -320 30 -320 30 +P 2 0 1 10 -320 30 -320 60 +P 2 0 1 10 -320 60 -320 90 +P 2 0 1 10 -320 60 -170 60 +P 2 0 1 10 -320 90 -360 60 +P 2 0 1 10 -320 90 -320 40 +P 2 0 1 10 -320 90 -320 90 +P 2 0 1 10 -200 0 -250 0 +P 2 0 1 10 -180 120 -220 120 +P 2 0 1 10 -170 60 -200 0 +P 2 0 1 10 -170 60 -140 60 +P 2 0 1 10 -140 60 -180 120 +P 2 0 1 10 -140 60 -60 60 +P 2 0 1 10 300 -300 -400 -300 +P 2 0 1 10 300 -300 300 300 +P 2 0 1 10 300 300 -400 300 +X D+ D+ 400 100 100 L 1 70 0 1 P +X D- D- 400 0 100 L 1 70 0 1 P +X GND GND 400 -200 100 L 1 70 0 1 W +X ID ID 400 -100 100 L 1 70 0 1 P +X VBUS VBUS 400 200 100 L 1 70 0 1 w +ENDDRAW +ENDDEF +# +# VCCO_3V3 +# +DEF VCCO_3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VCCO_3V3" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X VCCO_3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VCC_5V0 +# +DEF VCC_5V0 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VCC_5V0" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X VCC_5V0 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# WE-SHC +# +DEF WE-SHC IC 0 40 Y Y 1 F N +F0 "S" -300 450 60 H V L BNN +F1 "WE-SHC" 0 400 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -300 -500 -300 300 +P 2 0 1 10 -300 300 500 300 +X GND 1 -400 100 100 R 70 70 0 1 W +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_1 +# +DEF XC7A200TFBG484_1 IC 0 40 Y Y 1 F N +F0 "U" -410 -910 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 -410 810 50 0 1 1 122-1871-ND Normal 1 C C +T 0 -410 810 50 0 1 1 XC7A200T-1FBG484C Normal 1 C C +T 0 -410 810 50 0 1 1 Xilinx Normal 1 C C +P 2 0 1 10 -400 -800 0 -800 +P 2 0 1 10 0 -800 0 800 +P 2 0 1 10 0 800 -400 800 +X VCCBATT_0 E12 200 700 200 L 70 70 0 1 P +X VCCO_0 F12 200 600 200 L 70 70 0 1 P +X DONE_0 G11 200 300 200 L 70 70 0 1 P +X CCLK_0 L12 200 0 200 L 70 70 0 1 P +X PROGRAM_B_0 N12 200 100 200 L 70 70 0 1 P +X TDI_0 R13 200 -500 200 L 70 70 0 1 P +X VCCO_0 T12 200 500 200 L 70 70 0 1 P +X TMS_0 T13 200 -700 200 L 70 70 0 1 P +X M1_0 U10 200 -200 200 L 70 70 0 1 P +X M0_0 U11 200 -100 200 L 70 70 0 1 P +X INIT_B_0 U12 200 200 200 L 70 70 0 1 C +X TDO_0 U13 200 -600 200 L 70 70 0 1 O +X CFGBVS_0 U8 200 400 200 L 70 70 0 1 P +X M2_0 U9 200 -300 200 L 70 70 0 1 P +X TCK_0 V12 200 -400 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_10 +# +DEF XC7A200TFBG484_10 IC 0 40 Y Y 1 F N +F0 "U" -410 -2310 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2200 0 -2200 +P 2 0 1 10 0 -2200 0 2200 +P 2 0 1 10 0 2200 -400 2200 +X GND AA12 200 -1800 200 L 70 70 0 1 W +X GND AA2 200 -1700 200 L 70 70 0 1 W +X GND AA22 200 -1900 200 L 70 70 0 1 W +X GND AB19 200 -2100 200 L 70 70 0 1 W +X GND AB9 200 -2000 200 L 70 70 0 1 W +X GND J10 200 2100 200 L 70 70 0 1 W +X GND J12 200 2000 200 L 70 70 0 1 W +X GND J18 200 1900 200 L 70 70 0 1 W +X GND K11 200 1600 200 L 70 70 0 1 W +X GND K15 200 1500 200 L 70 70 0 1 W +X GND K5 200 1800 200 L 70 70 0 1 W +X GND K7 200 1700 200 L 70 70 0 1 W +X GND L2 200 1400 200 L 70 70 0 1 W +X GND L22 200 1200 200 L 70 70 0 1 W +X GND L8 200 1300 200 L 70 70 0 1 W +X GND M11 200 1000 200 L 70 70 0 1 W +X GND M19 200 900 200 L 70 70 0 1 W +X GND M7 200 1100 200 L 70 70 0 1 W +X GND N16 200 600 200 L 70 70 0 1 W +X GND N6 200 800 200 L 70 70 0 1 W +X GND N8 200 700 200 L 70 70 0 1 W +X GND P11 200 200 200 L 70 70 0 1 W +X GND P13 200 100 200 L 70 70 0 1 W +X GND P3 200 500 200 L 70 70 0 1 W +X GND P7 200 400 200 L 70 70 0 1 W +X GND P9 200 300 200 L 70 70 0 1 W +X GND R10 200 -100 200 L 70 70 0 1 W +X GND R12 200 -200 200 L 70 70 0 1 W +X GND R20 200 -300 200 L 70 70 0 1 W +X GND R8 200 0 200 L 70 70 0 1 W +X GND T11 200 -600 200 L 70 70 0 1 W +X GND T17 200 -700 200 L 70 70 0 1 W +X GND T7 200 -400 200 L 70 70 0 1 W +X GND T9 200 -500 200 L 70 70 0 1 W +X GND U14 200 -900 200 L 70 70 0 1 W +X GND U4 200 -800 200 L 70 70 0 1 W +X GND V1 200 -1000 200 L 70 70 0 1 W +X GND V11 200 -1100 200 L 70 70 0 1 W +X GND V21 200 -1200 200 L 70 70 0 1 W +X GND W18 200 -1400 200 L 70 70 0 1 W +X GND W8 200 -1300 200 L 70 70 0 1 W +X GND Y15 200 -1600 200 L 70 70 0 1 W +X GND Y5 200 -1500 200 L 70 70 0 1 W +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_11 +# +DEF XC7A200TFBG484_11 IC 0 40 Y Y 1 F N +F0 "U" -410 -410 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -300 0 -300 +P 2 0 1 10 0 -300 0 300 +P 2 0 1 10 0 300 -400 300 +X MGTAVCC D10 200 100 200 L 70 70 0 1 P +X MGTAVCC D6 200 200 200 L 70 70 0 1 P +X MGTAVCC E8 200 0 200 L 70 70 0 1 P +X MGTAVCC F7 200 -100 200 L 70 70 0 1 P +X MGTAVCC F9 200 -200 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_12 +# +DEF XC7A200TFBG484_12 IC 0 40 Y Y 1 F N +F0 "U" -410 -510 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -400 0 -400 +P 2 0 1 10 0 -400 0 300 +P 2 0 1 10 0 300 -400 300 +X MGTAVTT B11 200 -100 200 L 70 70 0 1 P +X MGTAVTT B5 200 200 200 L 70 70 0 1 P +X MGTAVTT B7 200 100 200 L 70 70 0 1 P +X MGTAVTT B9 200 0 200 L 70 70 0 1 P +X MGTAVTT C4 200 -200 200 L 70 70 0 1 P +X MGTAVTT C8 200 -300 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_13 +# +DEF XC7A200TFBG484_13 IC 0 40 Y Y 1 F N +F0 "U" -410 -310 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -200 0 -200 +P 2 0 1 10 0 -200 0 100 +P 2 0 1 10 0 100 -400 100 +X DXP_0 N10 200 0 200 L 70 70 0 1 P +X DXN_0 N9 200 -100 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_14 +# +DEF XC7A200TFBG484_14 IC 0 40 Y Y 1 F N +F0 "U" -410 -410 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -300 0 -300 +P 2 0 1 10 0 -300 0 300 +P 2 0 1 10 0 300 -400 300 +X VCCAUX H12 200 200 200 L 70 70 0 1 P +X VCCAUX K12 200 100 200 L 70 70 0 1 P +X VCCAUX M12 200 0 200 L 70 70 0 1 P +X VCCAUX P12 200 -100 200 L 70 70 0 1 P +X VCCAUX R11 200 -200 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_15 +# +DEF XC7A200TFBG484_15 IC 0 40 Y Y 1 F N +F0 "U" -410 -310 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -200 0 -200 +P 2 0 1 10 0 -200 0 200 +P 2 0 1 10 0 200 -400 200 +X VCCBRAM J11 200 100 200 L 70 70 0 1 P +X VCCBRAM L11 200 0 200 L 70 70 0 1 P +X VCCBRAM N11 200 -100 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_16 +# +DEF XC7A200TFBG484_16 IC 0 40 Y Y 1 F N +F0 "U" -410 -810 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -800 0 -800 +P 2 0 1 10 0 -800 0 700 +P 2 0 1 10 0 700 -400 700 +X VCCINT H10 200 500 200 L 70 70 0 1 P +X VCCINT H8 200 600 200 L 70 70 0 1 P +X VCCINT J7 200 400 200 L 70 70 0 1 P +X VCCINT J9 200 300 200 L 70 70 0 1 P +X VCCINT K8 200 200 200 L 70 70 0 1 P +X VCCINT L7 200 100 200 L 70 70 0 1 P +X VCCINT M8 200 0 200 L 70 70 0 1 P +X VCCINT N7 200 -100 200 L 70 70 0 1 P +X VCCINT P10 200 -300 200 L 70 70 0 1 P +X VCCINT P8 200 -200 200 L 70 70 0 1 P +X VCCINT R7 200 -400 200 L 70 70 0 1 P +X VCCINT R9 200 -500 200 L 70 70 0 1 P +X VCCINT T10 200 -700 200 L 70 70 0 1 P +X VCCINT T8 200 -600 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_17 +# +DEF XC7A200TFBG484_17 IC 0 40 Y Y 1 F N +F0 "U" -410 -510 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -400 0 -400 +P 2 0 1 10 0 -400 0 300 +P 2 0 1 10 0 300 -400 300 +X VCCADC_0 K10 200 200 200 L 70 70 0 1 P +X GNDADC_0 K9 200 -300 200 L 70 70 0 1 P +X VP_0 L10 200 100 200 L 70 70 0 1 P +X VREFN_0 L9 200 -200 200 L 70 70 0 1 P +X VREFP_0 M10 200 -100 200 L 70 70 0 1 P +X VN_0 M9 200 0 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_2 +# +DEF XC7A200TFBG484_2 IC 0 40 Y Y 1 F N +F0 "U" -410 -2210 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2100 0 -2100 +P 2 0 1 10 0 -2100 0 2000 +P 2 0 1 10 0 2000 -400 2000 +X IO_L9P_T1_DQS_13 AA10 200 -300 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_13 AA11 200 -400 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_13 AA13 200 900 200 L 70 70 0 1 P +X IO_L5N_T0_13 AA14 200 400 200 L 70 70 0 1 P +X IO_L4P_T0_13 AA15 200 700 200 L 70 70 0 1 P +X IO_L1N_T0_13 AA16 200 1200 200 L 70 70 0 1 P +X VCCO_13 AA17 200 1600 200 L 70 70 0 1 P +X IO_L8P_T1_13 AA9 200 -100 200 L 70 70 0 1 P +X IO_L8N_T1_13 AB10 200 -200 200 L 70 70 0 1 P +X IO_L7P_T1_13 AB11 200 100 200 L 70 70 0 1 P +X IO_L7N_T1_13 AB12 200 0 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_13 AB13 200 800 200 L 70 70 0 1 P +X VCCO_13 AB14 200 1500 200 L 70 70 0 1 P +X IO_L4N_T0_13 AB15 200 600 200 L 70 70 0 1 P +X IO_L2P_T0_13 AB16 200 1100 200 L 70 70 0 1 P +X IO_L2N_T0_13 AB17 200 1000 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_13 T14 200 -1500 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_13 T15 200 -1600 200 L 70 70 0 1 P +X IO_L17P_T2_13 T16 200 -1900 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_13 U15 200 -1300 200 L 70 70 0 1 P +X IO_L17N_T2_13 U16 200 -2000 200 L 70 70 0 1 P +X IO_L10P_T1_13 V10 200 -500 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_13 V13 200 -1100 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_13 V14 200 -1200 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_13 V15 200 -1400 200 L 70 70 0 1 P +X VCCO_13 V16 200 1900 200 L 70 70 0 1 P +X IO_L10N_T1_13 W10 200 -600 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_13 W11 200 -900 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_13 W12 200 -1000 200 L 70 70 0 1 P +X VCCO_13 W13 200 1800 200 L 70 70 0 1 P +X IO_L6P_T0_13 W14 200 300 200 L 70 70 0 1 P +X IO_L16P_T2_13 W15 200 -1700 200 L 70 70 0 1 P +X IO_L16N_T2_13 W16 200 -1800 200 L 70 70 0 1 P +X VCCO_13 Y10 200 1700 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_13 Y11 200 -700 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_13 Y12 200 -800 200 L 70 70 0 1 P +X IO_L5P_T0_13 Y13 200 500 200 L 70 70 0 1 P +X IO_L6N_T0_VREF_13 Y14 200 200 200 L 70 70 0 1 P +X IO_L1P_T0_13 Y16 200 1300 200 L 70 70 0 1 P +X IO_0_13 Y17 200 1400 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_3 +# +DEF XC7A200TFBG484_3 IC 0 40 Y Y 1 F N +F0 "U" -410 -3010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2900 0 -2900 +P 2 0 1 10 0 -2900 0 2800 +P 2 0 1 10 0 2800 -400 2800 +X IO_L17P_T2_A14_D30_14 AA18 200 -1200 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_RDWR_B_14 AA19 200 -800 200 L 70 70 0 1 P +X IO_L8P_T1_D11_14 AA20 200 600 200 L 70 70 0 1 P +X IO_L8N_T1_D12_14 AA21 200 500 200 L 70 70 0 1 P +X IO_L17N_T2_A13_D29_14 AB18 200 -1300 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_DOUT_CSO_B_14 AB20 200 -900 200 L 70 70 0 1 P +X IO_L10P_T1_D14_14 AB21 200 200 200 L 70 70 0 1 P +X IO_L10N_T1_D15_14 AB22 200 100 200 L 70 70 0 1 P +X VCCO_14 M14 200 2700 200 L 70 70 0 1 P +X IO_L23P_T3_A03_D19_14 N13 200 -2400 200 L 70 70 0 1 P +X IO_L23N_T3_A02_D18_14 N14 200 -2500 200 L 70 70 0 1 P +X IO_25_14 N15 200 -2800 200 L 70 70 0 1 P +X IO_L21P_T3_DQS_14 N17 200 -2000 200 L 70 70 0 1 P +X IO_L19P_T3_A10_D26_14 P14 200 -1600 200 L 70 70 0 1 P +X IO_L22P_T3_A05_D21_14 P15 200 -2200 200 L 70 70 0 1 P +X IO_L24P_T3_A01_D17_14 P16 200 -2600 200 L 70 70 0 1 P +X IO_L21N_T3_DQS_A06_D22_14 P17 200 -2100 200 L 70 70 0 1 P +X VCCO_14 P18 200 2600 200 L 70 70 0 1 P +X IO_L5P_T0_D06_14 P19 200 1200 200 L 70 70 0 1 P +X IO_0_14 P20 200 2100 200 L 70 70 0 1 P +X IO_L2P_T0_D02_14 P21 200 1800 200 L 70 70 0 1 P +X IO_L1P_T0_D00_MOSI_14 P22 200 2000 200 L 70 70 0 1 P +X IO_L19N_T3_A09_D25_VREF_14 R14 200 -1700 200 L 70 70 0 1 P +X VCCO_14 R15 200 2500 200 L 70 70 0 1 P +X IO_L22N_T3_A04_D20_14 R16 200 -2300 200 L 70 70 0 1 P +X IO_L24N_T3_A00_D16_14 R17 200 -2700 200 L 70 70 0 1 P +X IO_L20P_T3_A08_D24_14 R18 200 -1800 200 L 70 70 0 1 P +X IO_L5N_T0_D07_14 R19 200 1100 200 L 70 70 0 1 P +X IO_L2N_T0_D03_14 R21 200 1700 200 L 70 70 0 1 P +X IO_L1N_T0_D01_DIN_14 R22 200 1900 200 L 70 70 0 1 P +X IO_L20N_T3_A07_D23_14 T18 200 -1900 200 L 70 70 0 1 P +X IO_L6P_T0_FCS_B_14 T19 200 1000 200 L 70 70 0 1 P +X IO_L6N_T0_D08_VREF_14 T20 200 900 200 L 70 70 0 1 P +X IO_L4P_T0_D04_14 T21 200 1400 200 L 70 70 0 1 P +X VCCO_14 T22 200 2400 200 L 70 70 0 1 P +X IO_L18P_T2_A12_D28_14 U17 200 -1400 200 L 70 70 0 1 P +X IO_L18N_T2_A11_D27_14 U18 200 -1500 200 L 70 70 0 1 P +X VCCO_14 U19 200 2300 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_14 U20 200 0 200 L 70 70 0 1 P +X IO_L4N_T0_D05_14 U21 200 1300 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_PUDC_B_14 U22 200 1600 200 L 70 70 0 1 P +X IO_L16P_T2_CSI_B_14 V17 200 -1000 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_14 V18 200 -600 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_14 V19 200 -700 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_14 V20 200 -100 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_EMCCLK_14 V22 200 1500 200 L 70 70 0 1 P +X IO_L16N_T2_A15_D31_14 W17 200 -1100 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_14 W19 200 -200 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_14 W20 200 -300 200 L 70 70 0 1 P +X IO_L7P_T1_D09_14 W21 200 800 200 L 70 70 0 1 P +X IO_L7N_T1_D10_14 W22 200 700 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_14 Y18 200 -400 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_14 Y19 200 -500 200 L 70 70 0 1 P +X VCCO_14 Y20 200 2200 200 L 70 70 0 1 P +X IO_L9P_T1_DQS_14 Y21 200 400 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_D13_14 Y22 200 300 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_4 +# +DEF XC7A200TFBG484_4 IC 0 40 Y Y 1 F N +F0 "U" -410 -3010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2900 0 -2900 +P 2 0 1 10 0 -2900 0 2800 +P 2 0 1 10 0 2800 -400 2800 +X IO_L1N_T0_AD0N_15 G13 200 1900 200 L 70 70 0 1 P +X IO_L2P_T0_AD8P_15 G15 200 1800 200 L 70 70 0 1 P +X IO_L2N_T0_AD8N_15 G16 200 1700 200 L 70 70 0 1 P +X IO_L4P_T0_15 G17 200 1400 200 L 70 70 0 1 P +X IO_L4N_T0_15 G18 200 1300 200 L 70 70 0 1 P +X VCCO_15 G19 200 2700 200 L 70 70 0 1 P +X IO_L8N_T1_AD10N_15 G20 200 500 200 L 70 70 0 1 P +X IO_L1P_T0_AD0P_15 H13 200 2000 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_AD1N_15 H14 200 1500 200 L 70 70 0 1 P +X IO_L5N_T0_AD9N_15 H15 200 1100 200 L 70 70 0 1 P +X VCCO_15 H16 200 2600 200 L 70 70 0 1 P +X IO_L6P_T0_15 H17 200 1000 200 L 70 70 0 1 P +X IO_L6N_T0_VREF_15 H18 200 900 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_15 H19 200 -300 200 L 70 70 0 1 P +X IO_L8P_T1_AD10P_15 H20 200 600 200 L 70 70 0 1 P +X IO_L7N_T1_AD2N_15 H22 200 700 200 L 70 70 0 1 P +X VCCO_15 J13 200 2500 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_AD1P_15 J14 200 1600 200 L 70 70 0 1 P +X IO_L5P_T0_AD9P_15 J15 200 1200 200 L 70 70 0 1 P +X IO_0_15 J16 200 2100 200 L 70 70 0 1 P +X IO_L21N_T3_DQS_A18_15 J17 200 -2100 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_15 J19 200 -200 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_15 J20 200 0 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_15 J21 200 -100 200 L 70 70 0 1 P +X IO_L7P_T1_AD2P_15 J22 200 800 200 L 70 70 0 1 P +X IO_L19P_T3_A22_15 K13 200 -1600 200 L 70 70 0 1 P +X IO_L19N_T3_A21_VREF_15 K14 200 -1700 200 L 70 70 0 1 P +X IO_L23N_T3_FWE_B_15 K16 200 -2500 200 L 70 70 0 1 P +X IO_L21P_T3_DQS_15 K17 200 -2000 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_15 K18 200 -400 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_15 K19 200 -500 200 L 70 70 0 1 P +X VCCO_15 K20 200 2400 200 L 70 70 0 1 P +X IO_L9P_T1_DQS_AD3P_15 K21 200 400 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_AD3N_15 K22 200 300 200 L 70 70 0 1 P +X IO_L20N_T3_A19_15 L13 200 -1900 200 L 70 70 0 1 P +X IO_L22P_T3_A17_15 L14 200 -2200 200 L 70 70 0 1 P +X IO_L22N_T3_A16_15 L15 200 -2300 200 L 70 70 0 1 P +X IO_L23P_T3_FOE_B_15 L16 200 -2400 200 L 70 70 0 1 P +X VCCO_15 L17 200 2300 200 L 70 70 0 1 P +X IO_L16N_T2_A27_15 L18 200 -1100 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_15 L19 200 -600 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_15 L20 200 -700 200 L 70 70 0 1 P +X IO_L10N_T1_AD11N_15 L21 200 100 200 L 70 70 0 1 P +X IO_L20P_T3_A20_15 M13 200 -1800 200 L 70 70 0 1 P +X IO_L24P_T3_RS1_15 M15 200 -2600 200 L 70 70 0 1 P +X IO_L24N_T3_RS0_15 M16 200 -2700 200 L 70 70 0 1 P +X IO_25_15 M17 200 -2800 200 L 70 70 0 1 P +X IO_L16P_T2_A28_15 M18 200 -1000 200 L 70 70 0 1 P +X IO_L18N_T2_A23_15 M20 200 -1500 200 L 70 70 0 1 P +X IO_L10P_T1_AD11P_15 M21 200 200 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_ADV_B_15 M22 200 -900 200 L 70 70 0 1 P +X IO_L17P_T2_A26_15 N18 200 -1200 200 L 70 70 0 1 P +X IO_L17N_T2_A25_15 N19 200 -1300 200 L 70 70 0 1 P +X IO_L18P_T2_A24_15 N20 200 -1400 200 L 70 70 0 1 P +X VCCO_15 N21 200 2200 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_15 N22 200 -800 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_5 +# +DEF XC7A200TFBG484_5 IC 0 40 Y Y 1 F N +F0 "U" -410 -3010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2900 0 -2900 +P 2 0 1 10 0 -2900 0 2800 +P 2 0 1 10 0 2800 -400 2800 +X IO_L10P_T1_16 A13 200 200 200 L 70 70 0 1 P +X IO_L10N_T1_16 A14 200 100 200 L 70 70 0 1 P +X IO_L9P_T1_DQS_16 A15 200 400 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_16 A16 200 300 200 L 70 70 0 1 P +X VCCO_16 A17 200 2700 200 L 70 70 0 1 P +X IO_L17P_T2_16 A18 200 -1200 200 L 70 70 0 1 P +X IO_L17N_T2_16 A19 200 -1300 200 L 70 70 0 1 P +X IO_L16N_T2_16 A20 200 -1100 200 L 70 70 0 1 P +X IO_L21N_T3_DQS_16 A21 200 -2100 200 L 70 70 0 1 P +X IO_L8N_T1_16 B13 200 500 200 L 70 70 0 1 P +X VCCO_16 B14 200 2600 200 L 70 70 0 1 P +X IO_L7P_T1_16 B15 200 800 200 L 70 70 0 1 P +X IO_L7N_T1_16 B16 200 700 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_16 B17 200 0 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_16 B18 200 -100 200 L 70 70 0 1 P +X IO_L16P_T2_16 B20 200 -1000 200 L 70 70 0 1 P +X IO_L21P_T3_DQS_16 B21 200 -2000 200 L 70 70 0 1 P +X IO_L20N_T3_16 B22 200 -1900 200 L 70 70 0 1 P +X IO_L8P_T1_16 C13 200 600 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_16 C14 200 1600 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_16 C15 200 1500 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_16 C17 200 -300 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_16 C18 200 -400 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_16 C19 200 -500 200 L 70 70 0 1 P +X IO_L19N_T3_VREF_16 C20 200 -1700 200 L 70 70 0 1 P +X VCCO_16 C21 200 2500 200 L 70 70 0 1 P +X IO_L20P_T3_16 C22 200 -1800 200 L 70 70 0 1 P +X IO_L6P_T0_16 D14 200 1000 200 L 70 70 0 1 P +X IO_L6N_T0_VREF_16 D15 200 900 200 L 70 70 0 1 P +X IO_L5N_T0_16 D16 200 1100 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_16 D17 200 -200 200 L 70 70 0 1 P +X VCCO_16 D18 200 2400 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_16 D19 200 -700 200 L 70 70 0 1 P +X IO_L19P_T3_16 D20 200 -1600 200 L 70 70 0 1 P +X IO_L23N_T3_16 D21 200 -2500 200 L 70 70 0 1 P +X IO_L22N_T3_16 D22 200 -2300 200 L 70 70 0 1 P +X IO_L4P_T0_16 E13 200 1400 200 L 70 70 0 1 P +X IO_L4N_T0_16 E14 200 1300 200 L 70 70 0 1 P +X VCCO_16 E15 200 2300 200 L 70 70 0 1 P +X IO_L5P_T0_16 E16 200 1200 200 L 70 70 0 1 P +X IO_L2N_T0_16 E17 200 1700 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_16 E18 200 -900 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_16 E19 200 -600 200 L 70 70 0 1 P +X IO_L23P_T3_16 E21 200 -2400 200 L 70 70 0 1 P +X IO_L22P_T3_16 E22 200 -2200 200 L 70 70 0 1 P +X IO_L1P_T0_16 F13 200 2000 200 L 70 70 0 1 P +X IO_L1N_T0_16 F14 200 1900 200 L 70 70 0 1 P +X IO_0_16 F15 200 2100 200 L 70 70 0 1 P +X IO_L2P_T0_16 F16 200 1800 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_16 F18 200 -800 200 L 70 70 0 1 P +X IO_L18P_T2_16 F19 200 -1400 200 L 70 70 0 1 P +X IO_L18N_T2_16 F20 200 -1500 200 L 70 70 0 1 P +X IO_25_16 F21 200 -2800 200 L 70 70 0 1 P +X VCCO_16 F22 200 2200 200 L 70 70 0 1 P +X IO_L24P_T3_16 G21 200 -2600 200 L 70 70 0 1 P +X IO_L24N_T3_16 G22 200 -2700 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_6 +# +DEF XC7A200TFBG484_6 IC 0 40 Y Y 1 F N +F0 "U" -410 -3010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2900 0 -2900 +P 2 0 1 10 0 -2900 0 2800 +P 2 0 1 10 0 2800 -400 2800 +X IO_L7P_T1_34 AA1 200 800 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_34 AA3 200 300 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_34 AA4 200 -100 200 L 70 70 0 1 P +X IO_L10P_T1_34 AA5 200 200 200 L 70 70 0 1 P +X IO_L18N_T2_34 AA6 200 -1500 200 L 70 70 0 1 P +X VCCO_34 AA7 200 2300 200 L 70 70 0 1 P +X IO_L22P_T3_34 AA8 200 -2200 200 L 70 70 0 1 P +X IO_L7N_T1_34 AB1 200 700 200 L 70 70 0 1 P +X IO_L8N_T1_34 AB2 200 500 200 L 70 70 0 1 P +X IO_L8P_T1_34 AB3 200 600 200 L 70 70 0 1 P +X VCCO_34 AB4 200 2200 200 L 70 70 0 1 P +X IO_L10N_T1_34 AB5 200 100 200 L 70 70 0 1 P +X IO_L20N_T3_34 AB6 200 -1900 200 L 70 70 0 1 P +X IO_L20P_T3_34 AB7 200 -1800 200 L 70 70 0 1 P +X IO_L22N_T3_34 AB8 200 -2300 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_34 R2 200 1500 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_34 R3 200 1600 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_34 R4 200 -400 200 L 70 70 0 1 P +X VCCO_34 R5 200 2700 200 L 70 70 0 1 P +X IO_L17P_T2_34 R6 200 -1200 200 L 70 70 0 1 P +X IO_L1P_T0_34 T1 200 2000 200 L 70 70 0 1 P +X VCCO_34 T2 200 2600 200 L 70 70 0 1 P +X IO_0_34 T3 200 2100 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_34 T4 200 -500 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_34 T5 200 -600 200 L 70 70 0 1 P +X IO_L17N_T2_34 T6 200 -1300 200 L 70 70 0 1 P +X IO_L1N_T0_34 U1 200 1900 200 L 70 70 0 1 P +X IO_L2P_T0_34 U2 200 1800 200 L 70 70 0 1 P +X IO_L6P_T0_34 U3 200 1000 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_34 U5 200 -700 200 L 70 70 0 1 P +X IO_L16P_T2_34 U6 200 -1000 200 L 70 70 0 1 P +X IO_25_34 U7 200 -2800 200 L 70 70 0 1 P +X IO_L2N_T0_34 V2 200 1700 200 L 70 70 0 1 P +X IO_L6N_T0_VREF_34 V3 200 900 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_34 V4 200 -200 200 L 70 70 0 1 P +X IO_L16N_T2_34 V5 200 -1100 200 L 70 70 0 1 P +X VCCO_34 V6 200 2500 200 L 70 70 0 1 P +X IO_L19P_T3_34 V7 200 -1600 200 L 70 70 0 1 P +X IO_L21N_T3_DQS_34 V8 200 -2100 200 L 70 70 0 1 P +X IO_L21P_T3_DQS_34 V9 200 -2000 200 L 70 70 0 1 P +X IO_L5P_T0_34 W1 200 1200 200 L 70 70 0 1 P +X IO_L4P_T0_34 W2 200 1400 200 L 70 70 0 1 P +X VCCO_34 W3 200 2400 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_34 W4 200 -300 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_34 W5 200 -900 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_34 W6 200 -800 200 L 70 70 0 1 P +X IO_L19N_T3_VREF_34 W7 200 -1700 200 L 70 70 0 1 P +X IO_L24P_T3_34 W9 200 -2600 200 L 70 70 0 1 P +X IO_L5N_T0_34 Y1 200 1100 200 L 70 70 0 1 P +X IO_L4N_T0_34 Y2 200 1300 200 L 70 70 0 1 P +X IO_L9P_T1_DQS_34 Y3 200 400 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_34 Y4 200 0 200 L 70 70 0 1 P +X IO_L18P_T2_34 Y6 200 -1400 200 L 70 70 0 1 P +X IO_L23N_T3_34 Y7 200 -2500 200 L 70 70 0 1 P +X IO_L23P_T3_34 Y8 200 -2400 200 L 70 70 0 1 P +X IO_L24N_T3_34 Y9 200 -2700 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_7 +# +DEF XC7A200TFBG484_7 IC 0 40 Y Y 1 F N +F0 "U" -410 -3010 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2900 0 -2900 +P 2 0 1 10 0 -2900 0 2800 +P 2 0 1 10 0 2800 -400 2800 +X IO_L1N_T0_AD4N_35 A1 200 1900 200 L 70 70 0 1 P +X IO_L1P_T0_AD4P_35 B1 200 2000 200 L 70 70 0 1 P +X IO_L2N_T0_AD12N_35 B2 200 1700 200 L 70 70 0 1 P +X VCCO_35 C1 200 2700 200 L 70 70 0 1 P +X IO_L2P_T0_AD12P_35 C2 200 1800 200 L 70 70 0 1 P +X IO_L3N_T0_DQS_AD5N_35 D1 200 1500 200 L 70 70 0 1 P +X IO_L4N_T0_35 D2 200 1300 200 L 70 70 0 1 P +X IO_L3P_T0_DQS_AD5P_35 E1 200 1600 200 L 70 70 0 1 P +X IO_L4P_T0_35 E2 200 1400 200 L 70 70 0 1 P +X IO_L6N_T0_VREF_35 E3 200 900 200 L 70 70 0 1 P +X IO_L5N_T0_AD13N_35 F1 200 1100 200 L 70 70 0 1 P +X VCCO_35 F2 200 2600 200 L 70 70 0 1 P +X IO_L6P_T0_35 F3 200 1000 200 L 70 70 0 1 P +X IO_0_35 F4 200 2100 200 L 70 70 0 1 P +X IO_L5P_T0_AD13P_35 G1 200 1200 200 L 70 70 0 1 P +X IO_L8N_T1_AD14N_35 G2 200 500 200 L 70 70 0 1 P +X IO_L11N_T1_SRCC_35 G3 200 -100 200 L 70 70 0 1 P +X IO_L12N_T1_MRCC_35 G4 200 -300 200 L 70 70 0 1 P +X IO_L8P_T1_AD14P_35 H2 200 600 200 L 70 70 0 1 P +X IO_L11P_T1_SRCC_35 H3 200 0 200 L 70 70 0 1 P +X IO_L12P_T1_MRCC_35 H4 200 -200 200 L 70 70 0 1 P +X IO_L10N_T1_AD15N_35 H5 200 100 200 L 70 70 0 1 P +X VCCO_35 H6 200 2500 200 L 70 70 0 1 P +X IO_L7N_T1_AD6N_35 J1 200 700 200 L 70 70 0 1 P +X IO_L9N_T1_DQS_AD7N_35 J2 200 300 200 L 70 70 0 1 P +X VCCO_35 J3 200 2400 200 L 70 70 0 1 P +X IO_L13N_T2_MRCC_35 J4 200 -500 200 L 70 70 0 1 P +X IO_L10P_T1_AD15P_35 J5 200 200 200 L 70 70 0 1 P +X IO_L17N_T2_35 J6 200 -1300 200 L 70 70 0 1 P +X IO_L7P_T1_AD6P_35 K1 200 800 200 L 70 70 0 1 P +X IO_L9P_T1_DQS_AD7P_35 K2 200 400 200 L 70 70 0 1 P +X IO_L14N_T2_SRCC_35 K3 200 -700 200 L 70 70 0 1 P +X IO_L13P_T2_MRCC_35 K4 200 -400 200 L 70 70 0 1 P +X IO_L17P_T2_35 K6 200 -1200 200 L 70 70 0 1 P +X IO_L15N_T2_DQS_35 L1 200 -900 200 L 70 70 0 1 P +X IO_L14P_T2_SRCC_35 L3 200 -600 200 L 70 70 0 1 P +X IO_L18N_T2_35 L4 200 -1500 200 L 70 70 0 1 P +X IO_L18P_T2_35 L5 200 -1400 200 L 70 70 0 1 P +X IO_25_35 L6 200 -2800 200 L 70 70 0 1 P +X IO_L15P_T2_DQS_35 M1 200 -800 200 L 70 70 0 1 P +X IO_L16N_T2_35 M2 200 -1100 200 L 70 70 0 1 P +X IO_L16P_T2_35 M3 200 -1000 200 L 70 70 0 1 P +X VCCO_35 M4 200 2300 200 L 70 70 0 1 P +X IO_L23N_T3_35 M5 200 -2500 200 L 70 70 0 1 P +X IO_L23P_T3_35 M6 200 -2400 200 L 70 70 0 1 P +X VCCO_35 N1 200 2200 200 L 70 70 0 1 P +X IO_L22N_T3_35 N2 200 -2300 200 L 70 70 0 1 P +X IO_L19N_T3_VREF_35 N3 200 -1700 200 L 70 70 0 1 P +X IO_L19P_T3_35 N4 200 -1600 200 L 70 70 0 1 P +X IO_L24N_T3_35 N5 200 -2700 200 L 70 70 0 1 P +X IO_L20N_T3_35 P1 200 -1900 200 L 70 70 0 1 P +X IO_L22P_T3_35 P2 200 -2200 200 L 70 70 0 1 P +X IO_L21N_T3_DQS_35 P4 200 -2100 200 L 70 70 0 1 P +X IO_L21P_T3_DQS_35 P5 200 -2000 200 L 70 70 0 1 P +X IO_L24P_T3_35 P6 200 -2600 200 L 70 70 0 1 P +X IO_L20P_T3_35 R1 200 -1800 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_8 +# +DEF XC7A200TFBG484_8 IC 0 40 Y Y 1 F N +F0 "U" -410 -1210 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -1100 0 -1100 +P 2 0 1 10 0 -1100 0 1100 +P 2 0 1 10 0 1100 -400 1100 +X MGTPRXN1_216 A10 200 800 200 L 70 70 0 1 P +X MGTPTXN3_216 A4 200 -200 200 L 70 70 0 1 P +X MGTPTXN1_216 A6 200 0 200 L 70 70 0 1 P +X MGTPRXN3_216 A8 200 600 200 L 70 70 0 1 P +X MGTPRXP1_216 B10 200 400 200 L 70 70 0 1 P +X MGTPTXP3_216 B4 200 -600 200 L 70 70 0 1 P +X MGTPTXP1_216 B6 200 -400 200 L 70 70 0 1 P +X MGTPRXP3_216 B8 200 200 200 L 70 70 0 1 P +X MGTPRXN0_216 C11 200 900 200 L 70 70 0 1 P +X MGTPTXN2_216 C5 200 -100 200 L 70 70 0 1 P +X MGTPTXN0_216 C7 200 100 200 L 70 70 0 1 P +X MGTPRXN2_216 C9 200 700 200 L 70 70 0 1 P +X MGTPRXP0_216 D11 200 500 200 L 70 70 0 1 P +X MGTPTXP2_216 D5 200 -500 200 L 70 70 0 1 P +X MGTPTXP0_216 D7 200 -300 200 L 70 70 0 1 P +X MGTPRXP2_216 D9 200 300 200 L 70 70 0 1 P +X MGTREFCLK0N_216 E10 200 -800 200 L 70 70 0 1 P +X MGTREFCLK1N_216 E6 200 -1000 200 L 70 70 0 1 P +X MGTREFCLK0P_216 F10 200 -700 200 L 70 70 0 1 P +X MGTREFCLK1P_216 F6 200 -900 200 L 70 70 0 1 P +X MGTRREF_216 F8 200 1000 200 L 70 70 0 1 P +ENDDRAW +ENDDEF +# +# XC7A200TFBG484_9 +# +DEF XC7A200TFBG484_9 IC 0 40 Y Y 1 F N +F0 "U" -410 -2410 60 H V L BNN +F1 "" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 10 -400 -2300 0 -2300 +P 2 0 1 10 0 -2300 0 2200 +P 2 0 1 10 0 2200 -400 2200 +X GND A11 200 1600 200 L 70 70 0 1 W +X GND A12 200 1500 200 L 70 70 0 1 W +X GND A2 200 2100 200 L 70 70 0 1 W +X GND A22 200 1400 200 L 70 70 0 1 W +X GND A3 200 2000 200 L 70 70 0 1 W +X GND A5 200 1900 200 L 70 70 0 1 W +X GND A7 200 1800 200 L 70 70 0 1 W +X GND A9 200 1700 200 L 70 70 0 1 W +X GND B12 200 1200 200 L 70 70 0 1 W +X GND B19 200 1100 200 L 70 70 0 1 W +X GND B3 200 1300 200 L 70 70 0 1 W +X GND C10 200 800 200 L 70 70 0 1 W +X GND C12 200 700 200 L 70 70 0 1 W +X GND C16 200 600 200 L 70 70 0 1 W +X GND C3 200 1000 200 L 70 70 0 1 W +X GND C6 200 900 200 L 70 70 0 1 W +X GND D12 200 200 200 L 70 70 0 1 W +X GND D13 200 100 200 L 70 70 0 1 W +X GND D3 200 500 200 L 70 70 0 1 W +X GND D4 200 400 200 L 70 70 0 1 W +X GND D8 200 300 200 L 70 70 0 1 W +X GND E11 200 -400 200 L 70 70 0 1 W +X GND E20 200 -500 200 L 70 70 0 1 W +X GND E4 200 0 200 L 70 70 0 1 W +X GND E5 200 -100 200 L 70 70 0 1 W +X GND E7 200 -200 200 L 70 70 0 1 W +X GND E9 200 -300 200 L 70 70 0 1 W +X GND F11 200 -700 200 L 70 70 0 1 W +X GND F17 200 -800 200 L 70 70 0 1 W +X GND F5 200 -600 200 L 70 70 0 1 W +X GND G10 200 -1400 200 L 70 70 0 1 W +X GND G12 200 -1500 200 L 70 70 0 1 W +X GND G14 200 -1600 200 L 70 70 0 1 W +X GND G5 200 -900 200 L 70 70 0 1 W +X GND G6 200 -1000 200 L 70 70 0 1 W +X GND G7 200 -1100 200 L 70 70 0 1 W +X GND G8 200 -1200 200 L 70 70 0 1 W +X GND G9 200 -1300 200 L 70 70 0 1 W +X GND H1 200 -1700 200 L 70 70 0 1 W +X GND H11 200 -2000 200 L 70 70 0 1 W +X GND H21 200 -2100 200 L 70 70 0 1 W +X GND H7 200 -1800 200 L 70 70 0 1 W +X GND H9 200 -1900 200 L 70 70 0 1 W +X GND J8 200 -2200 200 L 70 70 0 1 W +ENDDRAW +ENDDEF +# +# XTAL-3.2X1.5 +# +DEF XTAL-3.2X1.5 IC 0 40 Y Y 1 F N +F0 "X" -110 -210 60 H V L BNN +F1 "XTAL-3.2X1.5" -170 -750 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 -220 110 50 0 1 1 2101347 Normal 1 C C +T 0 -220 110 50 0 1 1 ABS07-32.768KHZ-T Normal 1 C C +P 2 0 1 10 -100 -100 -100 100 +P 2 0 1 10 -50 -100 -50 100 +P 2 0 1 10 -50 100 50 100 +P 2 0 1 10 50 -100 -50 -100 +P 2 0 1 10 50 100 50 -100 +P 2 0 1 10 100 -100 100 100 +X P$1 P$1 -200 0 100 R 1 1 0 1 P +X P$2 P$2 200 0 100 L 1 1 0 1 P +ENDDRAW +ENDDEF +# +# XTAL-4-3225 +# +DEF XTAL-4-3225 IC 0 40 Y Y 1 F N +F0 "Q" -110 -430 60 H V L BNN +F1 "XTAL-4-3225" -470 230 60 H V L BNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 -220 110 50 0 1 1 2467848 Normal 1 C C +T 0 -220 110 50 0 1 1 ABM8G-25.000MHZ-4Y-T3 Normal 1 C C +P 2 0 1 10 -100 -100 -100 100 +P 2 0 1 10 -50 -100 -50 100 +P 2 0 1 10 -50 100 50 100 +P 2 0 1 10 50 -100 -50 -100 +P 2 0 1 10 50 100 50 -100 +P 2 0 1 10 100 -100 100 100 +X X1 1 -200 0 100 R 1 1 0 1 P +X G2 2 200 -300 200 L 1 1 0 1 W +X X2 3 200 0 100 L 1 1 0 1 P +X G1 4 -200 -300 200 R 1 1 0 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/KiCAD/footprints.pretty/694106301002.kicad_mod b/KiCAD/footprints.pretty/694106301002.kicad_mod new file mode 100644 index 0000000..82fb7c4 --- /dev/null +++ b/KiCAD/footprints.pretty/694106301002.kicad_mod @@ -0,0 +1,22 @@ +(module 694106301002 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth Power Connector 5.5x2.1mm Barrel" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill 0.8) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/PJ-002A.wrl + (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 180 270)) + ) + (model wrlshp/51D2E761-0F4D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/ASF.kicad_mod b/KiCAD/footprints.pretty/ASF.kicad_mod new file mode 100644 index 0000000..27c5194 --- /dev/null +++ b/KiCAD/footprints.pretty/ASF.kicad_mod @@ -0,0 +1,13 @@ +(module ASF (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference Q5 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.1302 -1.2954 90) (size 1.7018 1.4986) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 1.1302 1.2524 90) (size 1.7018 1.4986) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.0922 -1.2954 90) (size 1.7018 1.4986) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.0922 1.2524 90) (size 1.7018 1.4986) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/B1,27.kicad_mod b/KiCAD/footprints.pretty/B1,27.kicad_mod new file mode 100644 index 0000000..3e8ec71 --- /dev/null +++ b/KiCAD/footprints.pretty/B1,27.kicad_mod @@ -0,0 +1,10 @@ +(module B1,27 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference TP2 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/BGA484C100P22X22_2300X2300X254.kicad_mod b/KiCAD/footprints.pretty/BGA484C100P22X22_2300X2300X254.kicad_mod new file mode 100644 index 0000000..41df308 --- /dev/null +++ b/KiCAD/footprints.pretty/BGA484C100P22X22_2300X2300X254.kicad_mod @@ -0,0 +1,498 @@ +(module BGA484C100P22X22_2300X2300X254 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U13 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "Xilinx FPGA: XC7A200TFBG484" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad A1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad A22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad B22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad C1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad C2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad C3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad C4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste 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F.Paste F.Mask)) + (pad U20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad U21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad U22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad V22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad W22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad Y22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AA22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (pad AB22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/041B98A5-F02D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/CRYSTAL_3.2X2.5.kicad_mod b/KiCAD/footprints.pretty/CRYSTAL_3.2X2.5.kicad_mod new file mode 100644 index 0000000..b5ddcd9 --- /dev/null +++ b/KiCAD/footprints.pretty/CRYSTAL_3.2X2.5.kicad_mod @@ -0,0 +1,13 @@ +(module CRYSTAL_3.2X2.5 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/C_0402.kicad_mod b/KiCAD/footprints.pretty/C_0402.kicad_mod new file mode 100644 index 0000000..ee43cff --- /dev/null +++ b/KiCAD/footprints.pretty/C_0402.kicad_mod @@ -0,0 +1,21 @@ +(module C_0402 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference C215 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/C_0603.kicad_mod b/KiCAD/footprints.pretty/C_0603.kicad_mod new file mode 100644 index 0000000..4d831da --- /dev/null +++ b/KiCAD/footprints.pretty/C_0603.kicad_mod @@ -0,0 +1,21 @@ +(module C_0603 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference C25 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "0603 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.7 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 0.7 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/SW3dPS-0603 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/175C1D2E-5B2D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/C_0805.kicad_mod b/KiCAD/footprints.pretty/C_0805.kicad_mod new file mode 100644 index 0000000..23f6ac9 --- /dev/null +++ b/KiCAD/footprints.pretty/C_0805.kicad_mod @@ -0,0 +1,21 @@ +(module C_0805 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference C180 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0805 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 -0.02489199962615967 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/68E8DA21-73BF.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/C_1210.kicad_mod b/KiCAD/footprints.pretty/C_1210.kicad_mod new file mode 100644 index 0000000..689de02 --- /dev/null +++ b/KiCAD/footprints.pretty/C_1210.kicad_mod @@ -0,0 +1,21 @@ +(module C_1210 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference C210 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "1210 CAPACITOR X5R 6.3V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 1.249933981227875 0 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/C_D.kicad_mod b/KiCAD/footprints.pretty/C_D.kicad_mod new file mode 100644 index 0000000..1a1215a --- /dev/null +++ b/KiCAD/footprints.pretty/C_D.kicad_mod @@ -0,0 +1,21 @@ +(module C_D (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference C127 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Kemet Tantalum Capacitor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/5917D381-109F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/DEFAULT.kicad_mod b/KiCAD/footprints.pretty/DEFAULT.kicad_mod new file mode 100644 index 0000000..6eb993d --- /dev/null +++ b/KiCAD/footprints.pretty/DEFAULT.kicad_mod @@ -0,0 +1,19 @@ +(module DEFAULT (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference "" (at 0 0) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_text value "" (at 0 0) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (pad "" smd circle (at 33.95002 -17.89048) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 63.2848 -47.85) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 71.32122 -80.16781) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 43.03928 -54.55775) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 9.99172 -2.51847) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 7.9015 -67.27208) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 96.14374 -8.09382) (size 1 1) (layers B.Cu B.Paste B.Mask)) + (pad "" smd circle (at 25.37908 -67.99652 180) (size 1 1) (layers F.Cu F.Paste F.Mask)) + (pad "" smd circle (at 81.71065 -85.63807 180) (size 1 1) (layers F.Cu F.Paste F.Mask)) + (pad "" smd circle (at 65.2394 -15.597 180) (size 1 1) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/HDR1X10.kicad_mod b/KiCAD/footprints.pretty/HDR1X10.kicad_mod new file mode 100644 index 0000000..3ba8dbb --- /dev/null +++ b/KiCAD/footprints.pretty/HDR1X10.kicad_mod @@ -0,0 +1,19 @@ +(module HDR1X10 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 10-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115)." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) +) diff --git a/KiCAD/footprints.pretty/LQFP-32.kicad_mod b/KiCAD/footprints.pretty/LQFP-32.kicad_mod new file mode 100644 index 0000000..54624e7 --- /dev/null +++ b/KiCAD/footprints.pretty/LQFP-32.kicad_mod @@ -0,0 +1,51 @@ +(module LQFP-32 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "IC, MCU, 8KB, FLASH, 20MHZ, TQFP-32" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 32 smd rect (at -4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at -4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at -4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at -4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at -4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at -4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at -2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd rect (at -2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at -1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at -0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at 4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at 4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at 4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at 4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd oval (at -2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/User Library-sot358-1.wrl" + (offset (xyz 0 -0.01066799983978271 0.7000011294870376)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/590BE70C-A1C3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/LQFP-48.kicad_mod b/KiCAD/footprints.pretty/LQFP-48.kicad_mod new file mode 100644 index 0000000..7f193a3 --- /dev/null +++ b/KiCAD/footprints.pretty/LQFP-48.kicad_mod @@ -0,0 +1,67 @@ +(module LQFP-48 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/L_0603.kicad_mod b/KiCAD/footprints.pretty/L_0603.kicad_mod new file mode 100644 index 0000000..d03dfa4 --- /dev/null +++ b/KiCAD/footprints.pretty/L_0603.kicad_mod @@ -0,0 +1,21 @@ +(module L_0603 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/L_1206.kicad_mod b/KiCAD/footprints.pretty/L_1206.kicad_mod new file mode 100644 index 0000000..ac594ff --- /dev/null +++ b/KiCAD/footprints.pretty/L_1206.kicad_mod @@ -0,0 +1,21 @@ +(module L_1206 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference FB7 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -1.4) (size 1.8 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 1.4) (size 1.8 1.4) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/NDY.kicad_mod b/KiCAD/footprints.pretty/NDY.kicad_mod new file mode 100644 index 0000000..cdf270d --- /dev/null +++ b/KiCAD/footprints.pretty/NDY.kicad_mod @@ -0,0 +1,21 @@ +(module NDY (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U1 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 11 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad TP1 smd rect (at -9.525 0 270) (size 9.144 13.3858) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/PLD-16.kicad_mod b/KiCAD/footprints.pretty/PLD-16.kicad_mod new file mode 100644 index 0000000..f01d1ae --- /dev/null +++ b/KiCAD/footprints.pretty/PLD-16.kicad_mod @@ -0,0 +1,35 @@ +(module PLD-16 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/PLD-6.kicad_mod b/KiCAD/footprints.pretty/PLD-6.kicad_mod new file mode 100644 index 0000000..668e3e7 --- /dev/null +++ b/KiCAD/footprints.pretty/PLD-6.kicad_mod @@ -0,0 +1,25 @@ +(module PLD-6 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/PLS-2.kicad_mod b/KiCAD/footprints.pretty/PLS-2.kicad_mod new file mode 100644 index 0000000..397be96 --- /dev/null +++ b/KiCAD/footprints.pretty/PLS-2.kicad_mod @@ -0,0 +1,21 @@ +(module PLS-2 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/PLS-3.kicad_mod b/KiCAD/footprints.pretty/PLS-3.kicad_mod new file mode 100644 index 0000000..44aa6e7 --- /dev/null +++ b/KiCAD/footprints.pretty/PLS-3.kicad_mod @@ -0,0 +1,22 @@ +(module PLS-3 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/pin_header_aw_108_03-t.wrl + (offset (xyz 0.05003799924850464 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/836C6F64-A2E5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/PLS-6.kicad_mod b/KiCAD/footprints.pretty/PLS-6.kicad_mod new file mode 100644 index 0000000..84b77ec --- /dev/null +++ b/KiCAD/footprints.pretty/PLS-6.kicad_mod @@ -0,0 +1,25 @@ +(module PLS-6 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference J1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl + (offset (xyz 0.006349999904632569 0.08635999870300293 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 360)) + ) + (model wrlshp/670BFB14-85C2.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/PLS-8.kicad_mod b/KiCAD/footprints.pretty/PLS-8.kicad_mod new file mode 100644 index 0000000..c4bfa7a --- /dev/null +++ b/KiCAD/footprints.pretty/PLS-8.kicad_mod @@ -0,0 +1,27 @@ +(module PLS-8 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/PLS-8.wrl + (offset (xyz 8.889999866485596 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/A962434E-CFE5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/QFN38.kicad_mod b/KiCAD/footprints.pretty/QFN38.kicad_mod new file mode 100644 index 0000000..2662c4a --- /dev/null +++ b/KiCAD/footprints.pretty/QFN38.kicad_mod @@ -0,0 +1,48 @@ +(module QFN38 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U15 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad PAD39 smd oval (at 0 1.26) (size 2.6 1.94) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd oval (at 1.905 -3 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd oval (at 1.905 -2.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd oval (at 1.905 -2 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd oval (at 1.905 -1.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd oval (at 1.905 -1 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd oval (at 1.905 -0.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at 1.905 0.508 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd oval (at 1.905 1.016 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at 1.905 1.524 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd oval (at 1.905 2.0066 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd oval (at 1.905 2.5146 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd oval (at 1.905 3.0226 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd oval (at 1.27 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd oval (at 0.762 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd oval (at 0.254 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd oval (at -0.25 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd oval (at -0.75 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd oval (at -1.25 3.4036 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd oval (at -1.9 3.0226) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd oval (at -1.9 2.5146) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd oval (at -1.9 2.0066) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd oval (at -1.9 1.524) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at -1.9 1.016) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd oval (at -1.9 0.508) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd oval (at -1.9 -0.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd oval (at -1.9 -1) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at -1.9 -1.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd oval (at -1.9 -2) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at -1.9 -2.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd oval (at -1.9 -3) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd oval (at -1.25 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd oval (at -0.75 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd oval (at -0.25 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd oval (at 0.254 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd oval (at 0.762 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd oval (at 1.27 -3.4 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/QFN68.kicad_mod b/KiCAD/footprints.pretty/QFN68.kicad_mod new file mode 100644 index 0000000..0857201 --- /dev/null +++ b/KiCAD/footprints.pretty/QFN68.kicad_mod @@ -0,0 +1,79 @@ +(module QFN68 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U16 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad PAD70 smd oval (at 3.55 2.65 180) (size 2.5 1.3) (layers F.Cu F.Paste F.Mask)) + (pad PAD69 smd oval (at -2.175 -0.625 270) (size 5.35 2.35) (layers F.Cu F.Paste F.Mask)) + (pad 68 smd oval (at 4.5 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 67 smd oval (at 4 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 66 smd oval (at 3.5 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 65 smd oval (at 3 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 64 smd oval (at 2.5 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 63 smd oval (at 2 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 62 smd oval (at 1.5 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 61 smd oval (at 1 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 60 smd oval (at 0.5 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 59 smd oval (at 0 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 58 smd oval (at -0.508 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 57 smd oval (at -1.016 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 56 smd oval (at -1.524 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 55 smd oval (at -2.0066 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 54 smd oval (at -2.5146 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 53 smd oval (at -3.0226 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 52 smd oval (at -3.5052 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 51 smd oval (at -4.0132 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 50 smd oval (at -4.5212 3.9116 90) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 49 smd oval (at -5.5118 3.5052) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 48 smd oval (at -5.5118 3.0226) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 47 smd oval (at -5.5118 2.5146) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd oval (at -5.5118 2.0066) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd oval (at -5.5118 1.524) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd oval (at -5.5118 1.016) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd oval (at -5.5118 0.508) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 41 smd oval (at -5.5118 -0.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd oval (at -5.5118 -1) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd oval (at -5.5118 -1.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd oval (at -5.5118 -2) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd oval (at -5.5118 -2.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd oval (at -5.5118 -3) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd oval (at -5.5118 -3.5) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd oval (at -4.5212 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd oval (at -4.0132 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd oval (at -3.5052 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at -3.0226 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd oval (at -2.5146 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at -2.0066 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd oval (at -1.524 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd oval (at -1.016 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd oval (at -0.508 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd oval (at 0 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd oval (at 0.5 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd oval (at 1 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd oval (at 1.5 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd oval (at 2 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd oval (at 2.5 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd oval (at 3 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd oval (at 3.5 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd oval (at 4 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd oval (at 4.5 -3.9 270) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at 5.5 -3.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd oval (at 5.5 -3 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at 5.5 -2.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd oval (at 5.5 -2 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd oval (at 5.5 -1.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at 5.5 -1 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd oval (at 5.5 -0.5 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd oval (at 5.5 0.508 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd oval (at 5.5 1.016 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd oval (at 5.5 1.524 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd oval (at 5.5 2.0066 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd oval (at 5.5 2.5146 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd oval (at 5.5 3.0226 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd oval (at 5.5 3.5052 180) (size 0.6096 0.254) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/RCLAMP0502A.kicad_mod b/KiCAD/footprints.pretty/RCLAMP0502A.kicad_mod new file mode 100644 index 0000000..0a48df2 --- /dev/null +++ b/KiCAD/footprints.pretty/RCLAMP0502A.kicad_mod @@ -0,0 +1,15 @@ +(module RCLAMP0502A (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/README.TXT b/KiCAD/footprints.pretty/README.TXT new file mode 100644 index 0000000..5327bca --- /dev/null +++ b/KiCAD/footprints.pretty/README.TXT @@ -0,0 +1,5 @@ +These files were created manually from the converted PCB using the menu option + + File -> Archive Footprints -> Create New Library and Archive Footprints + +in the KiCAD PCB editor. diff --git a/KiCAD/footprints.pretty/R_0402.kicad_mod b/KiCAD/footprints.pretty/R_0402.kicad_mod new file mode 100644 index 0000000..9aa2f39 --- /dev/null +++ b/KiCAD/footprints.pretty/R_0402.kicad_mod @@ -0,0 +1,21 @@ +(module R_0402 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference R37 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/SO08.kicad_mod b/KiCAD/footprints.pretty/SO08.kicad_mod new file mode 100644 index 0000000..31af3de --- /dev/null +++ b/KiCAD/footprints.pretty/SO08.kicad_mod @@ -0,0 +1,17 @@ +(module SO08 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/SO20W.kicad_mod b/KiCAD/footprints.pretty/SO20W.kicad_mod new file mode 100644 index 0000000..4e12dd1 --- /dev/null +++ b/KiCAD/footprints.pretty/SO20W.kicad_mod @@ -0,0 +1,29 @@ +(module SO20W (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference IC4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at 3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at 1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at 0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at -0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at -1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at -3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at -4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at -5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/SOIC127P600X175-8N.kicad_mod b/KiCAD/footprints.pretty/SOIC127P600X175-8N.kicad_mod new file mode 100644 index 0000000..40a5ef9 --- /dev/null +++ b/KiCAD/footprints.pretty/SOIC127P600X175-8N.kicad_mod @@ -0,0 +1,17 @@ +(module SOIC127P600X175-8N (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U12 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "64K SPI Bus Low-Power Serial SRAM,SOIC-8" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 smd rect (at -1.905 -2.6924 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at -0.635 -2.6924 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 0.635 -2.6924 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 1.905 -2.6924 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 1.905 2.7178 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 0.635 2.7178 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -0.635 2.7178 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -1.905 2.7178 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/SOT-23-5.kicad_mod b/KiCAD/footprints.pretty/SOT-23-5.kicad_mod new file mode 100644 index 0000000..63bd4ba --- /dev/null +++ b/KiCAD/footprints.pretty/SOT-23-5.kicad_mod @@ -0,0 +1,24 @@ +(module SOT-23-5 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U3 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "Single Inverter with Schmitt-Trigger Input" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 1.35 0.95 270) (size 0.65 1.1) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 1.35 0 270) (size 0.65 1.1) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.35 -0.95 270) (size 0.65 1.1) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.35 -0.95 270) (size 0.65 1.1) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -1.35 0.95 270) (size 0.65 1.1) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/User Library-SOT23-5-1.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/612DFB50-5309.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/SOT-23.kicad_mod b/KiCAD/footprints.pretty/SOT-23.kicad_mod new file mode 100644 index 0000000..10db8f7 --- /dev/null +++ b/KiCAD/footprints.pretty/SOT-23.kicad_mod @@ -0,0 +1,22 @@ +(module SOT-23 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference T2 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/TACTILE_SWITCH.kicad_mod b/KiCAD/footprints.pretty/TACTILE_SWITCH.kicad_mod new file mode 100644 index 0000000..1ea48cd --- /dev/null +++ b/KiCAD/footprints.pretty/TACTILE_SWITCH.kicad_mod @@ -0,0 +1,15 @@ +(module TACTILE_SWITCH (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference S2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Tacktile switch" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/TSOT-8-23.kicad_mod b/KiCAD/footprints.pretty/TSOT-8-23.kicad_mod new file mode 100644 index 0000000..0fdcc7e --- /dev/null +++ b/KiCAD/footprints.pretty/TSOT-8-23.kicad_mod @@ -0,0 +1,17 @@ +(module TSOT-8-23 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Micropower, Low Noise, 100mA LDO, Linear Regulator" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/TSQFP50P3000X3000X160-208N.kicad_mod b/KiCAD/footprints.pretty/TSQFP50P3000X3000X160-208N.kicad_mod new file mode 100644 index 0000000..647daa8 --- /dev/null +++ b/KiCAD/footprints.pretty/TSQFP50P3000X3000X160-208N.kicad_mod @@ -0,0 +1,222 @@ +(module TSQFP50P3000X3000X160-208N (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U4 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -14.75 -12.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd oval (at -14.75 -12.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd oval (at -14.75 -11.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd oval (at -14.75 -11.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd oval (at -14.75 -10.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd oval (at -14.75 -10.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd oval (at -14.75 -9.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at -14.75 -9.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd oval (at -14.75 -8.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at -14.75 -8.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd oval (at -14.75 -7.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd oval (at -14.75 -7.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at -14.75 -6.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd oval (at -14.75 -6.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at -14.75 -5.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd oval (at -14.75 -5.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd oval (at -14.75 -4.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd oval (at -14.75 -4.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd oval (at -14.75 -3.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd oval (at -14.75 -3.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd oval (at -14.75 -2.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd oval (at -14.75 -2.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd oval (at -14.75 -1.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd oval (at -14.75 -1.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd oval (at -14.75 -0.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd oval (at -14.75 -0.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd oval (at -14.75 0.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd oval (at -14.75 0.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at -14.75 1.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd oval (at -14.75 1.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at -14.75 2.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd oval (at -14.75 2.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd oval (at -14.75 3.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd oval (at -14.75 3.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd oval (at -14.75 4.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd oval (at -14.75 4.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd oval (at -14.75 5.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd oval (at -14.75 5.75 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd oval (at -14.75 6.25 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd oval (at -14.75 6.75 90) (size 0.3 1.2) (layers F.Cu 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1.2) (layers F.Cu F.Paste F.Mask)) + (pad 198 smd oval (at -7.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 199 smd oval (at -8.25 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 200 smd oval (at -8.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 201 smd oval (at -9.25 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 202 smd oval (at -9.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 203 smd oval (at -10.25 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 204 smd oval (at -10.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 205 smd oval (at -11.25 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 206 smd oval (at -11.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 207 smd oval (at -12.25 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 208 smd oval (at -12.75 -14.75) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/1B9BC620-BA33.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/TSSOP50P1180X120-86N.kicad_mod b/KiCAD/footprints.pretty/TSSOP50P1180X120-86N.kicad_mod new file mode 100644 index 0000000..694284a --- /dev/null +++ b/KiCAD/footprints.pretty/TSSOP50P1180X120-86N.kicad_mod @@ -0,0 +1,100 @@ +(module TSSOP50P1180X120-86N (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference U6 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 44 smd oval (at 5.75 10.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd oval (at 5.75 10 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd oval (at 5.75 9.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 47 smd oval (at 5.75 9 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 48 smd oval (at 5.75 8.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 49 smd oval (at 5.75 8 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 50 smd oval (at 5.75 7.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 51 smd oval (at 5.75 7 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 52 smd oval (at 5.75 6.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 53 smd oval (at 5.75 6 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 54 smd oval (at 5.75 5.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 55 smd oval (at 5.75 5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 56 smd oval (at 5.75 4.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 57 smd oval (at 5.75 4 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 58 smd oval (at 5.75 3.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 59 smd oval (at 5.75 3 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 60 smd oval (at 5.75 2.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 61 smd oval (at 5.75 2 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 62 smd oval (at 5.75 1.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 63 smd oval (at 5.75 1 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 64 smd oval (at 5.75 0.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 65 smd oval (at 5.75 0 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 66 smd oval (at 5.75 -0.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 67 smd oval (at 5.75 -1 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 68 smd oval (at 5.75 -1.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 69 smd oval (at 5.75 -2 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 70 smd oval (at 5.75 -2.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 71 smd oval (at 5.75 -3 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 72 smd oval (at 5.75 -3.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 73 smd oval (at 5.75 -4 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 74 smd oval (at 5.75 -4.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 75 smd oval (at 5.75 -5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 76 smd oval (at 5.75 -5.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 77 smd oval (at 5.75 -6 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 78 smd oval (at 5.75 -6.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 79 smd oval (at 5.75 -7 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 80 smd oval (at 5.75 -7.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 81 smd oval (at 5.75 -8 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 82 smd oval (at 5.75 -8.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 83 smd oval (at 5.75 -9 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 84 smd oval (at 5.75 -9.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 85 smd oval (at 5.75 -10 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 86 smd oval (at 5.75 -10.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd oval (at -5.75 10.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd oval (at -5.75 10 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 41 smd oval (at -5.75 9.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd oval (at -5.75 9 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd oval (at -5.75 8.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd oval (at -5.75 8 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd oval (at -5.75 7.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd oval (at -5.75 7 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd oval (at -5.75 6.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd oval (at -5.75 6 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd oval (at -5.75 5.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd oval (at -5.75 5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at -5.75 4.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd oval (at -5.75 4 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at -5.75 3.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd oval (at -5.75 3 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd oval (at -5.75 2.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd oval (at -5.75 2 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd oval (at -5.75 1.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd oval (at -5.75 1 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd oval (at -5.75 0.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd oval (at -5.75 0 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd oval (at -5.75 -0.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd oval (at -5.75 -1 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd oval (at -5.75 -1.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd oval (at -5.75 -2 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd oval (at -5.75 -2.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd oval (at -5.75 -3 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at -5.75 -3.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd oval (at -5.75 -4 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at -5.75 -4.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd oval (at -5.75 -5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd oval (at -5.75 -5.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at -5.75 -6 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd oval (at -5.75 -6.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at -5.75 -7 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd oval (at -5.75 -7.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd oval (at -5.75 -8 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd oval (at -5.75 -8.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd oval (at -5.75 -9 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd oval (at -5.75 -9.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd oval (at -5.75 -10 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd oval (at -5.75 -10.5 90) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) +) diff --git a/KiCAD/footprints.pretty/USB-MINIB.kicad_mod b/KiCAD/footprints.pretty/USB-MINIB.kicad_mod new file mode 100644 index 0000000..ecbf4a3 --- /dev/null +++ b/KiCAD/footprints.pretty/USB-MINIB.kicad_mod @@ -0,0 +1,30 @@ +(module USB-MINIB (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference CN2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "mini USB type B Connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask)) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/23D50C2B-5C98.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/KiCAD/footprints.pretty/VD_0603.kicad_mod b/KiCAD/footprints.pretty/VD_0603.kicad_mod new file mode 100644 index 0000000..ee9faf1 --- /dev/null +++ b/KiCAD/footprints.pretty/VD_0603.kicad_mod @@ -0,0 +1,16 @@ +(module VD_0603 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference LED18 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) +) diff --git a/KiCAD/footprints.pretty/WE-SHC_36103205_NO_CREAM.kicad_mod b/KiCAD/footprints.pretty/WE-SHC_36103205_NO_CREAM.kicad_mod new file mode 100644 index 0000000..010fbd1 --- /dev/null +++ b/KiCAD/footprints.pretty/WE-SHC_36103205_NO_CREAM.kicad_mod @@ -0,0 +1,25 @@ +(module WE-SHC_36103205_NO_CREAM (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference S1 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror)) + ) + (fp_text value "WE-SHC Shielding cabinet" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -10.25 5.0292 270) (size 2.6162 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -10.25 -2.48 270) (size 2.6162 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 10.2616 -2.48 270) (size 2.6162 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 10.2616 5.0292 270) (size 2.6162 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -3.75 11.5316 270) (size 1.016 2.6162) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -3.75 -8.98 270) (size 1.016 2.6162) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 3.7592 -8.98 270) (size 1.016 2.6162) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 3.7592 11.5316 270) (size 1.016 2.6162) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 9.1186 -8.98 270) (size 1.016 3.302) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -9.1 -8.98 270) (size 1.016 3.302) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -9.1 11.5316 270) (size 1.016 3.302) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 9.1186 11.5316 270) (size 1.016 3.302) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 10.2616 -7.83 270) (size 3.302 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -10.25 -7.83 270) (size 3.302 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -10.25 10.3886 270) (size 3.302 1.016) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 10.2616 10.3886 270) (size 3.302 1.016) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/footprints.pretty/XTAL3215.kicad_mod b/KiCAD/footprints.pretty/XTAL3215.kicad_mod new file mode 100644 index 0000000..8f1fe09 --- /dev/null +++ b/KiCAD/footprints.pretty/XTAL3215.kicad_mod @@ -0,0 +1,11 @@ +(module XTAL3215 (layer F.Cu) (tedit 4289BEAB) + (attr smd) + (fp_text reference X1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 32.768kHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask)) + (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask)) +) diff --git a/KiCAD/fp-info-cache b/KiCAD/fp-info-cache new file mode 100644 index 0000000..573541a --- /dev/null +++ b/KiCAD/fp-info-cache @@ -0,0 +1 @@ +0 diff --git a/KiCAD/fp-lib-table b/KiCAD/fp-lib-table new file mode 100644 index 0000000..366e4e0 --- /dev/null +++ b/KiCAD/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name Cryptech_Alpha_Footprints)(type KiCad)(uri "$(KIPRJMOD)/footprints.pretty")(options "")(descr "")) +) diff --git a/KiCAD/rev02_00.sch b/KiCAD/rev02_00.sch new file mode 100644 index 0000000..3414c52 --- /dev/null +++ b/KiCAD/rev02_00.sch @@ -0,0 +1,26 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 2 27 +Title "rev02_00" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 1500 7500 0 168 ~ 12 +This document contains the electrical schematics for the Crypthech Alpha board.\nThe latest version of these schematics can be found here:\nhttps://wiki.cryptech.is/browser/hardware/eagle/alpha\nFor more information about the Alpha board including functionality, goals\nand block diagram, please see:\nhttps://wiki.cryptech.is/wiki/AlphaBoardStrategy\nFor more information about the Cryptech project, please see:\nhttps://cryptech.is/ +$Comp +L Cryptech_Alpha:OSHW-LOGOL-COPPER LOGO1 +U 1 1 580240DE +P 11840 10320 +F 0 "LOGO1" H 11388 9865 60 0000 L BNN + 1 11840 10320 + 1 0 0 -1 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_01.sch b/KiCAD/rev02_01.sch new file mode 100644 index 0000000..bec5b78 --- /dev/null +++ b/KiCAD/rev02_01.sch @@ -0,0 +1,865 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 3 27 +Title "rev02_01" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 9900 2050 0 84 ~ 12 +15V LDO powered from external 18V\nand supplying stable 15V to noise source +Text Notes 1300 2600 0 126 ~ 12 +Main power input\n18V DC +Text Notes 4850 2900 0 60 ~ 12 +To mitigate component ageing in the avalanche noise circuit,\nthis jumper can be used to decide if FPGA/ARM/None should\nbe allowed to turn off the entropy source\n(default On through pull-up) +Text Notes 12600 3700 0 60 ~ 12 +Max 3 ohm ESR +Text Notes 6100 5900 0 84 ~ 12 +*) Intermediate Regulator: 18V -> 5V +Text Notes 9400 9100 0 60 ~ 12 +*) VCC_5V0 = 0.8V x (1 + 6.3/1.21) = 4.965V\n*) Current sharing not used\n*) SYNC is not used +Text Notes 4900 1900 0 126 ~ 12 +Entropy source power +Text Notes 1400 4200 0 60 ~ 12 +XXX verify symbol +Text Notes 13700 10200 0 84 ~ 12 +Input power +Text Notes 8900 2650 2 60 ~ 12 +R7 +Text Notes 5950 7150 0 60 ~ 12 +R3 +Text Notes 3660 7190 0 60 ~ 12 +C1 +Text Notes 3660 7390 0 60 ~ 12 +10~uF +Text Notes 9660 6890 0 60 ~ 12 +C6 +Text Notes 9660 7090 0 60 ~ 12 +0.047~uF +Text Notes 5060 7190 0 60 ~ 12 +C4 +Text Notes 5060 7390 0 60 ~ 12 +0.047~uF +Text Notes 4060 7190 0 60 ~ 12 +C2 +Text Notes 4060 7390 0 60 ~ 12 +10~uF +Text Notes 4460 7190 0 60 ~ 12 +C3 +Text Notes 4460 7390 0 60 ~ 12 +10~uF +Text Notes 10260 6890 0 60 ~ 12 +C8 +Text Notes 10260 7090 0 60 ~ 12 +47uF +Text Notes 6850 3450 0 60 ~ 12 +2N7002 +Text Notes 6900 3300 0 60 ~ 12 +Q1 +Text Notes 6750 4000 3 60 ~ 12 +R6 +Text Notes 8300 2900 2 60 ~ 12 +JP2 +Text Notes 8350 2930 2 60 ~ 12 +JP1Q +$Comp +L power:GND GND +U 1 1 580240DD +P 2500 3700 +F 0 "GND" H 2500 3700 20 0000 C CNN +F 1 "+GND" H 2500 3630 30 0000 C CNN +F 2 "" H 2500 3700 70 0000 C CNN +F 3 "" H 2500 3700 70 0000 C CNN + 1 2500 3700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_2 +U 1 1 580240DC +P 10600 3800 +F 0 "GND_2" H 10600 3800 20 0000 C CNN +F 1 "+GND" H 10600 3730 30 0000 C CNN +F 2 "" H 10600 3800 70 0000 C CNN +F 3 "" H 10600 3800 70 0000 C CNN + 1 10600 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_3 +U 1 1 580240DB +P 12000 3800 +F 0 "GND_3" H 12000 3800 20 0000 C CNN +F 1 "+GND" H 12000 3730 30 0000 C CNN +F 2 "" H 12000 3800 70 0000 C CNN +F 3 "" H 12000 3800 70 0000 C CNN + 1 12000 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_4 +U 1 1 580240DA +P 12500 3800 +F 0 "GND_4" H 12500 3800 20 0000 C CNN +F 1 "+GND" H 12500 3730 30 0000 C CNN +F 2 "" H 12500 3800 70 0000 C CNN +F 3 "" H 12500 3800 70 0000 C CNN + 1 12500 3800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:PWR_18V PWR_18V +U 1 1 580240D9 +P 2500 3000 +F 0 "PWR_18V" H 2500 3000 20 0000 C CNN +F 1 "+PWR_18V" H 2500 2930 30 0000 C CNN +F 2 "" H 2500 3000 70 0000 C CNN +F 3 "" H 2500 3000 70 0000 C CNN + 1 2500 3000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:PWR_18V PWR_18V_2 +U 1 1 580240D8 +P 10100 2500 +F 0 "PWR_18V_2" H 10100 2500 20 0000 C CNN +F 1 "+PWR_18V" H 10100 2430 30 0000 C CNN +F 2 "" H 10100 2500 70 0000 C CNN +F 3 "" H 10100 2500 70 0000 C CNN + 1 10100 2500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:15V_STABLE 15V_STABLE +U 1 1 580240D7 +P 12800 2500 +F 0 "15V_STABLE" H 12800 2500 20 0000 C CNN +F 1 "+15V_STABLE" H 12800 2430 30 0000 C CNN +F 2 "" H 12800 2500 70 0000 C CNN +F 3 "" H 12800 2500 70 0000 C CNN + 1 12800 2500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_5 +U 1 1 580240D6 +P 7700 8800 +F 0 "GND_5" H 7700 8800 20 0000 C CNN +F 1 "+GND" H 7700 8730 30 0000 C CNN +F 2 "" H 7700 8800 70 0000 C CNN +F 3 "" H 7700 8800 70 0000 C CNN + 1 7700 8800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_6 +U 1 1 580240D5 +P 7900 8800 +F 0 "GND_6" H 7900 8800 20 0000 C CNN +F 1 "+GND" H 7900 8730 30 0000 C CNN +F 2 "" H 7900 8800 70 0000 C CNN +F 3 "" H 7900 8800 70 0000 C CNN + 1 7900 8800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_7 +U 1 1 580240D4 +P 6700 8800 +F 0 "GND_7" H 6700 8800 20 0000 C CNN +F 1 "+GND" H 6700 8730 30 0000 C CNN +F 2 "" H 6700 8800 70 0000 C CNN +F 3 "" H 6700 8800 70 0000 C CNN + 1 6700 8800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_8 +U 1 1 580240D3 +P 5600 7800 +F 0 "GND_8" H 5600 7800 20 0000 C CNN +F 1 "+GND" H 5600 7730 30 0000 C CNN +F 2 "" H 5600 7800 70 0000 C CNN +F 3 "" H 5600 7800 70 0000 C CNN + 1 5600 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_9 +U 1 1 580240D2 +P 5000 7800 +F 0 "GND_9" H 5000 7800 20 0000 C CNN +F 1 "+GND" H 5000 7730 30 0000 C CNN +F 2 "" H 5000 7800 70 0000 C CNN +F 3 "" H 5000 7800 70 0000 C CNN + 1 5000 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_10 +U 1 1 580240D1 +P 4400 7800 +F 0 "GND_10" H 4400 7800 20 0000 C CNN +F 1 "+GND" H 4400 7730 30 0000 C CNN +F 2 "" H 4400 7800 70 0000 C CNN +F 3 "" H 4400 7800 70 0000 C CNN + 1 4400 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_11 +U 1 1 580240D0 +P 4000 7800 +F 0 "GND_11" H 4000 7800 20 0000 C CNN +F 1 "+GND" H 4000 7730 30 0000 C CNN +F 2 "" H 4000 7800 70 0000 C CNN +F 3 "" H 4000 7800 70 0000 C CNN + 1 4000 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_12 +U 1 1 580240CF +P 3600 7800 +F 0 "GND_12" H 3600 7800 20 0000 C CNN +F 1 "+GND" H 3600 7730 30 0000 C CNN +F 2 "" H 3600 7800 70 0000 C CNN +F 3 "" H 3600 7800 70 0000 C CNN + 1 3600 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_13 +U 1 1 580240CE +P 9200 8000 +F 0 "GND_13" H 9200 8000 20 0000 C CNN +F 1 "+GND" H 9200 7930 30 0000 C CNN +F 2 "" H 9200 8000 70 0000 C CNN +F 3 "" H 9200 8000 70 0000 C CNN + 1 9200 8000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_14 +U 1 1 580240CD +P 9600 7300 +F 0 "GND_14" H 9600 7300 20 0000 C CNN +F 1 "+GND" H 9600 7230 30 0000 C CNN +F 2 "" H 9600 7300 70 0000 C CNN +F 3 "" H 9600 7300 70 0000 C CNN + 1 9600 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_15 +U 1 1 580240CC +P 10200 7300 +F 0 "GND_15" H 10200 7300 20 0000 C CNN +F 1 "+GND" H 10200 7230 30 0000 C CNN +F 2 "" H 10200 7300 70 0000 C CNN +F 3 "" H 10200 7300 70 0000 C CNN + 1 10200 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_16 +U 1 1 580240CB +P 10800 7300 +F 0 "GND_16" H 10800 7300 20 0000 C CNN +F 1 "+GND" H 10800 7230 30 0000 C CNN +F 2 "" H 10800 7300 70 0000 C CNN +F 3 "" H 10800 7300 70 0000 C CNN + 1 10800 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_17 +U 1 1 580240CA +P 11400 7300 +F 0 "GND_17" H 11400 7300 20 0000 C CNN +F 1 "+GND" H 11400 7230 30 0000 C CNN +F 2 "" H 11400 7300 70 0000 C CNN +F 3 "" H 11400 7300 70 0000 C CNN + 1 11400 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:PWR_18V PWR_18V_3 +U 1 1 580240C9 +P 3400 6300 +F 0 "PWR_18V_3" H 3400 6300 20 0000 C CNN +F 1 "+PWR_18V" H 3400 6230 30 0000 C CNN +F 2 "" H 3400 6300 70 0000 C CNN +F 3 "" H 3400 6300 70 0000 C CNN + 1 3400 6300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:PWR_18V PWR_18V_4 +U 1 1 580240C8 +P 8700 2500 +F 0 "PWR_18V_4" H 8700 2500 20 0000 C CNN +F 1 "+PWR_18V" H 8700 2430 30 0000 C CNN +F 2 "" H 8700 2500 70 0000 C CNN +F 3 "" H 8700 2500 70 0000 C CNN + 1 8700 2500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_18 +U 1 1 580240C7 +P 6900 4350 +F 0 "GND_18" H 6900 4350 20 0000 C CNN +F 1 "+GND" H 6900 4280 30 0000 C CNN +F 2 "" H 6900 4350 70 0000 C CNN +F 3 "" H 6900 4350 70 0000 C CNN + 1 6900 4350 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_19 +U 1 1 580240C6 +P 7700 4350 +F 0 "GND_19" H 7700 4350 20 0000 C CNN +F 1 "+GND" H 7700 4280 30 0000 C CNN +F 2 "" H 7700 4350 70 0000 C CNN +F 3 "" H 7700 4350 70 0000 C CNN + 1 7700 4350 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_20 +U 1 1 580240C5 +P 10100 3800 +F 0 "GND_20" H 10100 3800 20 0000 C CNN +F 1 "+GND" H 10100 3730 30 0000 C CNN +F 2 "" H 10100 3800 70 0000 C CNN +F 3 "" H 10100 3800 70 0000 C CNN + 1 10100 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 3500 1800 3500 +Wire Wire Line + 2500 3500 2500 3700 +Wire Wire Line + 10700 3400 10600 3400 +Wire Wire Line + 10600 3600 10600 3800 +Wire Wire Line + 10600 3500 10600 3600 +Wire Wire Line + 10600 3400 10600 3500 +Wire Wire Line + 12000 3700 12000 3800 +Wire Wire Line + 12500 3500 12500 3800 +Wire Wire Line + 7700 8400 7700 8800 +Wire Wire Line + 7900 8400 7900 8800 +Wire Wire Line + 6700 8600 6700 8800 +Wire Wire Line + 5600 7700 5600 7800 +Wire Wire Line + 3600 7400 3600 7800 +Wire Wire Line + 4000 7400 4000 7800 +Wire Wire Line + 4400 7400 4400 7800 +Wire Wire Line + 5000 7400 5000 7800 +Wire Wire Line + 9200 7900 9200 8000 +Wire Wire Line + 9600 7100 9600 7300 +Wire Wire Line + 10200 7100 10200 7300 +Wire Wire Line + 10800 7100 10800 7300 +Wire Wire Line + 11400 7100 11400 7300 +Wire Wire Line + 6900 4150 6900 4350 +Wire Wire Line + 7700 3550 7500 3550 +Wire Wire Line + 7700 3550 7700 4350 +Wire Wire Line + 10100 3700 10100 3800 +Wire Wire Line + 2500 3300 1800 3300 +Wire Wire Line + 2500 3000 2500 3300 +Wire Wire Line + 10700 2800 10100 2800 +Wire Wire Line + 10100 2500 10100 2800 +Wire Wire Line + 10100 2800 10100 3400 +Connection ~ 10100 2800 +Wire Wire Line + 5600 6600 5600 6700 +Wire Wire Line + 6900 6600 5600 6600 +Wire Wire Line + 3600 6600 3600 7100 +Wire Wire Line + 4000 6600 3600 6600 +Wire Wire Line + 4400 6600 4000 6600 +Wire Wire Line + 5000 6600 4400 6600 +Wire Wire Line + 5600 6600 5000 6600 +Wire Wire Line + 4000 6600 4000 7100 +Wire Wire Line + 5000 6600 5000 7100 +Wire Wire Line + 4400 6600 4400 7100 +Wire Wire Line + 3600 6600 3400 6600 +Wire Wire Line + 3400 6300 3400 6600 +Connection ~ 5600 6600 +Connection ~ 4000 6600 +Connection ~ 5000 6600 +Connection ~ 3600 6600 +Connection ~ 4400 6600 +Wire Wire Line + 8700 2500 8700 2600 +Wire Wire Line + 12000 3100 11900 3100 +Wire Wire Line + 12000 3400 11900 3400 +Wire Wire Line + 10700 3100 8700 3100 +Wire Wire Line + 8700 3000 8700 3100 +Wire Wire Line + 8700 3100 8450 3100 +Text Label 9000 3100 0 48 ~ +15V_LDO_ENABLE +Connection ~ 8700 3100 +Wire Wire Line + 12000 2800 11900 2800 +Wire Wire Line + 12500 2800 12000 2800 +Wire Wire Line + 12800 2800 12500 2800 +Wire Wire Line + 12500 2800 12500 3200 +Wire Wire Line + 12800 2500 12800 2800 +Connection ~ 12000 2800 +Connection ~ 12500 2800 +Wire Wire Line + 6700 8000 6700 8300 +Wire Wire Line + 6900 8000 6700 8000 +Wire Wire Line + 5900 7200 5600 7200 +Wire Wire Line + 5600 7100 5600 7200 +Wire Wire Line + 5600 7200 5600 7300 +Connection ~ 5600 7200 +Wire Wire Line + 6900 7200 6300 7200 +Wire Wire Line + 9200 7400 8700 7400 +Wire Wire Line + 9200 7200 9200 7400 +Wire Wire Line + 9200 7400 9200 7500 +Connection ~ 9200 7400 +Wire Wire Line + 9200 6600 9200 6800 +Wire Wire Line + 10200 6600 10200 6800 +Wire Wire Line + 10200 6600 9600 6600 +Wire Wire Line + 9600 6600 9200 6600 +Wire Wire Line + 9200 6600 8700 6600 +Wire Wire Line + 10800 6600 10800 6900 +Wire Wire Line + 10800 6600 10200 6600 +Wire Wire Line + 11400 6600 11400 6900 +Wire Wire Line + 11400 6600 10800 6600 +Wire Wire Line + 12300 6600 11400 6600 +Wire Wire Line + 9600 6600 9600 6800 +Text Label 12300 6600 2 48 ~ 0 +VCC_5V0 +Connection ~ 9200 6600 +Connection ~ 10200 6600 +Connection ~ 10800 6600 +Connection ~ 11400 6600 +Connection ~ 9600 6600 +Wire Wire Line + 6900 3550 6700 3550 +Wire Wire Line + 7100 3550 6900 3550 +Wire Wire Line + 6900 3550 6900 3750 +Connection ~ 6900 3550 +Wire Wire Line + 7700 3350 7500 3350 +Wire Wire Line + 7700 3100 7700 3350 +Wire Wire Line + 7850 3100 7700 3100 +Wire Wire Line + 6300 3550 6000 3550 +Text GLabel 5450 3550 0 48 Input ~ 0 +FPGA_ENTROPY_DISABLE +Wire Wire Line + 5450 3550 6000 3550 +Wire Wire Line + 10600 3500 10700 3500 +Wire Wire Line + 10600 3600 10700 3600 +Wire Wire Line + 6900 6600 6900 6700 +Wire Wire Line + 8700 6600 8700 6700 +Text Notes 6760 8390 0 60 ~ 12 +C124 +Text Notes 6800 8600 0 60 ~ 12 +0.47uF +Wire Wire Line + 1800 3500 1800 3400 +Wire Wire Line + 8000 8400 8100 8400 +Wire Wire Line + 7900 8400 8000 8400 +Connection ~ 1800 3500 +Connection ~ 6900 6600 +Connection ~ 7900 8400 +Connection ~ 8000 8400 +Connection ~ 8700 6600 +Connection ~ 10600 3600 +Connection ~ 10600 3500 +$Comp +L Cryptech_Alpha:C-EUC0402 C11 +U 1 1 580240C4 +P 12000 3000 +F 0 "C11" H 11900 3000 60 0000 R TNN +F 1 "0.01uF" H 11900 3100 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11900 3100 60 0001 C CNN +F 3 "" H 11900 3100 60 0000 C CNN + 1 12000 3000 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C6 +U 1 1 580240C3 +P 9600 6900 +F 0 "C6" H 9680 6710 60 0000 L BNN + 1 9600 6900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 9680 6710 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C4 +U 1 1 580240C2 +P 5000 7200 +F 0 "C4" H 5080 7010 60 0000 L BNN + 1 5000 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5080 7010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C2 +U 1 1 580240C1 +P 4000 7200 +F 0 "C2" H 4080 7010 60 0000 L BNN + 1 4000 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 4080 7010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C3 +U 1 1 580240C0 +P 4400 7200 +F 0 "C3" H 4480 7010 60 0000 L BNN + 1 4400 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 4480 7010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C8 +U 1 1 580240BF +P 10200 6900 +F 0 "C8" H 10280 6710 60 0000 L BNN + 1 10200 6900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 10280 6710 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:2N7002 Q1 +U 1 1 580240BE +P 7300 3450 +F 0 "Q1" H 7190 3195 60 0000 L BNN +F 1 "2N7002P,235" H 7100 3600 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 7100 3600 60 0001 C CNN +F 3 "" H 7100 3600 60 0000 C CNN + 1 7300 3450 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R6 +U 1 1 580240BD +P 6900 3950 +F 0 "R6" V 6990 3995 60 0000 L BNN +F 1 "10k" H 6900 3890 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6900 3890 60 0001 C CNN +F 3 "" H 6900 3890 60 0000 C CNN + 1 6900 3950 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R5 +U 1 1 580240BC +P 6500 3550 +F 0 "R5" H 6350 3600 60 0000 L BNN +F 1 "1k" H 6500 3600 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6500 3600 60 0001 C CNN +F 3 "" H 6500 3600 60 0000 C CNN + 1 6500 3550 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:JP1Q JP2 +U 1 1 580240BB +P 8150 3100 +F 0 "JP2" V 7945 3330 60 0000 R TNN + 1 8150 3100 + 0 -1 -1 0 +F 2 "Cryptech_Alpha_Footprints:PLS-2" H 7945 3330 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C7 +U 1 1 580240BA +P 10100 3500 +F 0 "C7" H 10200 3400 60 0000 L BNN +F 1 "4.7uF" H 10200 3300 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 10200 3300 60 0001 C CNN +F 3 "" H 10200 3300 60 0000 C CNN + 1 10100 3500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C13 +U 1 1 580240B9 +P 12500 3300 +F 0 "C13" H 12600 3200 60 0000 L BNN +F 1 "4.7uF" H 12600 3100 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 12600 3100 60 0001 C CNN +F 3 "" H 12600 3100 60 0000 C CNN + 1 12500 3300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:LT3060ITS8-15 U2 +U 1 1 580240B8 +P 11300 3100 +F 0 "U2" H 10890 3510 60 0000 L BNN +F 1 "LT3060ITS8-15#TRMPBF" H 10890 2390 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:TSOT-8-23" H 10890 2390 60 0001 C CNN +F 3 "" H 10890 2390 60 0000 C CNN + 1 11300 3100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:LMZ13608 U1 +U 1 1 580240B7 +P 7800 7300 +F 0 "U1" H 7090 8210 60 0000 L BNN +F 1 "LMZ13608TZ*" H 7300 8200 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:NDY" H 7300 8200 60 0001 C CNN +F 3 "" H 7300 8200 60 0000 C CNN + 1 7800 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C5 +U 1 1 580240B6 +P 6700 8400 +F 0 "C5" H 6800 8350 60 0000 L BNN + 1 6700 8400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6800 8350 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C12 +U 1 1 580240B5 +P 12000 3600 +F 0 "C12" H 11900 3600 60 0000 R TNN +F 1 "0.01uF" H 11900 3700 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11900 3700 60 0001 C CNN +F 3 "" H 11900 3700 60 0000 C CNN + 1 12000 3600 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:POWER_JACKSMD JP1 +U 1 1 580240B4 +P 1700 3600 +F 0 "JP1" H 1290 3930 60 0000 L BNN +F 1 "694106301002" H 1290 3570 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:694106301002" H 1290 3570 60 0001 C CNN +F 3 "" H 1290 3570 60 0000 C CNN + 1 1700 3600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:CP_E-035X080 C9 +U 1 1 580240B3 +P 10800 7000 +F 0 "C9" V 10825 6875 60 0000 R TNN +F 1 "330uF" V 10710 6907 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_D" H 10710 6907 60 0001 C CNN +F 3 "" H 10710 6907 60 0000 C CNN + 1 10800 7000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:CP_E-035X080 C10 +U 1 1 580240B2 +P 11400 7000 +F 0 "C10" V 11425 6875 60 0000 R TNN +F 1 "330uF" V 11310 6907 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_D" H 11310 6907 60 0001 C CNN +F 3 "" H 11310 6907 60 0000 C CNN + 1 11400 7000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R7 +U 1 1 580240B1 +P 8700 2800 +F 0 "R7" V 8790 2845 60 0000 L BNN +F 1 "10k" V 8750 2900 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8750 2900 60 0001 C CNN +F 3 "" H 8750 2900 60 0000 C CNN + 1 8700 2800 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R3 +U 1 1 580240B0 +P 6100 7200 +F 0 "R3" H 5990 7055 60 0000 L BNN +F 1 "100" H 6100 7250 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6100 7250 60 0001 C CNN +F 3 "" H 6100 7250 60 0000 C CNN + 1 6100 7200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R2 +U 1 1 580240AF +P 5600 7500 +F 0 "R2" V 5700 7380 60 0000 R TNN +F 1 "4.64k" V 5600 7400 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5600 7400 60 0001 C CNN +F 3 "" H 5600 7400 60 0000 C CNN + 1 5600 7500 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R1 +U 1 1 580240AE +P 5600 6900 +F 0 "R1" V 5700 6800 60 0000 R TNN +F 1 "56k" V 5600 6800 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5600 6800 60 0001 C CNN +F 3 "" H 5600 6800 60 0000 C CNN + 1 5600 6900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C1 +U 1 1 580240AD +P 3600 7200 +F 0 "C1" H 3680 7010 60 0000 L BNN + 1 3600 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 3680 7010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R8 +U 1 1 580240AC +P 9200 7000 +F 0 "R8" H 9050 7059 60 0000 R TNN +F 1 "6.3k" H 9210 7070 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9210 7070 60 0001 C CNN +F 3 "" H 9210 7070 60 0000 C CNN + 1 9200 7000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R9 +U 1 1 580240AB +P 9200 7700 +F 0 "R9" H 9050 7759 60 0000 R TNN +F 1 "1.21k" H 9200 7770 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9200 7770 60 0001 C CNN +F 3 "" H 9200 7770 60 0000 C CNN + 1 9200 7700 + 0 -1 -1 0 +$EndComp +NoConn ~ 8700 8000 +Wire Wire Line + 12300 6600 12300 6450 +$Comp +L Cryptech_Alpha:VCC_5V0 #PWR? +U 1 1 5AF35ED8 +P 12300 6450 +F 0 "#PWR?" H 12300 6300 50 0001 C CNN +F 1 "VCC_5V0" H 12315 6623 50 0000 C CNN +F 2 "" H 12300 6450 60 0000 C CNN +F 3 "" H 12300 6450 60 0000 C CNN + 1 12300 6450 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB973B +P 2200 3300 +F 0 "#FLG?" H 2200 3375 50 0001 C CNN +F 1 "PWR_FLAG" H 2200 3474 50 0000 C CNN +F 2 "" H 2200 3300 50 0001 C CNN +F 3 "~" H 2200 3300 50 0001 C CNN + 1 2200 3300 + 1 0 0 -1 +$EndComp +Connection ~ 2200 3300 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB98AE +P 2200 3500 +F 0 "#FLG?" H 2200 3575 50 0001 C CNN +F 1 "PWR_FLAG" H 2200 3673 50 0000 C CNN +F 2 "" H 2200 3500 50 0001 C CNN +F 3 "~" H 2200 3500 50 0001 C CNN + 1 2200 3500 + -1 0 0 1 +$EndComp +Connection ~ 2200 3500 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_02.sch b/KiCAD/rev02_02.sch new file mode 100644 index 0000000..66702b9 --- /dev/null +++ b/KiCAD/rev02_02.sch @@ -0,0 +1,388 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 4 27 +Title "rev02_02" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 11600 3700 0 126 ~ 12 +Digitizer +Text Notes 3200 3700 0 126 ~ 12 +Noise generator +Text Notes 4200 6410 0 60 ~ 12 +Noisy diode +Text Notes 6800 3700 0 126 ~ 12 +Amplifier +Text Notes 3200 7600 0 60 ~ 12 +AGND is connected to GND on the board using polygons\n(found no other good way) - not visible in schematics. +Text Notes 9400 7650 0 60 ~ 12 +This whole sheets circuitry should be as shielded as possible.\nSolid isolated ground plane and internal planes connected\nto the rest of the board at a single point is expected. +Text Notes 13690 10220 0 84 ~ 12 +Noise source +Text Notes 11980 4510 0 60 ~ 12 +U3 +Text Notes 11790 5790 0 60 ~ 12 +MC74HC1G14DTT1G +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3 +U 1 1 580240AA +P 11400 4100 +F 0 "VCCO_3V3" H 11400 4100 20 0000 C CNN +F 1 "+VCCO_3V3" H 11400 4030 30 0000 C CNN +F 2 "" H 11400 4100 70 0000 C CNN +F 3 "" H 11400 4100 70 0000 C CNN + 1 11400 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_21 +U 1 1 580240A9 +P 5050 6550 +F 0 "GND_21" H 5050 6550 20 0000 C CNN +F 1 "+GND" H 5050 6480 30 0000 C CNN +F 2 "" H 5050 6550 70 0000 C CNN +F 3 "" H 5050 6550 70 0000 C CNN + 1 5050 6550 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_2 +U 1 1 580240A8 +P 8800 4100 +F 0 "VCCO_3V3_2" H 8800 4100 20 0000 C CNN +F 1 "+VCCO_3V3" H 8800 4030 30 0000 C CNN +F 2 "" H 8800 4100 70 0000 C CNN +F 3 "" H 8800 4100 70 0000 C CNN + 1 8800 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:15V_STABLE 15V_STABLE_2 +U 1 1 580240A7 +P 5050 4350 +F 0 "15V_STABLE_2" H 5050 4350 20 0000 C CNN +F 1 "+15V_STABLE" H 5050 4280 30 0000 C CNN +F 2 "" H 5050 4350 70 0000 C CNN +F 3 "" H 5050 4350 70 0000 C CNN + 1 5050 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11500 4800 11400 4800 +Wire Wire Line + 11400 4100 11400 4800 +Wire Wire Line + 11100 4800 11100 5100 +Wire Wire Line + 11400 4800 11100 4800 +Connection ~ 11400 4800 +Wire Wire Line + 8800 4100 8800 4200 +Wire Wire Line + 11500 5000 10300 5000 +Text Label 10300 5000 0 48 ~ +AMPLIFIED +Wire Wire Line + 10050 5000 9300 5000 +Wire Wire Line + 8800 4600 8800 4700 +Wire Wire Line + 8800 4700 8800 5000 +Wire Wire Line + 8800 5000 8800 5200 +Wire Wire Line + 9300 5000 8800 5000 +Wire Wire Line + 8800 5000 8700 5000 +Wire Wire Line + 8800 4700 8600 4700 +Wire Wire Line + 9300 4900 9300 5000 +Text Label 10050 5000 2 48 ~ 0 +AMPLIFIED +Connection ~ 8800 5000 +Connection ~ 8800 5000 +Connection ~ 8800 4700 +Connection ~ 9300 5000 +Wire Wire Line + 13400 4800 12900 4800 +Text GLabel 13400 4800 2 48 Output ~ 0 +DIGITIZED_NOISE +Wire Wire Line + 11500 5400 11400 5400 +Wire Wire Line + 11400 5400 11400 5800 +Wire Wire Line + 11400 5800 11400 5900 +Wire Wire Line + 11100 5400 11100 5800 +Wire Wire Line + 11400 5800 11100 5800 +Connection ~ 11400 5800 +Wire Wire Line + 8800 5600 8800 5700 +Wire Wire Line + 4850 6000 4450 6000 +Text Label 4500 6000 0 48 ~ +NOISE_OUT +Wire Wire Line + 3950 5400 3950 6200 +Wire Wire Line + 4250 5400 3950 5400 +Wire Wire Line + 4450 5400 4250 5400 +Wire Wire Line + 4250 5400 4250 5800 +Connection ~ 4250 5400 +Text Label 3950 5400 0 48 ~ +NOISE_IN +Wire Wire Line + 5050 5400 4850 5400 +Wire Wire Line + 5050 5400 5050 5800 +Wire Wire Line + 5050 5300 5050 5400 +Wire Wire Line + 5350 5400 5050 5400 +Wire Wire Line + 6400 5400 5350 5400 +Wire Wire Line + 5350 5300 5350 5400 +Text Label 6400 5400 2 48 ~ 0 +RAW_NOISE +Connection ~ 5050 5400 +Connection ~ 5350 5400 +Wire Wire Line + 7700 5400 6750 5400 +Text Label 6750 5400 0 48 ~ +RAW_NOISE +Wire Wire Line + 8400 4700 8100 4700 +Wire Wire Line + 8100 5400 8000 5400 +Wire Wire Line + 8100 5000 8100 5400 +Wire Wire Line + 8300 5000 8100 5000 +Wire Wire Line + 8600 5400 8100 5400 +Wire Wire Line + 8100 4700 8100 5000 +Connection ~ 8100 5400 +Connection ~ 8100 5000 +Wire Wire Line + 5050 6200 5050 6550 +Wire Wire Line + 3950 6500 3950 6550 +Wire Wire Line + 5050 6550 3950 6550 +Connection ~ 5050 6550 +Wire Wire Line + 5050 4350 5050 4900 +Wire Wire Line + 3150 4950 3200 4950 +Wire Wire Line + 3150 5750 3150 4950 +$Comp +L power:GND GND_22 +U 1 1 580240A6 +P 3150 5750 +F 0 "GND_22" H 3150 5750 20 0000 C CNN +F 1 "+GND" H 3150 5680 30 0000 C CNN +F 2 "" H 3150 5750 70 0000 C CNN +F 3 "" H 3150 5750 70 0000 C CNN + 1 3150 5750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_23 +U 1 1 580240A5 +P 8800 5700 +F 0 "GND_23" H 8800 5700 20 0000 C CNN +F 1 "+GND" H 8800 5630 30 0000 C CNN +F 2 "" H 8800 5700 70 0000 C CNN +F 3 "" H 8800 5700 70 0000 C CNN + 1 8800 5700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_24 +U 1 1 580240A4 +P 11400 5900 +F 0 "GND_24" H 11400 5900 20 0000 C CNN +F 1 "+GND" H 11400 5830 30 0000 C CNN +F 2 "" H 11400 5900 70 0000 C CNN +F 3 "" H 11400 5900 70 0000 C CNN + 1 11400 5900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C16 +U 1 1 580240A3 +P 11100 5300 +F 0 "C16" H 11500 5260 60 0000 R TNN +F 1 "0.1uF" H 11510 5350 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11510 5350 60 0001 C CNN +F 3 "" H 11510 5350 60 0000 C CNN + 1 11100 5300 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:WE-SHC S1 +U 1 1 580240A2 +P 3600 5050 +F 0 "S1" H 3300 5500 60 0000 L BNN +F 1 "SHIELDING CABINET" H 3600 5450 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:WE-SHC_36103205_NO_CREAM" H 3600 5450 60 0001 C CNN +F 3 "" H 3600 5450 60 0000 C CNN + 1 3600 5050 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:BC818*SMD Q2 +U 1 1 580240A1 +P 4350 6000 +F 0 "Q2" H 4420 5680 60 0000 R TNN +F 1 "BC818-40LT1G" H 4420 5780 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 4420 5780 60 0001 C CNN +F 3 "" H 4420 5780 60 0000 C CNN + 1 4350 6000 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:BC818*SMD T1 +U 1 1 580240A0 +P 4950 6000 +F 0 "T1" H 5200 6250 60 0000 R TNN +F 1 "BC847BLT3G" H 5620 6150 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 5620 6150 60 0001 C CNN +F 3 "" H 5620 6150 60 0000 C CNN + 1 4950 6000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:BC818*SMD T2 +U 1 1 5802409F +P 8700 5400 +F 0 "T2" H 8950 5650 60 0000 R TNN +F 1 "BC847BLT3G" H 9370 5550 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 9370 5550 60 0001 C CNN +F 3 "" H 9370 5550 60 0000 C CNN + 1 8700 5400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:TPB1,27 TP1 +U 1 1 5802409E +P 5350 5200 +F 0 "TP1" H 5250 4900 60 0000 L BNN + 1 5350 5200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:B1,27" H 5250 4900 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:TPB1,27 TP2 +U 1 1 5802409D +P 9300 4800 +F 0 "TP2" H 9200 4500 60 0000 L BNN + 1 9300 4800 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:B1,27" H 9200 4500 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:MC74HC1G14DTT1G U3 +U 1 1 5802409C +P 12200 5000 +F 0 "U3" H 11670 4270 60 0000 L BNN + 1 12200 5000 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:SOT-23-5" H 11670 4270 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C14 +U 1 1 5802409B +P 3950 6400 +F 0 "C14" H 4400 6300 60 0000 R TNN +F 1 "0.1uF" H 4410 6420 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4410 6420 60 0001 C CNN +F 3 "" H 4410 6420 60 0000 C CNN + 1 3950 6400 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R10 +U 1 1 5802409A +P 4650 5400 +F 0 "R10" H 4797 5270 60 0000 R TNN +F 1 "470" H 4800 5350 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4800 5350 60 0001 C CNN +F 3 "" H 4800 5350 60 0000 C CNN + 1 4650 5400 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R11 +U 1 1 58024099 +P 5050 5100 +F 0 "R11" V 4950 5250 60 0000 L BNN +F 1 "1k" V 5060 5240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5060 5240 60 0001 C CNN +F 3 "" H 5060 5240 60 0000 C CNN + 1 5050 5100 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C15 +U 1 1 58024098 +P 7800 5400 +F 0 "C15" V 7600 5500 60 0000 R TNN +F 1 "0.1uF" V 7510 5500 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7510 5500 60 0001 C CNN +F 3 "" H 7510 5500 60 0000 C CNN + 1 7800 5400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R12 +U 1 1 58024097 +P 8500 5000 +F 0 "R12" H 8270 4850 60 0000 L BNN +F 1 "10k" H 8470 4850 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8470 4850 60 0001 C CNN +F 3 "" H 8470 4850 60 0000 C CNN + 1 8500 5000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R13 +U 1 1 58024096 +P 8800 4400 +F 0 "R13" V 8800 4300 60 0000 R TNN +F 1 "1k" V 8710 4310 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8710 4310 60 0001 C CNN +F 3 "" H 8710 4310 60 0000 C CNN + 1 8800 4400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:BAT54 D1 +U 1 1 58024095 +P 8500 4700 +F 0 "D1" H 8410 4775 60 0000 L BNN +F 1 "BAT54LT1G" H 8270 4530 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 8270 4530 60 0001 C CNN +F 3 "" H 8270 4530 60 0000 C CNN + 1 8500 4700 + 1 0 0 -1 +$EndComp +NoConn ~ 11500 5200 +NoConn ~ 4250 6200 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_03.sch b/KiCAD/rev02_03.sch new file mode 100644 index 0000000..f52f21f --- /dev/null +++ b/KiCAD/rev02_03.sch @@ -0,0 +1,489 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 5 27 +Title "rev02_03" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6640 6200 0 60 ~ 12 +ST 4488 §5.1\nBOOT0 to GND boots\nMain Flash Memory +Text Notes 2500 3980 0 60 ~ 12 +ST AN4488 §4.1.2\nsuggests 25 MHz for good\nEthernet, USB OTG and I2C +Text Notes 12400 3200 0 60 ~ 12 +SWD program/debug +Text Notes 13130 4670 0 60 ~ 12 +ST AN4488 §2.3.3\nReset circuit not needed,\nbut pull-down cap\nrecommended. +Text Notes 5140 4340 0 60 ~ 12 +PDR_ON high enables\ninternal power regulator +Text Notes 2490 4280 0 60 ~ 12 +CL 10pF +Text Notes 2000 2300 0 126 ~ 12 +Basic configuration, STM32 +Text Notes 13670 10230 0 84 ~ 12 +ARM configuration +Text Notes 6560 5960 0 60 ~ 12 +R15 +Text Notes 2460 5080 0 60 ~ 12 +R14 +Text Notes 3100 4550 0 60 ~ 12 +Q3 +Text Notes 3050 4900 0 60 ~ 12 +XTAL-4-3225 +Text Notes 3100 5000 0 60 ~ 12 +Gnd +$Comp +L power:GND GND_25 +U 1 1 58024094 +P 2400 5100 +F 0 "GND_25" H 2400 5100 20 0000 C CNN +F 1 "+GND" H 2400 5030 30 0000 C CNN +F 2 "" H 2400 5100 70 0000 C CNN +F 3 "" H 2400 5100 70 0000 C CNN + 1 2400 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_26 +U 1 1 58024093 +P 4000 5100 +F 0 "GND_26" H 4000 5100 20 0000 C CNN +F 1 "+GND" H 4000 5030 30 0000 C CNN +F 2 "" H 4000 5100 70 0000 C CNN +F 3 "" H 4000 5100 70 0000 C CNN + 1 4000 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_27 +U 1 1 58024092 +P 6440 6300 +F 0 "GND_27" H 6440 6300 20 0000 C CNN +F 1 "+GND" H 6440 6230 30 0000 C CNN +F 2 "" H 6440 6300 70 0000 C CNN +F 3 "" H 6440 6300 70 0000 C CNN + 1 6440 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_28 +U 1 1 58024091 +P 12860 4800 +F 0 "GND_28" H 12860 4800 20 0000 C CNN +F 1 "+GND" H 12860 4730 30 0000 C CNN +F 2 "" H 12860 4800 70 0000 C CNN +F 3 "" H 12860 4800 70 0000 C CNN + 1 12860 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_29 +U 1 1 58024090 +P 12100 4800 +F 0 "GND_29" H 12100 4800 20 0000 C CNN +F 1 "+GND" H 12100 4730 30 0000 C CNN +F 2 "" H 12100 4800 70 0000 C CNN +F 3 "" H 12100 4800 70 0000 C CNN + 1 12100 4800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_3 +U 1 1 5802408F +P 11800 3500 +F 0 "VCCO_3V3_3" H 11800 3500 20 0000 C CNN +F 1 "+VCCO_3V3" H 11800 3430 30 0000 C CNN +F 2 "" H 11800 3500 70 0000 C CNN +F 3 "" H 11800 3500 70 0000 C CNN + 1 11800 3500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_4 +U 1 1 5802408E +P 6500 3600 +F 0 "VCCO_3V3_4" H 6500 3600 20 0000 C CNN +F 1 "+VCCO_3V3" H 6500 3530 30 0000 C CNN +F 2 "" H 6500 3600 70 0000 C CNN +F 3 "" H 6500 3600 70 0000 C CNN + 1 6500 3600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_30 +U 1 1 5802408D +P 13700 6900 +F 0 "GND_30" H 13700 6900 20 0000 C CNN +F 1 "+GND" H 13700 6830 30 0000 C CNN +F 2 "" H 13700 6900 70 0000 C CNN +F 3 "" H 13700 6900 70 0000 C CNN + 1 13700 6900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_31 +U 1 1 5802408C +P 3000 5100 +F 0 "GND_31" H 3000 5100 20 0000 C CNN +F 1 "+GND" H 3000 5030 30 0000 C CNN +F 2 "" H 3000 5100 70 0000 C CNN +F 3 "" H 3000 5100 70 0000 C CNN + 1 3000 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_32 +U 1 1 5802408B +P 3400 5100 +F 0 "GND_32" H 3400 5100 20 0000 C CNN +F 1 "+GND" H 3400 5030 30 0000 C CNN +F 2 "" H 3400 5100 70 0000 C CNN +F 3 "" H 3400 5100 70 0000 C CNN + 1 3400 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_33 +U 1 1 5802408A +P 11800 4800 +F 0 "GND_33" H 11800 4800 20 0000 C CNN +F 1 "+GND" H 11800 4730 30 0000 C CNN +F 2 "" H 11800 4800 70 0000 C CNN +F 3 "" H 11800 4800 70 0000 C CNN + 1 11800 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 5000 2400 5100 +Wire Wire Line + 4000 5000 4000 5100 +Wire Wire Line + 6440 6200 6440 6300 +Wire Wire Line + 12100 4030 12100 4800 +Wire Wire Line + 13700 6500 13600 6500 +Wire Wire Line + 13700 6500 13700 6600 +Wire Wire Line + 13700 6600 13400 6600 +Wire Wire Line + 13700 6600 13700 6700 +Wire Wire Line + 13700 6700 13600 6700 +Wire Wire Line + 13700 6800 13400 6800 +Wire Wire Line + 13700 6700 13700 6800 +Wire Wire Line + 13700 6800 13700 6900 +Wire Wire Line + 3000 5000 3000 5100 +Wire Wire Line + 3400 5000 3400 5100 +Wire Wire Line + 11800 4300 11800 4800 +Wire Wire Line + 11800 3500 11800 3800 +Wire Wire Line + 11800 3830 11800 4000 +Wire Wire Line + 11800 3800 11800 3830 +Wire Wire Line + 6800 4300 6500 4300 +Wire Wire Line + 6500 3600 6500 4300 +Wire Wire Line + 6800 4500 6500 4500 +Wire Wire Line + 6500 4300 6500 4500 +Wire Wire Line + 3700 4700 3400 4700 +Wire Wire Line + 3700 4700 3700 5800 +Wire Wire Line + 4000 4700 3700 4700 +Text Label 3700 5800 1 48 ~ +OSC_OUT +Wire Wire Line + 6800 5000 6420 5000 +Text Label 6420 5000 0 48 ~ +OSC_OUT +Wire Wire Line + 2700 5300 2700 5800 +Text Label 2700 5800 1 48 ~ +OSC_IN +Wire Wire Line + 6800 4900 6420 4900 +Text Label 6420 4900 0 48 ~ +OSC_IN +Wire Wire Line + 13040 4130 12760 4130 +Text Label 12760 4130 0 48 ~ +SWDIO +Wire Wire Line + 9400 4800 9100 4800 +Text Label 9400 4800 0 48 ~ +SWDIO +Wire Wire Line + 13040 3930 12760 3930 +Text Label 12760 3930 0 48 ~ +SWDCLK +Wire Wire Line + 9400 4700 9100 4700 +Text Label 9400 4700 0 48 ~ +SWDCLK +Text Label 12760 4230 0 48 ~ +NRST +Wire Wire Line + 9400 4600 9100 4600 +Text Label 9400 4600 0 48 ~ +NRST +Wire Wire Line + 6800 5600 6440 5600 +Wire Wire Line + 6440 5600 6440 5800 +Text Label 6440 5600 0 48 ~ +BOOT0 +Wire Wire Line + 3000 4700 2700 4700 +Wire Wire Line + 2700 4700 2400 4700 +Wire Wire Line + 2700 4700 2700 4900 +Wire Wire Line + 12600 6500 11960 6500 +Text GLabel 11960 6500 0 48 Input ~ 0 +ARM_LED1 +Wire Wire Line + 12290 6600 11960 6600 +Text GLabel 11960 6600 0 48 Input ~ 0 +ARM_LED2 +Wire Wire Line + 12200 6700 11950 6700 +Text GLabel 11950 6700 0 48 Input ~ 0 +ARM_LED3 +Wire Wire Line + 12290 6800 11950 6800 +Text GLabel 11950 6800 0 48 Input ~ 0 +ARM_LED4 +Wire Wire Line + 13300 6500 13000 6500 +Wire Wire Line + 13100 6600 13000 6600 +Wire Wire Line + 13300 6700 13000 6700 +Wire Wire Line + 13100 6800 12690 6800 +Wire Wire Line + 12860 4230 13040 4230 +Wire Wire Line + 12760 4230 12860 4230 +Wire Wire Line + 12860 4230 12860 4500 +Wire Wire Line + 12100 4030 13040 4030 +Wire Wire Line + 13040 3830 11800 3830 +Wire Wire Line + 13000 6600 12690 6600 +Wire Wire Line + 12600 6700 12200 6700 +Connection ~ 11800 3830 +Connection ~ 12860 4230 +$Comp +L Cryptech_Alpha:C-EUC0402 C18 +U 1 1 58024089 +P 4000 4900 +F 0 "C18" H 3900 4800 60 0000 R TNN +F 1 "5pF" H 3880 4890 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3880 4890 60 0001 C CNN +F 3 "" H 3880 4890 60 0000 C CNN + 1 4000 4900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:XTAL-4-3225 Q3 +U 1 1 58024088 +P 3200 4700 +F 0 "Q3" H 3090 4270 60 0000 L BNN +F 1 "ABM8G-25.000MHZ-4Y-T3" H 2730 4930 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5" H 2730 4930 60 0001 C CNN +F 3 "" H 2730 4930 60 0000 C CNN + 1 3200 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C19 +U 1 1 58024087 +P 11800 4100 +F 0 "C19" H 11350 4150 60 0000 L BNN +F 1 "0.1uF" H 11340 4050 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11340 4050 60 0001 C CNN +F 3 "" H 11340 4050 60 0000 C CNN + 1 11800 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:STM32F429BIT6_2 U4 +U 1 1 58024086 +P 8000 4900 +F 0 "U4" H 6890 3890 60 0000 L BNN + 1 8000 4900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N" H 6890 3890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:STM32-SWD J1 +U 1 1 58024085 +P 13440 4130 +F 0 "J1" H 13588 3700 60 0000 R TNN + 1 13440 4130 + -1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:PLS-6" H 13588 3700 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R93 +U 1 1 58024084 +P 12800 6500 +F 0 "R93" H 12890 6320 60 0000 R TNN +F 1 "330" H 12900 6410 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 12900 6410 60 0001 C CNN +F 3 "" H 12900 6410 60 0000 C CNN + 1 12800 6500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R92 +U 1 1 58024083 +P 12490 6600 +F 0 "R92" H 12620 6320 60 0000 R TNN +F 1 "330" H 12630 6410 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 12630 6410 60 0001 C CNN +F 3 "" H 12630 6410 60 0000 C CNN + 1 12490 6600 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R16 +U 1 1 58024082 +P 12800 6700 +F 0 "R16" H 12480 6310 60 0000 R TNN +F 1 "330" H 12490 6400 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 12490 6400 60 0001 C CNN +F 3 "" H 12490 6400 60 0000 C CNN + 1 12800 6700 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R94 +U 1 1 58024081 +P 12490 6800 +F 0 "R94" H 12580 6970 60 0000 R TNN +F 1 "330" H 12590 7060 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 12590 7060 60 0001 C CNN +F 3 "" H 12590 7060 60 0000 C CNN + 1 12490 6800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C17 +U 1 1 58024080 +P 2400 4900 +F 0 "C17" H 2800 4800 60 0000 R TNN +F 1 "5pF" H 2800 4900 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2800 4900 60 0001 C CNN +F 3 "" H 2800 4900 60 0000 C CNN + 1 2400 4900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R15 +U 1 1 5802407F +P 6440 6000 +F 0 "R15" V 6350 5955 60 0000 R TNN +F 1 "10k" V 6380 5880 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6380 5880 60 0001 C CNN +F 3 "" H 6380 5880 60 0000 C CNN + 1 6440 6000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C20 +U 1 1 5802407E +P 12860 4600 +F 0 "C20" H 12410 4650 60 0000 L BNN +F 1 "0.1uF" H 12410 4550 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12410 4550 60 0001 C CNN +F 3 "" H 12410 4550 60 0000 C CNN + 1 12860 4600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R14 +U 1 1 5802407D +P 2700 5100 +F 0 "R14" V 2610 5055 60 0000 R TNN +F 1 "0" V 2640 5230 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2640 5230 60 0001 C CNN +F 3 "" H 2640 5230 60 0000 C CNN + 1 2700 5100 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED3 +U 1 1 5802407C +P 13400 6500 +F 0 "LED3" V 13370 6067 60 0000 R TNN +F 1 "LTST-C193TBKT-5A" V 13350 5460 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13350 5460 60 0001 C CNN +F 3 "" H 13350 5460 60 0000 C CNN + 1 13400 6500 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED1 +U 1 1 5802407B +P 13200 6600 +F 0 "LED1" V 13170 5967 60 0000 R TNN +F 1 "LTST-C191KGKT" V 13160 5360 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13160 5360 60 0001 C CNN +F 3 "" H 13160 5360 60 0000 C CNN + 1 13200 6600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED4 +U 1 1 5802407A +P 13400 6700 +F 0 "LED4" V 13370 6267 60 0000 R TNN +F 1 "LTST-C191KSKT" V 13355 5666 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13355 5666 60 0001 C CNN +F 3 "" H 13355 5666 60 0000 C CNN + 1 13400 6700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED2 +U 1 1 58024079 +P 13200 6800 +F 0 "LED2" V 13170 6167 60 0000 R TNN +F 1 "LTST-C191KRKT" V 13160 5560 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13160 5560 60 0001 C CNN +F 3 "" H 13160 5560 60 0000 C CNN + 1 13200 6800 + 0 -1 -1 0 +$EndComp +NoConn ~ 9100 5100 +NoConn ~ 9100 5200 +NoConn ~ 9100 5300 +NoConn ~ 6800 5400 +NoConn ~ 13040 4330 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_04.sch b/KiCAD/rev02_04.sch new file mode 100644 index 0000000..2845096 --- /dev/null +++ b/KiCAD/rev02_04.sch @@ -0,0 +1,752 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 6 27 +Title "rev02_04" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 12530 4700 0 60 ~ 12 +ST AN8844 §2.2\nOne bypass capacitor for every VDD.\nUse 0.1 uF X7R 10V. +Text Notes 9350 4850 0 60 ~ 12 +ST AN8844 §2.2\nOne 10uF bypass cap for the package.\n(two used for extra comfort) +Text Notes 6400 4850 0 60 ~ 12 +2*2*2.2uF LowESR or\n2*1*4.7uF LowESR\n< 1 ohm\n(ST AN4488 §2.2) +Text Notes 1900 2100 0 126 ~ 12 +Power and bypass capacitors, STM32 +Text Notes 13930 10220 0 84 ~ 12 +ARM power +$Comp +L power:GND GND_34 +U 1 1 58024078 +P 10100 6300 +F 0 "GND_34" H 10100 6300 20 0000 C CNN +F 1 "+GND" H 10100 6230 30 0000 C CNN +F 2 "" H 10100 6300 70 0000 C CNN +F 3 "" H 10100 6300 70 0000 C CNN + 1 10100 6300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_5 +U 1 1 58024077 +P 10100 5400 +F 0 "VCCO_3V3_5" H 10100 5400 20 0000 C CNN +F 1 "+VCCO_3V3" H 10100 5330 30 0000 C CNN +F 2 "" H 10100 5400 70 0000 C CNN +F 3 "" H 10100 5400 70 0000 C CNN + 1 10100 5400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_6 +U 1 1 58024076 +P 12200 4850 +F 0 "VCCO_3V3_6" H 12200 4850 20 0000 C CNN +F 1 "+VCCO_3V3" H 12200 4780 30 0000 C CNN +F 2 "" H 12200 4850 70 0000 C CNN +F 3 "" H 12200 4850 70 0000 C CNN + 1 12200 4850 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_35 +U 1 1 58024075 +P 12200 6300 +F 0 "GND_35" H 12200 6300 20 0000 C CNN +F 1 "+GND" H 12200 6230 30 0000 C CNN +F 2 "" H 12200 6300 70 0000 C CNN +F 3 "" H 12200 6300 70 0000 C CNN + 1 12200 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_36 +U 1 1 58024074 +P 2400 7200 +F 0 "GND_36" H 2400 7200 20 0000 C CNN +F 1 "+GND" H 2400 7130 30 0000 C CNN +F 2 "" H 2400 7200 70 0000 C CNN +F 3 "" H 2400 7200 70 0000 C CNN + 1 2400 7200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_7 +U 1 1 58024073 +P 2300 4250 +F 0 "VCCO_3V3_7" H 2300 4250 20 0000 C CNN +F 1 "+VCCO_3V3" H 2300 4180 30 0000 C CNN +F 2 "" H 2300 4250 70 0000 C CNN +F 3 "" H 2300 4250 70 0000 C CNN + 1 2300 4250 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_37 +U 1 1 58024072 +P 4400 7200 +F 0 "GND_37" H 4400 7200 20 0000 C CNN +F 1 "+GND" H 4400 7130 30 0000 C CNN +F 2 "" H 4400 7200 70 0000 C CNN +F 3 "" H 4400 7200 70 0000 C CNN + 1 4400 7200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_38 +U 1 1 58024071 +P 7600 6200 +F 0 "GND_38" H 7600 6200 20 0000 C CNN +F 1 "+GND" H 7600 6130 30 0000 C CNN +F 2 "" H 7600 6200 70 0000 C CNN +F 3 "" H 7600 6200 70 0000 C CNN + 1 7600 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_39 +U 1 1 58024070 +P 6300 6200 +F 0 "GND_39" H 6300 6200 20 0000 C CNN +F 1 "+GND" H 6300 6130 30 0000 C CNN +F 2 "" H 6300 6200 70 0000 C CNN +F 3 "" H 6300 6200 70 0000 C CNN + 1 6300 6200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT +U 1 1 5802406F +P 2600 3500 +F 0 "3V3_BATT" H 2600 3500 20 0000 C CNN +F 1 "+3V3_BATT" H 2600 3430 30 0000 C CNN +F 2 "" H 2600 3500 70 0000 C CNN +F 3 "" H 2600 3500 70 0000 C CNN + 1 2600 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9900 6000 9900 6100 +Wire Wire Line + 10100 6100 9900 6100 +Wire Wire Line + 10100 6100 10100 6300 +Wire Wire Line + 10300 6000 10300 6100 +Wire Wire Line + 10300 6100 10100 6100 +Wire Wire Line + 14000 5500 13800 5500 +Wire Wire Line + 13800 5500 13600 5500 +Wire Wire Line + 13600 5500 13400 5500 +Wire Wire Line + 13400 5500 13200 5500 +Wire Wire Line + 13200 5500 13000 5500 +Wire Wire Line + 13000 5500 12800 5500 +Wire Wire Line + 12800 5500 12600 5500 +Wire Wire Line + 12600 5500 12400 5500 +Wire Wire Line + 12400 5500 12200 5500 +Wire Wire Line + 12200 5500 12200 6000 +Wire Wire Line + 12200 6000 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2600 4000 2600 4200 +Wire Wire Line + 2600 3500 2600 3600 +Wire Wire Line + 2400 4500 2300 4500 +Wire Wire Line + 2300 4250 2300 4500 +$Comp +L Cryptech_Alpha:C-EUC0805 C26 +U 1 1 5802406E +P 9900 5800 +F 0 "C26" H 9510 5780 60 0000 L BNN +F 1 "10uF" H 9500 5680 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 9500 5680 60 0001 C CNN +F 3 "" H 9500 5680 60 0000 C CNN + 1 9900 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C31 +U 1 1 5802406D +P 12600 5300 +F 0 "C31" H 12520 5490 60 0000 L BNN +F 1 "0.1uF" H 12480 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12480 5410 60 0001 C CNN +F 3 "" H 12480 5410 60 0000 C CNN + 1 12600 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C32 +U 1 1 5802406C +P 12600 5800 +F 0 "C32" H 12550 5990 60 0000 L BNN +F 1 "0.1uF" H 12960 5930 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12960 5930 60 0001 C CNN +F 3 "" H 12960 5930 60 0000 C CNN + 1 12600 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C30 +U 1 1 5802406B +P 12400 5800 +F 0 "C30" H 12300 5500 60 0000 L BNN +F 1 "0.1uF" H 12240 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12240 5410 60 0001 C CNN +F 3 "" H 12240 5410 60 0000 C CNN + 1 12400 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C29 +U 1 1 5802406A +P 12400 5300 +F 0 "C29" H 12250 5490 60 0000 L BNN +F 1 "0.1uF" H 12240 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12240 5410 60 0001 C CNN +F 3 "" H 12240 5410 60 0000 C CNN + 1 12400 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C28 +U 1 1 58024069 +P 12200 5300 +F 0 "C28" H 11880 5330 60 0000 L BNN +F 1 "0.1uF" H 11870 5210 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11870 5210 60 0001 C CNN +F 3 "" H 11870 5210 60 0000 C CNN + 1 12200 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C46 +U 1 1 58024068 +P 14000 5800 +F 0 "C46" H 14110 5790 60 0000 L BNN +F 1 "0.1uF" H 14120 5690 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 14120 5690 60 0001 C CNN +F 3 "" H 14120 5690 60 0000 C CNN + 1 14000 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C44 +U 1 1 58024067 +P 13800 5800 +F 0 "C44" H 13760 5490 60 0000 L BNN +F 1 "0.1uF" H 13760 5400 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13760 5400 60 0001 C CNN +F 3 "" H 13760 5400 60 0000 C CNN + 1 13800 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C42 +U 1 1 58024066 +P 13600 5800 +F 0 "C42" H 13540 5510 60 0000 L BNN +F 1 "0.1uF" H 13530 5420 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13530 5420 60 0001 C CNN +F 3 "" H 13530 5420 60 0000 C CNN + 1 13600 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C40 +U 1 1 58024065 +P 13400 5800 +F 0 "C40" H 13330 5490 60 0000 L BNN +F 1 "0.1uF" H 13290 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13290 5410 60 0001 C CNN +F 3 "" H 13290 5410 60 0000 C CNN + 1 13400 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C38 +U 1 1 58024064 +P 13200 5800 +F 0 "C38" H 13150 5350 60 0000 L BNN +F 1 "0.1uF" H 13110 5260 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13110 5260 60 0001 C CNN +F 3 "" H 13110 5260 60 0000 C CNN + 1 13200 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C27 +U 1 1 58024063 +P 10300 5800 +F 0 "C27" H 10390 5800 60 0000 L BNN +F 1 "10uF" H 10400 5710 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 10400 5710 60 0001 C CNN +F 3 "" H 10400 5710 60 0000 C CNN + 1 10300 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C36 +U 1 1 58024062 +P 13000 5800 +F 0 "C36" H 12960 5500 60 0000 L BNN +F 1 "0.1uF" H 12950 5430 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12950 5430 60 0001 C CNN +F 3 "" H 12950 5430 60 0000 C CNN + 1 13000 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C34 +U 1 1 58024061 +P 12800 5800 +F 0 "C34" H 12740 5500 60 0000 L BNN +F 1 "0.1uF" H 12700 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12700 5410 60 0001 C CNN +F 3 "" H 12700 5410 60 0000 C CNN + 1 12800 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C21 +U 1 1 58024060 +P 2400 6900 +F 0 "C21" H 2100 7000 60 0000 L BNN +F 1 "1uF" H 2090 6870 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0603" H 2090 6870 60 0001 C CNN +F 3 "" H 2090 6870 60 0000 C CNN + 1 2400 6900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C24 +U 1 1 5802405F +P 6300 5800 +F 0 "C24" H 6140 5785 60 0000 R TNN +F 1 "2.2uF" H 6130 5870 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0603" H 6130 5870 60 0001 C CNN +F 3 "" H 6130 5870 60 0000 C CNN + 1 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C22 +U 1 1 5802405E +P 7800 5800 +F 0 "C22" H 7640 5785 60 0000 R TNN +F 1 "2.2uF" H 7630 5870 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0603" H 7630 5870 60 0001 C CNN +F 3 "" H 7630 5870 60 0000 C CNN + 1 7800 5800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C23 +U 1 1 5802405D +P 7600 5800 +F 0 "C23" H 7897 5770 60 0000 R TNN +F 1 "2.2uF" H 7940 5870 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0603" H 7940 5870 60 0001 C CNN +F 3 "" H 7940 5870 60 0000 C CNN + 1 7600 5800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C25 +U 1 1 5802405C +P 6100 5800 +F 0 "C25" H 6457 5785 60 0000 R TNN +F 1 "2.2uF" H 6460 5880 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0603" H 6460 5880 60 0001 C CNN +F 3 "" H 6460 5880 60 0000 C CNN + 1 6100 5800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R32 +U 1 1 5802405B +P 2600 3800 +F 0 "R32" V 2500 3500 60 0000 L BNN +F 1 "0" V 2580 3600 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2580 3600 60 0001 C CNN +F 3 "" H 2580 3600 60 0000 C CNN + 1 2600 3800 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:STM32F429BIT6_3 U4_2 +U 1 1 5802405A +P 3400 5500 +F 0 "U4_2" H 2690 3890 60 0000 L BNN + 1 3400 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N" H 2690 3890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C45 +U 1 1 58024059 +P 14000 5300 +F 0 "C45" H 13990 5480 60 0000 L BNN +F 1 "0.1uF" H 13960 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13960 5410 60 0001 C CNN +F 3 "" H 13960 5410 60 0000 C CNN + 1 14000 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C43 +U 1 1 58024058 +P 13800 5300 +F 0 "C43" H 13790 5010 60 0000 L BNN +F 1 "0.1uF" H 13780 4930 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13780 4930 60 0001 C CNN +F 3 "" H 13780 4930 60 0000 C CNN + 1 13800 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C41 +U 1 1 58024057 +P 13600 5300 +F 0 "C41" H 13570 5490 60 0000 L BNN +F 1 "0.1uF" H 13540 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13540 5410 60 0001 C CNN +F 3 "" H 13540 5410 60 0000 C CNN + 1 13600 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C39 +U 1 1 58024056 +P 13400 5300 +F 0 "C39" H 13390 5010 60 0000 L BNN +F 1 "0.1uF" H 13390 4920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13390 4920 60 0001 C CNN +F 3 "" H 13390 4920 60 0000 C CNN + 1 13400 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C37 +U 1 1 58024055 +P 13200 5300 +F 0 "C37" H 13120 5490 60 0000 L BNN +F 1 "0.1uF" H 13120 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 13120 5410 60 0001 C CNN +F 3 "" H 13120 5410 60 0000 C CNN + 1 13200 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C35 +U 1 1 58024054 +P 13000 5300 +F 0 "C35" H 12990 5010 60 0000 L BNN +F 1 "0.1uF" H 12760 5410 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12760 5410 60 0001 C CNN +F 3 "" H 12760 5410 60 0000 C CNN + 1 13000 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C33 +U 1 1 58024053 +P 12800 5300 +F 0 "C33" H 12780 5490 60 0000 L BNN +F 1 "0.1uF" H 12520 4920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12520 4920 60 0001 C CNN +F 3 "" H 12520 4920 60 0000 C CNN + 1 12800 5300 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAF93B +P 2600 4000 +F 0 "#FLG?" H 2600 4075 50 0001 C CNN +F 1 "PWR_FLAG" V 2600 4128 50 0000 L CNN +F 2 "" H 2600 4000 50 0001 C CNN +F 3 "~" H 2600 4000 50 0001 C CNN + 1 2600 4000 + 0 -1 -1 0 +$EndComp +Connection ~ 2600 4000 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_05.sch b/KiCAD/rev02_05.sch new file mode 100644 index 0000000..6d85bf5 --- /dev/null +++ b/KiCAD/rev02_05.sch @@ -0,0 +1,674 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 7 27 +Title "rev02_05" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3200 9350 0 60 ~ 12 +All of these input/outputs can be swapped\nwith equivalent functionality pins. +Text Notes 1400 1500 0 126 ~ 12 +Input/output, STM32 +Text Notes 13930 10220 0 84 ~ 12 +ARM I/O +Text Notes 3400 2100 0 60 ~ 12 +U4 +Text Notes 3400 2300 0 60 ~ 12 +STM32F429BIT6 +Wire Wire Line + 10600 7100 9990 7100 +Text GLabel 9990 7100 0 48 Output ~ 0 +FMC_CLK +Wire Wire Line + 10600 6800 9990 6800 +Text GLabel 9990 6800 0 48 UnSpc ~ 0 +FMC_NL +Wire Wire Line + 10600 7200 9990 7200 +Text GLabel 9990 7200 0 48 Output ~ 0 +FMC_NOE +Wire Wire Line + 10600 7300 9990 7300 +Text GLabel 9990 7300 0 48 Output ~ 0 +FMC_NWE +Wire Wire Line + 10600 7400 9990 7400 +Text GLabel 9990 7400 0 48 Output ~ 0 +FMC_NWAIT +Wire Wire Line + 10600 7500 9990 7500 +Text GLabel 9990 7500 0 48 Output ~ 0 +FMC_NE1 +Wire Wire Line + 13490 7700 13000 7700 +Text GLabel 13490 7700 2 48 Output ~ 0 +FMC_SDNCAS +Wire Wire Line + 13490 7800 13000 7800 +Text GLabel 13490 7800 2 48 Output ~ 0 +FMC_SDNRAS +Wire Wire Line + 10600 6200 9990 6200 +Text GLabel 9990 6200 0 48 Output ~ 0 +FMC_NBL0 +Wire Wire Line + 10600 6300 9990 6300 +Text GLabel 9990 6300 0 48 Output ~ 0 +FMC_NBL1 +Wire Wire Line + 10600 6400 9990 6400 +Text GLabel 9990 6400 0 48 Output ~ 0 +FMC_NBL2 +Wire Wire Line + 10600 6500 9990 6500 +Text GLabel 9990 6500 0 48 Output ~ 0 +FMC_NBL3 +Wire Wire Line + 13490 7500 13000 7500 +Text GLabel 13490 7500 2 48 Output ~ 0 +FMC_SDCKE1 +Wire Wire Line + 13490 7200 13000 7200 +Text GLabel 13490 7200 2 48 Output ~ 0 +FMC_SDNE1 +Entry Wire Line + 10040 3400 9990 3450 +Wire Wire Line + 10600 3400 10040 3400 +Text GLabel 10160 3400 2 48 Output ~ 0 +FMC_A0 +Entry Wire Line + 10040 3500 9990 3550 +Wire Wire Line + 10600 3500 10040 3500 +Text GLabel 10160 3500 2 48 Output ~ 0 +FMC_A1 +Entry Wire Line + 10040 3600 9990 3650 +Wire Wire Line + 10600 3600 10040 3600 +Text GLabel 10160 3600 2 48 Output ~ 0 +FMC_A2 +Entry Wire Line + 10040 3700 9990 3750 +Wire Wire Line + 10600 3700 10040 3700 +Text GLabel 10160 3700 2 48 Output ~ 0 +FMC_A3 +Entry Wire Line + 10040 3800 9990 3850 +Wire Wire Line + 10600 3800 10040 3800 +Text GLabel 10160 3800 2 48 Output ~ 0 +FMC_A4 +Entry Wire Line + 10040 3900 9990 3950 +Wire Wire Line + 10600 3900 10040 3900 +Text GLabel 10160 3900 2 48 Output ~ 0 +FMC_A5 +Entry Wire Line + 10040 4000 9990 4050 +Wire Wire Line + 10600 4000 10040 4000 +Text GLabel 10160 4000 2 48 Output ~ 0 +FMC_A6 +Entry Wire Line + 10040 4100 9990 4150 +Wire Wire Line + 10600 4100 10040 4100 +Text GLabel 10160 4100 2 48 Output ~ 0 +FMC_A7 +Entry Wire Line + 10040 4200 9990 4250 +Wire Wire Line + 10600 4200 10040 4200 +Text GLabel 10160 4200 2 48 Output ~ 0 +FMC_A8 +Entry Wire Line + 10040 4300 9990 4350 +Wire Wire Line + 10600 4300 10040 4300 +Text GLabel 10160 4300 2 48 Output ~ 0 +FMC_A9 +Entry Wire Line + 10040 4400 9990 4450 +Wire Wire Line + 10600 4400 10040 4400 +Text GLabel 10160 4400 2 48 Output ~ 0 +FMC_A10 +Entry Wire Line + 10040 4500 9990 4550 +Wire Wire Line + 10600 4500 10040 4500 +Text GLabel 10160 4500 2 48 Output ~ 0 +FMC_A11 +Entry Wire Line + 10040 4600 9990 4650 +Wire Wire Line + 10600 4600 10040 4600 +Text GLabel 10160 4600 2 48 Output ~ 0 +FMC_A12 +Entry Wire Line + 10040 4700 9990 4750 +Wire Wire Line + 10600 4700 10040 4700 +Text GLabel 10160 4700 2 48 Output ~ 0 +FMC_A13 +Entry Wire Line + 10040 4800 9990 4850 +Wire Wire Line + 10600 4800 10040 4800 +Text GLabel 10160 4800 2 48 Output ~ 0 +FMC_A14 +Entry Wire Line + 10040 4900 9990 4950 +Wire Wire Line + 10600 4900 10040 4900 +Text GLabel 10160 4900 2 48 Output ~ 0 +FMC_A15 +Entry Wire Line + 10040 5000 9990 5050 +Wire Wire Line + 10600 5000 10040 5000 +Text GLabel 10160 5000 2 48 Output ~ 0 +FMC_A16 +Entry Wire Line + 10040 5100 9990 5150 +Wire Wire Line + 10600 5100 10040 5100 +Text GLabel 10160 5100 2 48 Output ~ 0 +FMC_A17 +Entry Wire Line + 10040 5200 9990 5250 +Wire Wire Line + 10600 5200 10040 5200 +Text GLabel 10160 5200 2 48 Output ~ 0 +FMC_A18 +Entry Wire Line + 10040 5300 9990 5350 +Wire Wire Line + 10600 5300 10040 5300 +Text GLabel 10160 5300 2 48 Output ~ 0 +FMC_A19 +Entry Wire Line + 10040 5400 9990 5450 +Wire Wire Line + 10600 5400 10040 5400 +Text GLabel 10160 5400 2 48 Output ~ 0 +FMC_A20 +Entry Wire Line + 10040 5500 9990 5550 +Wire Wire Line + 10600 5500 10040 5500 +Text GLabel 10160 5500 2 48 Output ~ 0 +FMC_A21 +Entry Wire Line + 10040 5600 9990 5650 +Wire Wire Line + 10600 5600 10040 5600 +Text GLabel 10160 5600 2 48 Output ~ 0 +FMC_A22 +Entry Wire Line + 10040 5700 9990 5750 +Wire Wire Line + 10600 5700 10040 5700 +Text GLabel 10160 5700 2 48 Output ~ 0 +FMC_A23 +Entry Wire Line + 10040 5800 9990 5850 +Wire Wire Line + 10600 5800 10040 5800 +Text GLabel 10160 5800 2 48 Output ~ 0 +FMC_A24 +Entry Wire Line + 10040 5900 9990 5900 +Wire Wire Line + 10600 5900 10040 5900 +Text GLabel 10160 5900 2 48 Output ~ 0 +FMC_A25 +Entry Wire Line + 13450 3400 13500 3350 +Wire Wire Line + 13450 3400 13000 3400 +Text GLabel 13070 3400 2 48 BiDi ~ 0 +FMC_D0 +Entry Wire Line + 13450 3500 13500 3450 +Wire Wire Line + 13450 3500 13000 3500 +Text GLabel 13070 3500 2 48 BiDi ~ 0 +FMC_D1 +Entry Wire Line + 13450 3600 13500 3550 +Wire Wire Line + 13450 3600 13000 3600 +Text GLabel 13070 3600 2 48 BiDi ~ 0 +FMC_D2 +Entry Wire Line + 13450 3700 13500 3650 +Wire Wire Line + 13450 3700 13000 3700 +Text GLabel 13070 3700 2 48 BiDi ~ 0 +FMC_D3 +Entry Wire Line + 13450 3800 13500 3750 +Wire Wire Line + 13450 3800 13000 3800 +Text GLabel 13070 3800 2 48 BiDi ~ 0 +FMC_D4 +Entry Wire Line + 13450 3900 13500 3850 +Wire Wire Line + 13450 3900 13000 3900 +Text GLabel 13070 3900 2 48 BiDi ~ 0 +FMC_D5 +Entry Wire Line + 13450 4000 13500 3950 +Wire Wire Line + 13450 4000 13000 4000 +Text GLabel 13070 4000 2 48 BiDi ~ 0 +FMC_D6 +Entry Wire Line + 13450 4100 13500 4050 +Wire Wire Line + 13450 4100 13000 4100 +Text GLabel 13070 4100 2 48 BiDi ~ 0 +FMC_D7 +Entry Wire Line + 13450 4200 13500 4150 +Wire Wire Line + 13450 4200 13000 4200 +Text GLabel 13070 4200 2 48 BiDi ~ 0 +FMC_D8 +Entry Wire Line + 13450 4300 13500 4250 +Wire Wire Line + 13450 4300 13000 4300 +Text GLabel 13070 4300 2 48 BiDi ~ 0 +FMC_D9 +Entry Wire Line + 13450 4400 13500 4350 +Wire Wire Line + 13450 4400 13000 4400 +Text GLabel 13070 4400 2 48 BiDi ~ 0 +FMC_D10 +Entry Wire Line + 13450 4500 13500 4450 +Wire Wire Line + 13450 4500 13000 4500 +Text GLabel 13070 4500 2 48 BiDi ~ 0 +FMC_D11 +Entry Wire Line + 13450 4600 13500 4550 +Wire Wire Line + 13450 4600 13000 4600 +Text GLabel 13070 4600 2 48 BiDi ~ 0 +FMC_D12 +Entry Wire Line + 13450 4700 13500 4650 +Wire Wire Line + 13450 4700 13000 4700 +Text GLabel 13070 4700 2 48 BiDi ~ 0 +FMC_D13 +Entry Wire Line + 13450 4800 13500 4750 +Wire Wire Line + 13450 4800 13000 4800 +Text GLabel 13070 4800 2 48 BiDi ~ 0 +FMC_D14 +Entry Wire Line + 13450 4900 13500 4850 +Wire Wire Line + 13450 4900 13000 4900 +Text GLabel 13070 4900 2 48 BiDi ~ 0 +FMC_D15 +Entry Wire Line + 13450 5000 13500 4950 +Wire Wire Line + 13450 5000 13000 5000 +Text GLabel 13070 5000 2 48 BiDi ~ 0 +FMC_D16 +Entry Wire Line + 13450 5100 13500 5050 +Wire Wire Line + 13450 5100 13000 5100 +Text GLabel 13070 5100 2 48 BiDi ~ 0 +FMC_D17 +Entry Wire Line + 13450 5200 13500 5150 +Wire Wire Line + 13450 5200 13000 5200 +Text GLabel 13070 5200 2 48 BiDi ~ 0 +FMC_D18 +Entry Wire Line + 13450 5300 13500 5250 +Wire Wire Line + 13450 5300 13000 5300 +Text GLabel 13070 5300 2 48 BiDi ~ 0 +FMC_D19 +Entry Wire Line + 13450 5400 13500 5350 +Wire Wire Line + 13450 5400 13000 5400 +Text GLabel 13070 5400 2 48 BiDi ~ 0 +FMC_D20 +Entry Wire Line + 13450 5500 13500 5450 +Wire Wire Line + 13450 5500 13000 5500 +Text GLabel 13070 5500 2 48 BiDi ~ 0 +FMC_D21 +Entry Wire Line + 13450 5600 13500 5550 +Wire Wire Line + 13450 5600 13000 5600 +Text GLabel 13070 5600 2 48 BiDi ~ 0 +FMC_D22 +Entry Wire Line + 13450 5700 13500 5650 +Wire Wire Line + 13450 5700 13000 5700 +Text GLabel 13070 5700 2 48 BiDi ~ 0 +FMC_D23 +Entry Wire Line + 13450 5800 13500 5750 +Wire Wire Line + 13450 5800 13000 5800 +Text GLabel 13070 5800 2 48 BiDi ~ 0 +FMC_D24 +Entry Wire Line + 13450 5900 13500 5850 +Wire Wire Line + 13450 5900 13000 5900 +Text GLabel 13070 5900 2 48 BiDi ~ 0 +FMC_D25 +Entry Wire Line + 13450 6000 13500 5950 +Wire Wire Line + 13450 6000 13000 6000 +Text GLabel 13070 6000 2 48 BiDi ~ 0 +FMC_D26 +Entry Wire Line + 13450 6100 13500 6050 +Wire Wire Line + 13450 6100 13000 6100 +Text GLabel 13070 6100 2 48 BiDi ~ 0 +FMC_D27 +Entry Wire Line + 13450 6200 13500 6150 +Wire Wire Line + 13450 6200 13000 6200 +Text GLabel 13070 6200 2 48 BiDi ~ 0 +FMC_D28 +Entry Wire Line + 13450 6300 13500 6250 +Wire Wire Line + 13450 6300 13000 6300 +Text GLabel 13070 6300 2 48 BiDi ~ 0 +FMC_D29 +Entry Wire Line + 13450 6400 13500 6350 +Wire Wire Line + 13450 6400 13000 6400 +Text GLabel 13070 6400 2 48 BiDi ~ 0 +FMC_D30 +Entry Wire Line + 13450 6500 13500 6450 +Wire Wire Line + 13450 6500 13000 6500 +Text GLabel 13070 6500 2 48 BiDi ~ 0 +FMC_D31 +Wire Wire Line + 13490 7400 13000 7400 +Text GLabel 13490 7400 2 48 Output ~ 0 +FMC_SDCKE0 +Wire Wire Line + 13490 7100 13000 7100 +Text GLabel 13490 7100 2 48 Output ~ 0 +FMC_SDNE0 +Wire Wire Line + 13490 6900 13000 6900 +Text GLabel 13490 6900 2 48 Output ~ 0 +FMC_SDNWE +Wire Wire Line + 13490 6800 13000 6800 +Text GLabel 13490 6800 2 48 Output ~ 0 +FMC_SDCLK +Wire Wire Line + 3100 2900 2250 2900 +Text GLabel 2250 2900 0 48 Input ~ 0 +FT_TXD +Wire Wire Line + 3100 2800 2250 2800 +Text GLabel 2250 2800 0 48 Output ~ 0 +FT_RXD +Wire Wire Line + 7050 4300 6200 4300 +Text GLabel 7050 4300 2 48 BiDi ~ 0 +AVR_GPIO_ARM_1 +Wire Wire Line + 7050 4400 6200 4400 +Text GLabel 7050 4400 2 48 BiDi ~ 0 +AVR_GPIO_ARM_0 +Wire Wire Line + 3100 6200 2250 6200 +Text GLabel 2250 6200 0 48 Output ~ 0 +RTC_SCL +Wire Wire Line + 3100 6100 2250 6100 +Text GLabel 2250 6100 0 48 BiDi ~ 0 +RTC_SDA +Wire Wire Line + 3100 6300 2250 6300 +Text GLabel 2250 6300 0 48 UnSpc ~ 0 +RTC_MFP +Wire Wire Line + 7000 6500 6200 6500 +Text GLabel 7000 6500 2 48 UnSpc ~ 0 +FPGA_IRQ_N_0 +Wire Wire Line + 7000 6600 6200 6600 +Text GLabel 7000 6600 2 48 UnSpc ~ 0 +FPGA_IRQ_N_1 +Wire Wire Line + 7000 6700 6200 6700 +Text GLabel 7000 6700 2 48 UnSpc ~ 0 +FPGA_IRQ_N_2 +Wire Wire Line + 7000 6800 6200 6800 +Text GLabel 7000 6800 2 48 UnSpc ~ 0 +FPGA_IRQ_N_3 +Wire Wire Line + 7000 6300 6200 6300 +Text GLabel 7000 6300 2 48 UnSpc ~ 0 +FPGA_PROGRAM_B +Wire Wire Line + 7000 6200 6200 6200 +Text GLabel 7000 6200 2 48 UnSpc ~ 0 +FPGA_INIT_B +Wire Wire Line + 3100 4200 2250 4200 +Text GLabel 2250 4200 0 48 Output ~ 0 +ARM_FPGA_CFG_SCLK +Wire Wire Line + 3100 4300 2250 4300 +Text GLabel 2250 4300 0 48 Input ~ 0 +ARM_FPGA_CFG_MISO +Wire Wire Line + 3100 4400 2250 4400 +Text GLabel 2250 4400 0 48 Output ~ 0 +ARM_FPGA_CFG_MOSI +Wire Wire Line + 3100 4800 2250 4800 +Text GLabel 2250 4800 0 48 Output ~ 0 +KSM_PROM_SCLK +Wire Wire Line + 3100 4900 2250 4900 +Text GLabel 2250 4900 0 48 Input ~ 0 +KSM_PROM_MISO +Wire Wire Line + 3100 5000 2250 5000 +Text GLabel 2250 5000 0 48 Output ~ 0 +KSM_PROM_MOSI +Wire Wire Line + 3100 3100 2250 3100 +Text GLabel 2250 3100 0 48 Output ~ 0 +FT_RTS +Wire Wire Line + 3100 3000 2250 3000 +Text GLabel 2250 3000 0 48 UnSpc ~ 0 +FT_CTS +Wire Wire Line + 3100 3500 2250 3500 +Text GLabel 2250 3500 0 48 Output ~ 0 +FT_MGMT_RXD +Wire Wire Line + 3100 3600 2250 3600 +Text GLabel 2250 3600 0 48 Input ~ 0 +FT_MGMT_TXD +Wire Wire Line + 3100 3700 2250 3700 +Text GLabel 2250 3700 0 48 Input ~ 0 +FT_MGMT_CTS +Wire Wire Line + 3100 3800 2250 3800 +Text GLabel 2250 3800 0 48 Output ~ 0 +FT_MGMT_RTS +Wire Wire Line + 7000 7000 6200 7000 +Text GLabel 7000 7000 2 48 UnSpc ~ 0 +FPGA_DONE +Wire Wire Line + 3100 2700 2250 2700 +Text GLabel 2250 2700 0 48 UnSpc ~ 0 +FT_DTR +Wire Wire Line + 3100 3400 2250 3400 +Text GLabel 2250 3400 0 48 Output ~ 0 +FT_MGMT_DTR +Wire Wire Line + 3100 4100 2250 4100 +Text GLabel 2250 4100 0 48 Output ~ 0 +ARM_FPGA_CFG_CS_N +Wire Wire Line + 3100 4700 2250 4700 +Text GLabel 2250 4700 0 48 Output ~ 0 +KSM_PROM_CS_N +Wire Wire Line + 3100 7300 2250 7300 +Text GLabel 2250 7300 0 48 BiDi ~ 0 +AVR_GPIO_ARM_2 +Wire Wire Line + 3100 7200 2250 7200 +Text GLabel 2250 7200 0 48 BiDi ~ 0 +AVR_GPIO_ARM_3 +Wire Bus Line + 14900 3200 13500 3200 +Wire Bus Line + 13500 3200 13500 6500 +Text Label 13500 3200 0 60 ~ +FMC_D[0..31]FMC_A[0..25] +Wire Bus Line + 9990 3200 9990 5900 +Wire Bus Line + 9990 3200 8590 3200 +Text Label 8590 3200 0 60 ~ +FMC_D[0..31]FMC_A[0..25] +Wire Wire Line + 7000 7700 6200 7700 +Text GLabel 7000 7700 2 48 Output ~ 0 +ARM_LED1 +Wire Wire Line + 7000 7800 6200 7800 +Text GLabel 7000 7800 2 48 Output ~ 0 +ARM_LED2 +Wire Wire Line + 7000 7900 6200 7900 +Text GLabel 7000 7900 2 48 Output ~ 0 +ARM_LED3 +Wire Wire Line + 7000 8000 6200 8000 +Text GLabel 7000 8000 2 48 Output ~ 0 +ARM_LED4 +Wire Wire Line + 7000 5100 6200 5100 +Text GLabel 7000 5100 2 48 Output ~ 0 +FPGA_CFG_CTRL_FPGA_DIS +Wire Wire Line + 7000 2700 6200 2700 +Text GLabel 7000 2700 2 48 Output ~ 0 +FPGA_CFG_CTRL_ARM_ENA +$Comp +L Cryptech_Alpha:STM32F429BIT6_4 U4_3 +U 1 1 58024052 +P 11900 5500 +F 0 "U4_3" H 10690 2690 60 0000 L BNN + 1 11900 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N" H 10690 2690 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:STM32F429BIT6_1 U4_4 +U 1 1 58024051 +P 4700 5600 +F 0 "U4_4" H 3190 2390 60 0000 L BNN + 1 4700 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:TSQFP50P3000X3000X160-208N" H 3190 2390 60 0001 C CNN +$EndComp +NoConn ~ 3100 5300 +NoConn ~ 3100 5400 +NoConn ~ 3100 5500 +NoConn ~ 3100 5600 +NoConn ~ 3100 5700 +NoConn ~ 3100 5800 +NoConn ~ 3100 6900 +NoConn ~ 3100 7000 +NoConn ~ 3100 7100 +NoConn ~ 3100 7700 +NoConn ~ 3100 7800 +NoConn ~ 3100 7900 +NoConn ~ 3100 8000 +NoConn ~ 3100 8100 +NoConn ~ 3100 8200 +NoConn ~ 3100 8300 +NoConn ~ 3100 8400 +NoConn ~ 6200 7600 +NoConn ~ 6200 7500 +NoConn ~ 6200 7400 +NoConn ~ 6200 7300 +NoConn ~ 6200 6900 +NoConn ~ 6200 6400 +NoConn ~ 6200 6100 +NoConn ~ 6200 6000 +NoConn ~ 6200 5900 +NoConn ~ 6200 5800 +NoConn ~ 6200 5700 +NoConn ~ 6200 5600 +NoConn ~ 6200 5500 +NoConn ~ 6200 5200 +NoConn ~ 6200 5000 +NoConn ~ 6200 4900 +NoConn ~ 6200 4800 +NoConn ~ 6200 4700 +NoConn ~ 6200 4200 +NoConn ~ 6200 3900 +NoConn ~ 6200 3800 +NoConn ~ 6200 3700 +NoConn ~ 6200 3600 +NoConn ~ 6200 3500 +NoConn ~ 6200 3400 +NoConn ~ 6200 3100 +NoConn ~ 6200 3000 +NoConn ~ 6200 2900 +NoConn ~ 6200 2800 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_06.sch b/KiCAD/rev02_06.sch new file mode 100644 index 0000000..7e4271d --- /dev/null +++ b/KiCAD/rev02_06.sch @@ -0,0 +1,1434 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 8 27 +Title "rev02_06" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 5500 1300 0 126 ~ 12 +2x512 Mbit SDRAM memory for the ARM +Text Notes 13910 10230 0 84 ~ 12 +SDRAM +Text Notes 6000 1700 0 60 ~ 12 +These packages are TSSOP, but if new packages are to be created\nfor layout, BGA package is preferred. +Text Notes 3180 2240 0 60 ~ 12 +U5 +Text Notes 3900 4500 0 60 ~ 12 +IS45S32160F +Text Notes 10160 2330 0 60 ~ 12 +U6 +Text Notes 10900 4600 0 60 ~ 12 +IS45S32160F +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_8 +U 1 1 58024050 +P 3900 2050 +F 0 "VCCO_3V3_8" H 3900 2050 20 0000 C CNN +F 1 "+VCCO_3V3" H 3900 1980 30 0000 C CNN +F 2 "" H 3900 2050 70 0000 C CNN +F 3 "" H 3900 2050 70 0000 C CNN + 1 3900 2050 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_9 +U 1 1 5802404F +P 4400 2050 +F 0 "VCCO_3V3_9" H 4400 2050 20 0000 C CNN +F 1 "+VCCO_3V3" H 4400 1980 30 0000 C CNN +F 2 "" H 4400 2050 70 0000 C CNN +F 3 "" H 4400 2050 70 0000 C CNN + 1 4400 2050 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_40 +U 1 1 5802404E +P 4500 7200 +F 0 "GND_40" H 4500 7200 20 0000 C CNN +F 1 "+GND" H 4500 7130 30 0000 C CNN +F 2 "" H 4500 7200 70 0000 C CNN +F 3 "" H 4500 7200 70 0000 C CNN + 1 4500 7200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_10 +U 1 1 5802404D +P 3500 7650 +F 0 "VCCO_3V3_10" H 3500 7650 20 0000 C CNN +F 1 "+VCCO_3V3" H 3500 7580 30 0000 C CNN +F 2 "" H 3500 7650 70 0000 C CNN +F 3 "" H 3500 7650 70 0000 C CNN + 1 3500 7650 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_41 +U 1 1 5802404C +P 3500 9000 +F 0 "GND_41" H 3500 9000 20 0000 C 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5000 13300 4950 +Wire Wire Line + 13250 5000 12700 5000 +Text GLabel 5820 4900 2 48 BiDi ~ 0 +FMC_D23 +Text GLabel 12820 5000 2 48 BiDi ~ 0 +FMC_D23 +Entry Wire Line + 6250 5000 6300 4950 +Wire Wire Line + 6250 5000 5700 5000 +Entry Wire Line + 13250 5100 13300 5050 +Wire Wire Line + 13250 5100 12700 5100 +Text GLabel 5820 5000 2 48 BiDi ~ 0 +FMC_D24 +Text GLabel 12820 5100 2 48 BiDi ~ 0 +FMC_D24 +Entry Wire Line + 6250 5100 6300 5050 +Wire Wire Line + 6250 5100 5700 5100 +Entry Wire Line + 13250 5200 13300 5150 +Wire Wire Line + 13250 5200 12700 5200 +Text GLabel 5820 5100 2 48 BiDi ~ 0 +FMC_D25 +Text GLabel 12820 5200 2 48 BiDi ~ 0 +FMC_D25 +Entry Wire Line + 6250 5200 6300 5150 +Wire Wire Line + 6250 5200 5700 5200 +Entry Wire Line + 13250 5300 13300 5250 +Wire Wire Line + 13250 5300 12700 5300 +Text GLabel 5820 5200 2 48 BiDi ~ 0 +FMC_D26 +Text GLabel 12820 5300 2 48 BiDi ~ 0 +FMC_D26 +Entry Wire Line + 6250 5300 6300 5250 +Wire Wire Line + 6250 5300 5700 5300 +Entry Wire Line + 13250 5400 13300 5350 +Wire Wire Line + 13250 5400 12700 5400 +Text GLabel 5820 5300 2 48 BiDi ~ 0 +FMC_D27 +Text GLabel 12820 5400 2 48 BiDi ~ 0 +FMC_D27 +Entry Wire Line + 6250 5400 6300 5350 +Wire Wire Line + 6250 5400 5700 5400 +Entry Wire Line + 13250 5500 13300 5450 +Wire Wire Line + 13250 5500 12700 5500 +Text GLabel 5820 5400 2 48 BiDi ~ 0 +FMC_D28 +Text GLabel 12820 5500 2 48 BiDi ~ 0 +FMC_D28 +Entry Wire Line + 6250 5500 6300 5450 +Wire Wire Line + 6250 5500 5700 5500 +Entry Wire Line + 13250 5600 13300 5550 +Wire Wire Line + 13250 5600 12700 5600 +Text GLabel 5820 5500 2 48 BiDi ~ 0 +FMC_D29 +Text GLabel 12820 5600 2 48 BiDi ~ 0 +FMC_D29 +Entry Wire Line + 6250 5600 6300 5550 +Wire Wire Line + 6250 5600 5700 5600 +Entry Wire Line + 13250 5700 13300 5650 +Wire Wire Line + 13250 5700 12700 5700 +Text GLabel 5820 5600 2 48 BiDi ~ 0 +FMC_D30 +Text GLabel 12820 5700 2 48 BiDi ~ 0 +FMC_D30 +Entry Wire Line + 6250 5700 6300 5650 +Wire Wire Line + 6250 5700 5700 5700 +Entry Wire Line + 13250 5800 13300 5750 +Wire Wire Line + 13250 5800 12700 5800 +Text GLabel 5820 5700 2 48 BiDi ~ 0 +FMC_D31 +Text GLabel 12820 5800 2 48 BiDi ~ 0 +FMC_D31 +Wire Wire Line + 3300 5500 2700 5500 +Text GLabel 2700 5500 0 48 Input ~ 0 +FMC_SDCKE0 +Wire Wire Line + 3300 6000 2700 6000 +Text GLabel 2700 6000 0 48 Input ~ 0 +FMC_SDNE0 +Wire Wire Line + 3300 6500 2700 6500 +Text GLabel 2700 6500 0 48 Input ~ 0 +FMC_SDNWE +Wire Wire Line + 10300 6600 9700 6600 +Text GLabel 9700 6600 0 48 Input ~ 0 +FMC_SDNWE +Wire Wire Line + 3300 4400 2700 4400 +Text GLabel 2700 4400 0 48 Input ~ 0 +FMC_SDNCAS +Wire Wire Line + 10300 4500 9700 4500 +Text GLabel 9700 4500 0 48 Input ~ 0 +FMC_SDNCAS +Wire Wire Line + 3300 4500 2700 4500 +Text GLabel 2700 4500 0 48 Input ~ 0 +FMC_SDNRAS +Wire Wire Line + 10300 4600 9700 4600 +Text GLabel 9700 4600 0 48 Input ~ 0 +FMC_SDNRAS +Entry Wire Line + 2750 4100 2700 4150 +Wire Wire Line + 3300 4100 2750 4100 +Text GLabel 2850 4100 2 48 Input ~ 0 +FMC_A14 +Entry Wire Line + 9750 4200 9700 4250 +Wire Wire Line + 10300 4200 9750 4200 +Text GLabel 9850 4200 2 48 Input ~ 0 +FMC_A14 +Entry Wire Line + 2750 4200 2700 4200 +Wire Wire Line + 3300 4200 2750 4200 +Text GLabel 2850 4200 2 48 Input ~ 0 +FMC_A15 +Entry Wire Line + 9750 4300 9700 4300 +Wire Wire Line + 10300 4300 9750 4300 +Text GLabel 9850 4300 2 48 Input ~ 0 +FMC_A15 +Wire Wire Line + 6300 5900 5700 5900 +Text GLabel 6300 5900 2 48 Input ~ 0 +FMC_NBL0 +Wire Wire Line + 13300 6000 12700 6000 +Text GLabel 13300 6000 2 48 Input ~ 0 +FMC_NBL0 +Wire Wire Line + 6300 6000 5700 6000 +Text GLabel 6300 6000 2 48 Input ~ 0 +FMC_NBL1 +Wire Wire Line + 13300 6100 12700 6100 +Text GLabel 13300 6100 2 48 Input ~ 0 +FMC_NBL1 +Wire Wire Line + 6300 6100 5700 6100 +Text GLabel 6300 6100 2 48 Input ~ 0 +FMC_NBL2 +Wire Wire Line + 13300 6200 12700 6200 +Text GLabel 13300 6200 2 48 Input ~ 0 +FMC_NBL2 +Wire Wire Line + 6300 6200 5700 6200 +Text GLabel 6300 6200 2 48 Input ~ 0 +FMC_NBL3 +Wire Wire Line + 13300 6300 12700 6300 +Text GLabel 13300 6300 2 48 Input ~ 0 +FMC_NBL3 +Wire Wire Line + 3300 5000 2700 5000 +Text GLabel 2700 5000 0 48 Input ~ 0 +FMC_SDCLK +Wire Wire Line + 10300 5100 9700 5100 +Text GLabel 9700 5100 0 48 Input ~ 0 +FMC_SDCLK +Wire Wire Line + 10300 5600 9700 5600 +Text GLabel 9700 5600 0 48 Input ~ 0 +FMC_SDCKE1 +Wire Wire Line + 10300 6100 9700 6100 +Text GLabel 9700 6100 0 48 Input ~ 0 +FMC_SDNE1 +Wire Bus Line + 2700 2400 2150 2400 +Wire Bus Line + 2700 2400 2700 4200 +Text Label 2150 2400 0 60 ~ +FMC_A[0..25] +Wire Bus Line + 9700 2500 9150 2500 +Wire Bus Line + 9700 2500 9700 4300 +Text Label 9150 2500 0 60 ~ +FMC_A[0..25] +Wire Bus Line + 6300 2400 6300 5700 +Wire Bus Line + 6900 2400 6300 2400 +Text Label 6300 2400 0 60 ~ +FMC_D[0..31] +Wire Bus Line + 13300 2500 13300 5800 +Wire Bus Line + 13900 2500 13300 2500 +Text Label 13300 2500 0 60 ~ +FMC_D[0..31] +$Comp +L Cryptech_Alpha:IS45S32160F U5 +U 1 1 58024046 +P 4500 4600 +F 0 "U5" H 5720 6710 60 0000 L BNN +F 1 "IS45S32160F*" H 3160 6830 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N" H 3160 6830 60 0001 C CNN +F 3 "" H 3160 6830 60 0000 C CNN + 1 4500 4600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C57 +U 1 1 58024045 +P 4500 8500 +F 0 "C57" H 4610 8460 60 0000 L BNN +F 1 "0.1uF" H 4470 9160 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4470 9160 60 0001 C CNN +F 3 "" H 4470 9160 60 0000 C CNN + 1 4500 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C55 +U 1 1 58024044 +P 4300 8500 +F 0 "C55" H 4290 8200 60 0000 L BNN +F 1 "0.1uF" H 4610 8400 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4610 8400 60 0001 C CNN +F 3 "" H 4610 8400 60 0000 C CNN + 1 4300 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C53 +U 1 1 58024043 +P 4100 8500 +F 0 "C53" H 4000 8200 60 0000 L BNN +F 1 "0.1uF" H 4290 8130 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4290 8130 60 0001 C CNN +F 3 "" H 4290 8130 60 0000 C CNN + 1 4100 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:IS45S32160F U6 +U 1 1 58024042 +P 11500 4700 +F 0 "U6" H 12720 6810 60 0000 L BNN +F 1 "IS45S32160F*" H 10140 6950 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:TSSOP50P1180X120-86N" H 10140 6950 60 0001 C CNN +F 3 "" H 10140 6950 60 0000 C CNN + 1 11500 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C67 +U 1 1 58024041 +P 11500 8100 +F 0 "C67" H 11490 8300 60 0000 L BNN +F 1 "0.1uF" H 11480 8240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11480 8240 60 0001 C CNN +F 3 "" H 11480 8240 60 0000 C CNN + 1 11500 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C65 +U 1 1 58024040 +P 11300 8100 +F 0 "C65" H 11260 8290 60 0000 L BNN +F 1 "0.1uF" H 11240 8240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11240 8240 60 0001 C CNN +F 3 "" H 11240 8240 60 0000 C CNN + 1 11300 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C63 +U 1 1 5802403F +P 11100 8100 +F 0 "C63" H 11070 8380 60 0000 L BNN +F 1 "0.1uF" H 11030 8320 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11030 8320 60 0001 C CNN +F 3 "" H 11030 8320 60 0000 C CNN + 1 11100 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C61 +U 1 1 5802403E +P 10900 8100 +F 0 "C61" H 10840 8290 60 0000 L BNN +F 1 "0.1uF" H 10830 8230 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10830 8230 60 0001 C CNN +F 3 "" H 10830 8230 60 0000 C CNN + 1 10900 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C62 +U 1 1 5802403D +P 10900 8600 +F 0 "C62" H 10780 8780 60 0000 L BNN +F 1 "0.1uF" H 10780 8720 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10780 8720 60 0001 C CNN +F 3 "" H 10780 8720 60 0000 C CNN + 1 10900 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C60 +U 1 1 5802403C +P 10700 8600 +F 0 "C60" H 10600 8300 60 0000 L BNN +F 1 "0.1uF" H 10600 8240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10600 8240 60 0001 C CNN +F 3 "" H 10600 8240 60 0000 C CNN + 1 10700 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C56 +U 1 1 5802403B +P 4500 8000 +F 0 "C56" H 4470 8220 60 0000 L BNN +F 1 "0.1uF" H 4070 8150 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4070 8150 60 0001 C CNN +F 3 "" H 4070 8150 60 0000 C CNN + 1 4500 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C59 +U 1 1 5802403A +P 10700 8100 +F 0 "C59" H 10600 8290 60 0000 L BNN +F 1 "0.1uF" H 10600 8230 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10600 8230 60 0001 C CNN +F 3 "" H 10600 8230 60 0000 C CNN + 1 10700 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C58 +U 1 1 58024039 +P 10500 8100 +F 0 "C58" H 10160 8080 60 0000 L BNN +F 1 "0.1uF" H 10160 8020 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10160 8020 60 0001 C CNN +F 3 "" H 10160 8020 60 0000 C CNN + 1 10500 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C68 +U 1 1 58024038 +P 11500 8600 +F 0 "C68" H 11620 8560 60 0000 L BNN +F 1 "0.1uF" H 11620 8500 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11620 8500 60 0001 C CNN +F 3 "" H 11620 8500 60 0000 C CNN + 1 11500 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C66 +U 1 1 58024037 +P 11300 8600 +F 0 "C66" H 11220 8780 60 0000 L BNN +F 1 "0.1uF" H 11220 8720 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11220 8720 60 0001 C CNN +F 3 "" H 11220 8720 60 0000 C CNN + 1 11300 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C64 +U 1 1 58024036 +P 11100 8600 +F 0 "C64" H 11000 8300 60 0000 L BNN +F 1 "0.1uF" H 11000 8240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11000 8240 60 0001 C CNN +F 3 "" H 11000 8240 60 0000 C CNN + 1 11100 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C54 +U 1 1 58024035 +P 4300 8000 +F 0 "C54" H 4280 7700 60 0000 L BNN +F 1 "0.1uF" H 4280 7640 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4280 7640 60 0001 C CNN +F 3 "" H 4280 7640 60 0000 C CNN + 1 4300 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C52 +U 1 1 58024034 +P 4100 8000 +F 0 "C52" H 4070 8210 60 0000 L BNN +F 1 "0.1uF" H 3790 7630 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3790 7630 60 0001 C CNN +F 3 "" H 3790 7630 60 0000 C CNN + 1 4100 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C50 +U 1 1 58024033 +P 3900 8000 +F 0 "C50" H 3810 8210 60 0000 L BNN +F 1 "0.1uF" H 3810 8150 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3810 8150 60 0001 C CNN +F 3 "" H 3810 8150 60 0000 C CNN + 1 3900 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C51 +U 1 1 58024032 +P 3900 8500 +F 0 "C51" H 3790 8690 60 0000 L BNN +F 1 "0.1uF" H 3990 8130 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3990 8130 60 0001 C CNN +F 3 "" H 3990 8130 60 0000 C CNN + 1 3900 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C49 +U 1 1 58024031 +P 3700 8500 +F 0 "C49" H 3530 8210 60 0000 L BNN +F 1 "0.1uF" H 3530 8140 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3530 8140 60 0001 C CNN +F 3 "" H 3530 8140 60 0000 C CNN + 1 3700 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C48 +U 1 1 58024030 +P 3700 8000 +F 0 "C48" H 3540 8210 60 0000 L BNN +F 1 "0.1uF" H 3540 8150 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3540 8150 60 0001 C CNN +F 3 "" H 3540 8150 60 0000 C CNN + 1 3700 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C47 +U 1 1 5802402F +P 3500 8000 +F 0 "C47" H 3130 7980 60 0000 L BNN +F 1 "0.1uF" H 3120 7920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3120 7920 60 0001 C CNN +F 3 "" H 3120 7920 60 0000 C CNN + 1 3500 8000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_07.sch b/KiCAD/rev02_07.sch new file mode 100644 index 0000000..a25a91a --- /dev/null +++ b/KiCAD/rev02_07.sch @@ -0,0 +1,168 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 9 27 +Title "rev02_07" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 8900 5200 0 60 ~ 12 +*) HOLD feature not used +Text Notes 6400 3800 0 84 ~ 12 +This memory holds cryptographic keys\nwrapped with the master key. +Text Notes 6400 3200 0 126 ~ 12 +Keystore memory, 128 Mbit +Text Notes 13640 10230 0 84 ~ 12 +Keystore memory +Text Notes 7190 5380 0 60 ~ 12 +IC1 +Text Notes 7760 5380 0 60 ~ 12 +N25Q128A13ES +Text Notes 9760 5990 0 60 ~ 12 +C69 +Text Notes 9760 6190 0 60 ~ 12 +0.1~uF +$Comp +L power:GND GND_44 +U 1 1 5802402E +P 6800 6500 +F 0 "GND_44" H 6800 6500 20 0000 C CNN +F 1 "+GND" H 6800 6430 30 0000 C CNN +F 2 "" H 6800 6500 70 0000 C CNN +F 3 "" H 6800 6500 70 0000 C CNN + 1 6800 6500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_45 +U 1 1 5802402D +P 9700 6500 +F 0 "GND_45" H 9700 6500 20 0000 C CNN +F 1 "+GND" H 9700 6430 30 0000 C CNN +F 2 "" H 9700 6500 70 0000 C CNN +F 3 "" H 9700 6500 70 0000 C CNN + 1 9700 6500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_14 +U 1 1 5802402C +P 6200 4400 +F 0 "VCCO_3V3_14" H 6200 4400 20 0000 C CNN +F 1 "+VCCO_3V3" H 6200 4330 30 0000 C CNN +F 2 "" H 6200 4400 70 0000 C CNN +F 3 "" H 6200 4400 70 0000 C CNN + 1 6200 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6800 5800 6800 6500 +Wire Wire Line + 7000 5800 6800 5800 +Wire Wire Line + 9700 6200 9700 6500 +Wire Wire Line + 6200 4400 6200 4700 +Wire Wire Line + 8700 5500 8450 5500 +Wire Wire Line + 8700 4700 8700 5500 +Wire Wire Line + 7000 4700 6500 4700 +Wire Wire Line + 8700 4700 7000 4700 +Wire Wire Line + 6500 4700 6200 4700 +Wire Wire Line + 8700 5600 8450 5600 +Wire Wire Line + 8700 5500 8700 5600 +Wire Wire Line + 9700 5600 9700 5900 +Wire Wire Line + 9700 5600 8700 5600 +Wire Wire Line + 7000 4700 7000 4900 +Wire Wire Line + 6200 4700 6200 4900 +Connection ~ 8700 5500 +Connection ~ 8700 5600 +Connection ~ 7000 4700 +Connection ~ 6200 4700 +Wire Wire Line + 7000 5500 6500 5500 +Wire Wire Line + 7000 5300 7000 5500 +Wire Wire Line + 6500 5500 6270 5500 +Text GLabel 6270 5500 0 48 Input ~ 0 +KSM_PROM_CS_N +Connection ~ 7000 5500 +Wire Wire Line + 8600 5800 8450 5800 +Text GLabel 8600 5800 2 48 Input ~ 0 +KSM_PROM_MOSI +Wire Wire Line + 8600 5700 8450 5700 +Text GLabel 8600 5700 2 48 Input ~ 0 +KSM_PROM_SCLK +Wire Wire Line + 7000 5600 6270 5600 +Text GLabel 6270 5600 0 48 Output ~ 0 +KSM_PROM_MISO +Wire Wire Line + 7000 5700 6200 5700 +Wire Wire Line + 6200 5300 6200 5700 +$Comp +L Cryptech_Alpha:N25Q128A13ES IC1 +U 1 1 5802402B +P 7700 5750 +F 0 "IC1" H 7190 5490 60 0000 L BNN +F 1 "N25Q128A13ESE*" H 7470 6120 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO08" H 7470 6120 60 0001 C CNN +F 3 "" H 7470 6120 60 0000 C CNN + 1 7700 5750 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R18 +U 1 1 5802402A +P 7000 5100 +F 0 "R18" V 6941 5250 60 0000 L BNN +F 1 "4.7k" V 7040 5240 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 7040 5240 60 0001 C CNN +F 3 "" H 7040 5240 60 0000 C CNN + 1 7000 5100 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C69 +U 1 1 58024029 +P 9700 6000 +F 0 "C69" H 9780 5810 60 0000 L BNN +F 1 "0.1uF" H 9990 6010 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 9990 6010 60 0001 C CNN +F 3 "" H 9990 6010 60 0000 C CNN + 1 9700 6000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R17 +U 1 1 58024028 +P 6200 5100 +F 0 "R17" V 6140 4780 60 0000 L BNN +F 1 "4.7k" V 6250 4780 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6250 4780 60 0001 C CNN +F 3 "" H 6250 4780 60 0000 C CNN + 1 6200 5100 + 0 1 1 0 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_08.sch b/KiCAD/rev02_08.sch new file mode 100644 index 0000000..751c30d --- /dev/null +++ b/KiCAD/rev02_08.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 10 27 +Title "rev02_08" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6860 5660 0 60 ~ 12 +CL 12.5 pF +Text Notes 8800 6200 0 60 ~ 12 +MFP is Multi Function Pin.\nGPIO output from RTC. +Text Notes 8400 4600 0 60 ~ 12 +i2c pull-ups, typically 10K for 100kHz +Text Notes 6200 3400 0 126 ~ 12 +Real Time Clock +Text Notes 13730 10220 0 84 ~ 12 +Real Time Clock +Text Notes 7600 5060 0 60 ~ 12 +U7 +Text Notes 7600 5180 0 60 ~ 12 +MCP79412-I_SN +Text Notes 6240 6640 0 60 ~ 12 +X1 +Text Notes 6250 6200 0 60 ~ 12 +XTAL-3.2X1.5 +$Comp +L power:GND GND_46 +U 1 1 58024027 +P 7200 6400 +F 0 "GND_46" H 7200 6400 20 0000 C CNN +F 1 "+GND" H 7200 6330 30 0000 C CNN +F 2 "" H 7200 6400 70 0000 C CNN +F 3 "" H 7200 6400 70 0000 C CNN + 1 7200 6400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_2 +U 1 1 58024026 +P 6900 4800 +F 0 "3V3_BATT_2" H 6900 4800 20 0000 C CNN +F 1 "+3V3_BATT" H 6900 4730 30 0000 C CNN +F 2 "" H 6900 4800 70 0000 C CNN +F 3 "" H 6900 4800 70 0000 C CNN + 1 6900 4800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_15 +U 1 1 58024025 +P 7400 4800 +F 0 "VCCO_3V3_15" H 7400 4800 20 0000 C CNN +F 1 "+VCCO_3V3" H 7400 4730 30 0000 C CNN +F 2 "" H 7400 4800 70 0000 C CNN +F 3 "" H 7400 4800 70 0000 C CNN + 1 7400 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_47 +U 1 1 58024024 +P 6100 6400 +F 0 "GND_47" H 6100 6400 20 0000 C CNN +F 1 "+GND" H 6100 6330 30 0000 C CNN +F 2 "" H 6100 6400 70 0000 C CNN +F 3 "" H 6100 6400 70 0000 C CNN + 1 6100 6400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_48 +U 1 1 58024023 +P 6700 6400 +F 0 "GND_48" H 6700 6400 20 0000 C CNN +F 1 "+GND" H 6700 6330 30 0000 C CNN +F 2 "" H 6700 6400 70 0000 C CNN +F 3 "" H 6700 6400 70 0000 C CNN + 1 6700 6400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 4800 6900 5500 +Wire Wire Line + 7400 5500 6900 5500 +Wire Wire Line + 7400 6000 7200 6000 +Wire Wire Line + 7200 6000 7200 6400 +Wire Wire Line + 6700 6300 6700 6400 +Wire Wire Line + 6100 6300 6100 6400 +Wire Wire Line + 7400 4800 7400 5400 +Wire Wire Line + 6200 6000 6100 6000 +Wire Wire Line + 7400 5700 6100 5700 +Wire Wire Line + 6100 5700 6100 6000 +Connection ~ 6100 6000 +Wire Wire Line + 6700 6000 6600 6000 +Wire Wire Line + 7400 5800 6700 5800 +Wire Wire Line + 6700 5800 6700 6000 +Connection ~ 6700 6000 +Wire Wire Line + 9300 5500 8600 5500 +Wire Wire Line + 9500 5500 9300 5500 +Wire Wire Line + 9300 5400 9300 5500 +Text GLabel 9500 5500 2 48 UnSpc ~ 0 +RTC_MFP +Connection ~ 9300 5500 +Wire Wire Line + 9100 5600 8600 5600 +Wire Wire Line + 9500 5600 9100 5600 +Wire Wire Line + 9100 5400 9100 5600 +Text GLabel 9500 5600 2 48 Input ~ 0 +RTC_SCL +Connection ~ 9100 5600 +Wire Wire Line + 8900 5700 8600 5700 +Wire Wire Line + 9500 5700 8900 5700 +Wire Wire Line + 8900 5400 8900 5700 +Text GLabel 9500 5700 2 48 BiDi ~ 0 +RTC_SDA +Connection ~ 8900 5700 +Wire Wire Line + 9100 4800 9100 4900 +Wire Wire Line + 9100 4900 9100 5000 +Wire Wire Line + 8900 4900 8900 5000 +Wire Wire Line + 9100 4900 8900 4900 +Wire Wire Line + 9300 4900 9100 4900 +Wire Wire Line + 9300 4900 9300 5000 +Connection ~ 9100 4900 +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_16 +U 1 1 58024022 +P 9100 4800 +F 0 "VCCO_3V3_16" H 9100 4800 20 0000 C CNN +F 1 "+VCCO_3V3" H 9100 4730 30 0000 C CNN +F 2 "" H 9100 4800 70 0000 C CNN +F 3 "" H 9100 4800 70 0000 C CNN + 1 9100 4800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:MCP79412-I_SN U7 +U 1 1 58024021 +P 8000 5600 +F 0 "U7" H 7570 4870 60 0000 L BNN +F 1 "MCP79412-I_SN" H 7580 6030 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SOIC127P600X175-8N" H 7580 6030 60 0001 C CNN +F 3 "" H 7580 6030 60 0000 C CNN + 1 8000 5600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C71 +U 1 1 58024020 +P 6700 6200 +F 0 "C71" H 6570 6110 60 0000 R TNN +F 1 "5pF" H 6570 6200 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6570 6200 60 0001 C CNN +F 3 "" H 6570 6200 60 0000 C CNN + 1 6700 6200 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C70 +U 1 1 5802401F +P 6100 6200 +F 0 "C70" H 6440 6120 60 0000 R TNN +F 1 "5pF" H 6440 6220 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6440 6220 60 0001 C CNN +F 3 "" H 6440 6220 60 0000 C CNN + 1 6100 6200 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:XTAL-3.2X1.5 X1 +U 1 1 5802401E +P 6400 6000 +F 0 "X1" H 6290 5790 60 0000 L BNN +F 1 "ABS07-32.768KHZ-T" H 6230 5250 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:XTAL3215" H 6230 5250 60 0001 C CNN +F 3 "" H 6230 5250 60 0000 C CNN + 1 6400 6000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R21 +U 1 1 5802401D +P 9300 5200 +F 0 "R21" V 9300 5500 60 0000 L BNN +F 1 "10k" V 9290 5700 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9290 5700 60 0001 C CNN +F 3 "" H 9290 5700 60 0000 C CNN + 1 9300 5200 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R20 +U 1 1 5802401C +P 9100 5200 +F 0 "R20" V 9000 5700 60 0000 L BNN +F 1 "10k" V 8990 5900 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8990 5900 60 0001 C CNN +F 3 "" H 8990 5900 60 0000 C CNN + 1 9100 5200 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R19 +U 1 1 5802401B +P 8900 5200 +F 0 "R19" V 8700 5900 60 0000 L BNN +F 1 "10k" V 8690 6110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8690 6110 60 0001 C CNN +F 3 "" H 8690 6110 60 0000 C CNN + 1 8900 5200 + 0 1 1 0 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_09.sch b/KiCAD/rev02_09.sch new file mode 100644 index 0000000..c9aff59 --- /dev/null +++ b/KiCAD/rev02_09.sch @@ -0,0 +1,1098 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 11 27 +Title "rev02_09" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 5000 2800 0 60 ~ 12 +DS_FT232H.pdf\n6.1 USB Bus Powered Configuration\ncopy of reference circuit +Text Notes 7750 7350 0 42 ~ 12 +Place close to FT232 +Text Notes 5490 5650 0 60 ~ 12 +CL 10pF +Text Notes 6200 1700 0 126 ~ 12 +Application access USB UART +Text Notes 13630 10230 0 84 ~ 12 +USB-UART interface +Text Notes 13700 5900 0 60 ~ 12 +If possible, line up with\ncorresponding header\nfor MGMT USB-UART and\nlabel pins on silk screen +Text Notes 7290 3180 0 60 ~ 12 +U8 +Text Notes 7900 4800 0 60 ~ 12 +FT232H_SERIAL +Text Notes 6830 4060 2 60 ~ 12 +R23 +Text Notes 7850 7630 0 60 ~ 12 +FB2 +Text Notes 7640 7870 0 60 ~ 12 +600R~500mA +Text Notes 6050 7630 0 60 ~ 12 +FB1 +Text Notes 5840 7860 0 60 ~ 12 +600R~500mA +Text Notes 3030 3280 0 60 ~ 12 +IC5 +Text Notes 2800 3900 0 60 ~ 12 +RCLAMP0502ASC-89 +Text Notes 12730 5990 0 60 ~ 12 +1 +Text Notes 13030 5990 0 60 ~ 12 +2 +Text Notes 12730 6090 0 60 ~ 12 +3 +Text Notes 13030 6090 0 60 ~ 12 +4 +Text Notes 12730 6190 0 60 ~ 12 +5 +Text Notes 13030 6190 0 60 ~ 12 +6 +$Comp +L power:GND GND_49 +U 1 1 5802401A +P 6100 4600 +F 0 "GND_49" H 6100 4600 20 0000 C CNN +F 1 "+GND" H 6100 4530 30 0000 C CNN +F 2 "" H 6100 4600 70 0000 C CNN +F 3 "" H 6100 4600 70 0000 C CNN + 1 6100 4600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_50 +U 1 1 58024019 +P 8400 6200 +F 0 "GND_50" H 8400 6200 20 0000 C CNN +F 1 "+GND" H 8400 6130 30 0000 C CNN +F 2 "" H 8400 6200 70 0000 C CNN +F 3 "" H 8400 6200 70 0000 C CNN + 1 8400 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_51 +U 1 1 58024018 +P 7300 6200 +F 0 "GND_51" H 7300 6200 20 0000 C CNN +F 1 "+GND" H 7300 6130 30 0000 C CNN +F 2 "" H 7300 6200 70 0000 C CNN +F 3 "" H 7300 6200 70 0000 C CNN + 1 7300 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_52 +U 1 1 58024017 +P 6000 6200 +F 0 "GND_52" H 6000 6200 20 0000 C CNN +F 1 "+GND" H 6000 6130 30 0000 C CNN +F 2 "" H 6000 6200 70 0000 C CNN +F 3 "" H 6000 6200 70 0000 C CNN + 1 6000 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_53 +U 1 1 58024016 +P 6600 6200 +F 0 "GND_53" H 6600 6200 20 0000 C CNN +F 1 "+GND" H 6600 6130 30 0000 C CNN +F 2 "" H 6600 6200 70 0000 C CNN +F 3 "" H 6600 6200 70 0000 C CNN + 1 6600 6200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 FT_VCC3V3 +U 1 1 58024015 +P 8500 2500 +F 0 "FT_VCC3V3" H 8500 2500 20 0000 C CNN +F 1 "+FT_VCC3V3" H 8500 2430 30 0000 C CNN +F 2 "" H 8500 2500 70 0000 C CNN +F 3 "" H 8500 2500 70 0000 C CNN + 1 8500 2500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_54 +U 1 1 58024014 +P 4900 8400 +F 0 "GND_54" H 4900 8400 20 0000 C CNN +F 1 "+GND" H 4900 8330 30 0000 C CNN +F 2 "" H 4900 8400 70 0000 C CNN +F 3 "" H 4900 8400 70 0000 C CNN + 1 4900 8400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_55 +U 1 1 58024013 +P 10100 8400 +F 0 "GND_55" H 10100 8400 20 0000 C CNN +F 1 "+GND" H 10100 8330 30 0000 C CNN +F 2 "" H 10100 8400 70 0000 C CNN +F 3 "" H 10100 8400 70 0000 C CNN + 1 10100 8400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_56 +U 1 1 58024012 +P 6900 8400 +F 0 "GND_56" H 6900 8400 20 0000 C CNN +F 1 "+GND" H 6900 8330 30 0000 C CNN +F 2 "" H 6900 8400 70 0000 C CNN +F 3 "" H 6900 8400 70 0000 C CNN + 1 6900 8400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_57 +U 1 1 58024011 +P 8700 8400 +F 0 "GND_57" H 8700 8400 20 0000 C CNN +F 1 "+GND" H 8700 8330 30 0000 C CNN +F 2 "" H 8700 8400 70 0000 C CNN +F 3 "" H 8700 8400 70 0000 C CNN + 1 8700 8400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_58 +U 1 1 58024010 +P 11500 8400 +F 0 "GND_58" H 11500 8400 20 0000 C CNN +F 1 "+GND" H 11500 8330 30 0000 C CNN +F 2 "" H 11500 8400 70 0000 C CNN +F 3 "" H 11500 8400 70 0000 C CNN + 1 11500 8400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 FT_VCC3V3_2 +U 1 1 5802400F +P 11500 7300 +F 0 "FT_VCC3V3_2" H 11500 7300 20 0000 C CNN +F 1 "+FT_VCC3V3" H 11500 7230 30 0000 C CNN +F 2 "" H 11500 7300 70 0000 C CNN +F 3 "" H 11500 7300 70 0000 C CNN + 1 11500 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_59 +U 1 1 5802400E +P 2150 3850 +F 0 "GND_59" H 2150 3850 20 0000 C CNN +F 1 "+GND" H 2150 3780 30 0000 C CNN +F 2 "" H 2150 3850 70 0000 C CNN +F 3 "" H 2150 3850 70 0000 C CNN + 1 2150 3850 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 FT_VCC3V3_3 +U 1 1 5802400D +P 9800 7300 +F 0 "FT_VCC3V3_3" H 9800 7300 20 0000 C CNN +F 1 "+FT_VCC3V3" H 9800 7230 30 0000 C CNN +F 2 "" H 9800 7300 70 0000 C CNN +F 3 "" H 9800 7300 70 0000 C CNN + 1 9800 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VREGIN FT_VREGIN +U 1 1 5802400C +P 4600 7300 +F 0 "FT_VREGIN" H 4600 7300 20 0000 C CNN +F 1 "+FT_VREGIN" H 4600 7230 30 0000 C CNN +F 2 "" H 4600 7300 70 0000 C CNN +F 3 "" H 4600 7300 70 0000 C CNN + 1 4600 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 FT_VCC3V3_4 +U 1 1 5802400B +P 5900 7300 +F 0 "FT_VCC3V3_4" H 5900 7300 20 0000 C CNN +F 1 "+FT_VCC3V3" H 5900 7230 30 0000 C CNN +F 2 "" H 5900 7300 70 0000 C CNN +F 3 "" H 5900 7300 70 0000 C CNN + 1 5900 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VPHY FT_VPHY +U 1 1 5802400A +P 6900 7300 +F 0 "FT_VPHY" H 6900 7300 20 0000 C CNN +F 1 "+FT_VPHY" H 6900 7230 30 0000 C CNN +F 2 "" H 6900 7300 70 0000 C CNN +F 3 "" H 6900 7300 70 0000 C CNN + 1 6900 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 FT_VCC3V3_5 +U 1 1 58024009 +P 7700 7300 +F 0 "FT_VCC3V3_5" H 7700 7300 20 0000 C CNN +F 1 "+FT_VCC3V3" H 7700 7230 30 0000 C CNN +F 2 "" H 7700 7300 70 0000 C CNN +F 3 "" H 7700 7300 70 0000 C CNN + 1 7700 7300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VPLL FT_VPLL +U 1 1 58024008 +P 8700 7300 +F 0 "FT_VPLL" H 8700 7300 20 0000 C CNN +F 1 "+FT_VPLL" H 8700 7230 30 0000 C CNN +F 2 "" H 8700 7300 70 0000 C CNN +F 3 "" H 8700 7300 70 0000 C CNN + 1 8700 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_60 +U 1 1 58024007 +P 3900 3900 +F 0 "GND_60" H 3900 3900 20 0000 C CNN +F 1 "+GND" H 3900 3830 30 0000 C CNN +F 2 "" H 3900 3900 70 0000 C CNN +F 3 "" H 3900 3900 70 0000 C CNN + 1 3900 3900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_VREGIN FT_VREGIN_2 +U 1 1 58024006 +P 13300 5400 +F 0 "FT_VREGIN_2" H 13300 5400 20 0000 C CNN +F 1 "+FT_VREGIN" H 13300 5330 30 0000 C CNN +F 2 "" H 13300 5400 70 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3100 +Wire Wire Line + 8200 2800 7550 2800 +Text Label 7550 2800 0 48 ~ +FT_VPHY +Wire Wire Line + 6900 7700 6400 7700 +Wire Wire Line + 6900 7700 6900 7900 +Wire Wire Line + 6400 7700 6400 7900 +Wire Wire Line + 6900 7300 6900 7700 +Wire Wire Line + 6400 7700 6200 7700 +Connection ~ 6400 7700 +Connection ~ 6900 7700 +Wire Wire Line + 8300 2600 8300 3100 +Wire Wire Line + 8300 2600 7550 2600 +Text Label 7550 2600 0 48 ~ +FT_VPLL +Wire Wire Line + 8700 7700 8200 7700 +Wire Wire Line + 8700 7700 8700 7900 +Wire Wire Line + 8200 7700 8200 7900 +Wire Wire Line + 8700 7300 8700 7700 +Wire Wire Line + 8200 7700 8000 7700 +Connection ~ 8200 7700 +Connection ~ 8700 7700 +Wire Wire Line + 9700 3600 9500 3600 +Text GLabel 9700 3600 2 48 Output ~ 0 +FT_RTS +Wire Wire Line + 9700 3700 9500 3700 +Text GLabel 9700 3700 2 48 Input ~ 0 +FT_CTS +Wire Wire Line + 9700 3800 9500 3800 +Text GLabel 9700 3800 2 48 UnSpc ~ 0 +FT_DTR +Wire Wire Line + 2600 3400 2000 3400 +Wire Wire Line + 2300 3500 2000 3500 +Wire Wire Line + 2300 3500 2300 3600 +Wire Wire Line + 2600 3600 2300 3600 +Wire Wire Line + 10500 3400 9500 3400 +Text Label 9800 3400 0 48 ~ +FT_TXD1 +Wire Wire Line + 13400 6200 13200 6200 +Text Label 13400 6200 0 48 ~ 0 +FT_TXD1 +Wire Wire Line + 10500 3500 9500 3500 +Text Label 9800 3500 0 48 ~ +FT_RXD1 +Wire Wire Line + 12600 6200 12400 6200 +Text Label 12400 6200 0 48 ~ +FT_RXD1 +Wire Wire Line + 13300 5600 13300 6000 +Wire Wire Line + 13300 5400 13300 5600 +Wire Wire Line + 13300 5600 12350 5600 +Wire Wire Line + 13300 6000 13200 6000 +Connection ~ 13300 5600 +Wire Wire Line + 11000 2500 11000 2700 +Text Label 7090 4000 0 48 ~ +USB_N +Text Label 7090 4100 0 48 ~ +USB_P +Text Label 13400 6100 0 48 ~ 0 +USB_N +Text Label 12400 6100 0 48 ~ +USB_P +Text Label 2050 3400 0 60 ~ +D1_P +Text Label 2050 3500 0 60 ~ +D1_N +$Comp +L Cryptech_Alpha:FT_VREGIN FT_VREGIN_3 +U 1 1 58024003 +P 2500 3300 +F 0 "FT_VREGIN_3" H 2500 3300 20 0000 C CNN +F 1 "+FT_VREGIN" H 2500 3230 30 0000 C CNN +F 2 "" H 2500 3300 70 0000 C CNN +F 3 "" H 2500 3300 70 0000 C CNN + 1 2500 3300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_62 +U 1 1 58024002 +P 6200 5700 +F 0 "GND_62" H 6200 5700 20 0000 C CNN +F 1 "+GND" H 6200 5630 30 0000 C CNN +F 2 "" H 6200 5700 70 0000 C CNN +F 3 "" H 6200 5700 70 0000 C CNN + 1 6200 5700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_63 +U 1 1 58024001 +P 6400 5700 +F 0 "GND_63" H 6400 5700 20 0000 C CNN +F 1 "+GND" H 6400 5630 30 0000 C CNN +F 2 "" H 6400 5700 70 0000 C CNN +F 3 "" H 6400 5700 70 0000 C CNN + 1 6400 5700 + 1 0 0 -1 +$EndComp +Connection ~ 2500 3300 +Connection ~ 6570 3600 +$Comp +L Cryptech_Alpha:FT232H_SERIAL U8 +U 1 1 58024000 +P 8400 4600 +F 0 "U8" H 9520 5810 60 0000 L BNN +F 1 "FT232HL-REEL" H 7280 6120 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:LQFP-48" H 7280 6120 60 0001 C CNN +F 3 "" H 7280 6120 60 0000 C CNN + 1 8400 4600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C82 +U 1 1 58023FFF +P 9800 8000 +F 0 "C82" H 9513 8084 60 0000 L BNN +F 1 "4.7uF" H 9510 7990 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 9510 7990 60 0001 C CNN +F 3 "" H 9510 7990 60 0000 C CNN + 1 9800 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C83 +U 1 1 58023FFE +P 10100 8000 +F 0 "C83" H 10200 8100 60 0000 L BNN +F 1 "0.1uF" H 10210 8010 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10210 8010 60 0001 C CNN +F 3 "" H 10210 8010 60 0000 C CNN + 1 10100 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C79 +U 1 1 58023FFD +P 6900 8000 +F 0 "C79" H 7000 7900 60 0000 L BNN +F 1 "0.1uF" H 7000 7820 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7000 7820 60 0001 C CNN +F 3 "" H 7000 7820 60 0000 C CNN + 1 6900 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C77 +U 1 1 58023FFC +P 6400 8000 +F 0 "C77" H 6113 7884 60 0000 L BNN +F 1 "10uF" H 6070 7790 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 6070 7790 60 0001 C CNN +F 3 "" H 6070 7790 60 0000 C CNN + 1 6400 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C81 +U 1 1 58023FFB +P 8700 8000 +F 0 "C81" H 8800 7900 60 0000 L BNN +F 1 "0.1uF" H 8800 7820 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 8800 7820 60 0001 C CNN +F 3 "" H 8800 7820 60 0000 C CNN + 1 8700 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C80 +U 1 1 58023FFA +P 8200 8000 +F 0 "C80" H 7913 7934 60 0000 L BNN +F 1 "10uF" H 7880 7840 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 7880 7840 60 0001 C CNN +F 3 "" H 7880 7840 60 0000 C CNN + 1 8200 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C84 +U 1 1 58023FF9 +P 11100 8000 +F 0 "C84" H 10762 7915 60 0000 L BNN +F 1 "0.1uF" H 10750 7820 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10750 7820 60 0001 C CNN +F 3 "" H 10750 7820 60 0000 C CNN + 1 11100 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C85 +U 1 1 58023FF8 +P 11500 8000 +F 0 "C85" H 11220 8110 60 0000 L BNN +F 1 "0.1uF" H 11210 8020 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11210 8020 60 0001 C CNN +F 3 "" H 11210 8020 60 0000 C CNN + 1 11500 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C86 +U 1 1 58023FF7 +P 11900 8000 +F 0 "C86" H 12000 7900 60 0000 L BNN +F 1 "0.1uF" H 12000 7820 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12000 7820 60 0001 C CNN +F 3 "" H 12000 7820 60 0000 C CNN + 1 11900 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FERRITE_0603MP FB2 +U 1 1 58023FF6 +P 7900 7700 +F 0 "FB2" H 7820 7532 60 0000 L BNN + 1 7900 7700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:L_0603" H 7820 7532 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R23 +U 1 1 58023FF5 +P 6770 4300 +F 0 "R23" H 6880 4445 60 0000 R TNN +F 1 "10k" H 6880 4240 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6880 4240 60 0001 C CNN +F 3 "" H 6880 4240 60 0000 C CNN + 1 6770 4300 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:FERRITE_0603MP FB1 +U 1 1 58023FF4 +P 6100 7700 +F 0 "FB1" H 6020 7532 60 0000 L BNN + 1 6100 7700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:L_0603" H 6020 7532 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:USBMINIB CN1 +U 1 1 58023FF3 +P 1600 3500 +F 0 "CN1" H 1188 3090 60 0000 L BNN +F 1 "690-005-299-043" H 1188 3810 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:USB-MINIB" H 1188 3810 60 0001 C CNN +F 3 "" H 1188 3810 60 0000 C CNN + 1 1600 3500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:RCLAMP0502ASC-89 IC5 +U 1 1 58023FF2 +P 3100 3500 +F 0 "IC5" H 2690 3190 60 0000 L BNN +F 1 "RCLAMP0502A.TCT" H 2700 3170 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:RCLAMP0502A" H 2700 3170 60 0001 C CNN +F 3 "" H 2700 3170 60 0000 C CNN + 1 3100 3500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R86 +U 1 1 58023FF1 +P 10700 3400 +F 0 "R86" H 10797 3170 60 0000 R TNN +F 1 "100" H 10780 3270 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10780 3270 60 0001 C CNN +F 3 "" H 10780 3270 60 0000 C CNN + 1 10700 3400 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R87 +U 1 1 58023FF0 +P 10700 3500 +F 0 "R87" H 10840 3660 60 0000 R TNN +F 1 "100" H 10840 3750 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10840 3750 60 0001 C CNN +F 3 "" H 10840 3750 60 0000 C CNN + 1 10700 3500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:M03X2NO_SILK J2 +U 1 1 58023FEF +P 12900 6100 +F 0 "J2" H 12690 5790 60 0000 L BNN + 1 12900 6100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 12690 5790 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C214 +U 1 1 58023FEE +P 12350 5700 +F 0 "C214" H 11950 5600 60 0000 L BNN +F 1 "0.1uF" H 11950 5500 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11950 5500 60 0001 C CNN +F 3 "" H 11950 5500 60 0000 C CNN + 1 12350 5700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R91 +U 1 1 58023FED +P 11000 2900 +F 0 "R91" V 10900 3000 60 0000 L BNN +F 1 "10k" V 10990 3000 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10990 3000 60 0001 C CNN +F 3 "" H 10990 3000 60 0000 C CNN + 1 11000 2900 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:CRYSTALTHIN Y1 +U 1 1 58023FEC +P 6300 5600 +F 0 "Y1" H 6400 5720 60 0000 R BNN +F 1 "ABM8G-12.000MHZ-4Y-T3" H 5480 5740 60 0000 R BNN +F 2 "Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5" H 5480 5740 60 0001 C CNN +F 3 "" H 5480 5740 60 0000 C CNN + 1 6300 5600 + -1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C76 +U 1 1 58023FEB +P 6200 4100 +F 0 "C76" H 6300 4100 60 0000 L BNN +F 1 "0.1uF" H 6310 4000 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6310 4000 60 0001 C CNN +F 3 "" H 6310 4000 60 0000 C CNN + 1 6200 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C74 +U 1 1 58023FEA +P 6000 4100 +F 0 "C74" H 5660 4100 60 0000 L BNN +F 1 "0.1uF" H 5640 3990 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5640 3990 60 0001 C CNN +F 3 "" H 5640 3990 60 0000 C CNN + 1 6000 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R22 +U 1 1 58023FE9 +P 6600 4500 +F 0 "R22" H 6700 4660 60 0000 R TNN +F 1 "12k" H 6710 4750 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6710 4750 60 0001 C CNN +F 3 "" H 6710 4750 60 0000 C CNN + 1 6600 4500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C78 +U 1 1 58023FE8 +P 6600 5900 +F 0 "C78" H 6500 5900 60 0000 R TNN +F 1 "5pF" H 6480 6000 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6480 6000 60 0001 C CNN +F 3 "" H 6480 6000 60 0000 C CNN + 1 6600 5900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C75 +U 1 1 58023FE7 +P 6000 5900 +F 0 "C75" H 6300 5900 60 0000 R TNN +F 1 "5pF" H 6290 6000 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6290 6000 60 0001 C CNN +F 3 "" H 6290 6000 60 0000 C CNN + 1 6000 5900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C72 +U 1 1 58023FE6 +P 4600 8000 +F 0 "C72" H 4313 8084 60 0000 L BNN +F 1 "4.7uF" H 4310 8000 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4310 8000 60 0001 C CNN +F 3 "" H 4310 8000 60 0000 C CNN + 1 4600 8000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C73 +U 1 1 58023FE5 +P 4900 8000 +F 0 "C73" H 5000 8100 60 0000 L BNN +F 1 "0.1uF" H 4990 8020 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4990 8020 60 0001 C CNN +F 3 "" H 4990 8020 60 0000 C CNN + 1 4900 8000 + 1 0 0 -1 +$EndComp +NoConn ~ 9500 3900 +NoConn ~ 9500 4000 +NoConn ~ 9500 4100 +NoConn ~ 9500 4300 +NoConn ~ 9500 4400 +NoConn ~ 9500 4500 +NoConn ~ 9500 4600 +NoConn ~ 9500 4700 +NoConn ~ 9500 4800 +NoConn ~ 9500 4900 +NoConn ~ 9500 5000 +NoConn ~ 9500 5100 +NoConn ~ 9500 5200 +NoConn ~ 7300 5100 +NoConn ~ 7300 5000 +NoConn ~ 7300 4900 +NoConn ~ 2000 3600 +$Comp +L Cryptech_Alpha:FT_VPLL #PWR? +U 1 1 5AF3BF7C +P 7550 2600 +F 0 "#PWR?" H 7550 2450 50 0001 C CNN +F 1 "FT_VPLL" V 7565 2727 50 0000 L CNN +F 2 "" H 7550 2600 60 0000 C CNN +F 3 "" H 7550 2600 60 0000 C CNN + 1 7550 2600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 #PWR? +U 1 1 5AF3CDAF +P 6000 3600 +F 0 "#PWR?" H 6000 3450 50 0001 C CNN +F 1 "FT_VCC3V3" V 6015 3728 50 0000 L CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 1 6000 3600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VREGIN #PWR? +U 1 1 5AF3DC52 +P 6000 3400 +F 0 "#PWR?" H 6000 3250 50 0001 C CNN +F 1 "FT_VREGIN" V 6015 3527 50 0000 L CNN +F 2 "" H 6000 3400 60 0000 C CNN +F 3 "" H 6000 3400 60 0000 C CNN + 1 6000 3400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VPHY #PWR? +U 1 1 5AF3EA0F +P 7550 2800 +F 0 "#PWR?" H 7550 2650 50 0001 C CNN +F 1 "FT_VPHY" V 7565 2927 50 0000 L CNN +F 2 "" H 7550 2800 60 0000 C CNN +F 3 "" H 7550 2800 60 0000 C CNN + 1 7550 2800 + 0 -1 -1 0 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAEA32 +P 8200 7700 +F 0 "#FLG?" H 8200 7775 50 0001 C CNN +F 1 "PWR_FLAG" H 8200 7874 50 0000 C CNN +F 2 "" H 8200 7700 50 0001 C CNN +F 3 "~" H 8200 7700 50 0001 C CNN + 1 8200 7700 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAEB88 +P 6400 7700 +F 0 "#FLG?" H 6400 7775 50 0001 C CNN +F 1 "PWR_FLAG" H 6400 7874 50 0000 C CNN +F 2 "" H 6400 7700 50 0001 C CNN +F 3 "~" H 6400 7700 50 0001 C CNN + 1 6400 7700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_10.sch b/KiCAD/rev02_10.sch new file mode 100644 index 0000000..f4d9532 --- /dev/null +++ b/KiCAD/rev02_10.sch @@ -0,0 +1,1102 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 12 27 +Title "rev02_10" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 5100 2900 0 60 ~ 12 +DS_FT232H.pdf\n6.1 USB Bus Powered Configuration\ncopy of reference circuit +Text Notes 7850 7450 0 42 ~ 12 +Place close to FT232 +Text Notes 5610 5750 0 60 ~ 12 +CL 10pF +Text Notes 6200 1800 0 126 ~ 12 +Management access USB UART +Text Notes 13890 10220 0 84 ~ 12 +MGMT USB-UART +Text Notes 14090 6010 0 60 ~ 12 +If possible, line up with\ncorresponding header\nfor USB-UART and label\npins on silk screen +Text Notes 8000 4700 0 60 ~ 12 +U9 +Text Notes 8000 4900 0 60 ~ 12 +FT232H_SERIAL +Text Notes 6880 4190 2 60 ~ 12 +R27 +Text Notes 6360 4190 0 60 ~ 12 +C91 +Text Notes 6360 4390 0 60 ~ 12 +0.1~uF +Text Notes 7950 7730 0 60 ~ 12 +FB4 +Text Notes 7740 7960 0 60 ~ 12 +600R~500mA +Text Notes 6150 7730 0 60 ~ 12 +FB3 +Text Notes 5930 7960 0 60 ~ 12 +600R~500mA +Text Notes 3110 3390 0 60 ~ 12 +IC6 +Text Notes 2900 4000 0 60 ~ 12 +RCLAMP0502ASC-89 +Text Notes 12830 6090 0 60 ~ 12 +1 +Text Notes 13130 6090 0 60 ~ 12 +2 +Text Notes 12830 6190 0 60 ~ 12 +3 +Text Notes 13130 6190 0 60 ~ 12 +4 +Text Notes 12830 6290 0 60 ~ 12 +5 +Text Notes 13130 6290 0 60 ~ 12 +6 +$Comp +L power:GND GND_64 +U 1 1 58023FE4 +P 6200 4700 +F 0 "GND_64" H 6200 4700 20 0000 C CNN +F 1 "+GND" H 6200 4630 30 0000 C CNN +F 2 "" H 6200 4700 70 0000 C CNN +F 3 "" H 6200 4700 70 0000 C CNN + 1 6200 4700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_65 +U 1 1 58023FE3 +P 8700 6300 +F 0 "GND_65" H 8700 6300 20 0000 C CNN +F 1 "+GND" H 8700 6230 30 0000 C CNN +F 2 "" H 8700 6300 70 0000 C CNN +F 3 "" H 8700 6300 70 0000 C CNN + 1 8700 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_66 +U 1 1 58023FE2 +P 7400 6300 +F 0 "GND_66" H 7400 6300 20 0000 C CNN +F 1 "+GND" H 7400 6230 30 0000 C CNN +F 2 "" H 7400 6300 70 0000 C CNN +F 3 "" H 7400 6300 70 0000 C CNN + 1 7400 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_67 +U 1 1 58023FE1 +P 6100 6300 +F 0 "GND_67" H 6100 6300 20 0000 C CNN +F 1 "+GND" H 6100 6230 30 0000 C CNN +F 2 "" H 6100 6300 70 0000 C CNN +F 3 "" H 6100 6300 70 0000 C CNN + 1 6100 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_68 +U 1 1 58023FE0 +P 6700 6300 +F 0 "GND_68" H 6700 6300 20 0000 C CNN +F 1 "+GND" H 6700 6230 30 0000 C CNN +F 2 "" H 6700 6300 70 0000 C CNN +F 3 "" H 6700 6300 70 0000 C CNN + 1 6700 6300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 FT_MGMT_VCC3V3 +U 1 1 58023FDF +P 8600 2600 +F 0 "FT_MGMT_VCC3V3" H 8600 2600 20 0000 C CNN +F 1 "+FT_MGMT_VCC3V3" H 8600 2530 30 0000 C CNN +F 2 "" H 8600 2600 70 0000 C CNN +F 3 "" H 8600 2600 70 0000 C CNN + 1 8600 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_69 +U 1 1 58023FDE +P 5000 8500 +F 0 "GND_69" H 5000 8500 20 0000 C CNN +F 1 "+GND" H 5000 8430 30 0000 C CNN +F 2 "" H 5000 8500 70 0000 C CNN +F 3 "" H 5000 8500 70 0000 C CNN + 1 5000 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_70 +U 1 1 58023FDD +P 10200 8500 +F 0 "GND_70" H 10200 8500 20 0000 C CNN +F 1 "+GND" H 10200 8430 30 0000 C CNN +F 2 "" H 10200 8500 70 0000 C CNN +F 3 "" H 10200 8500 70 0000 C CNN + 1 10200 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_71 +U 1 1 58023FDC +P 7000 8500 +F 0 "GND_71" H 7000 8500 20 0000 C CNN +F 1 "+GND" H 7000 8430 30 0000 C CNN +F 2 "" H 7000 8500 70 0000 C CNN +F 3 "" H 7000 8500 70 0000 C CNN + 1 7000 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_72 +U 1 1 58023FDB +P 8800 8500 +F 0 "GND_72" H 8800 8500 20 0000 C CNN +F 1 "+GND" H 8800 8430 30 0000 C CNN +F 2 "" H 8800 8500 70 0000 C CNN +F 3 "" H 8800 8500 70 0000 C CNN + 1 8800 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_73 +U 1 1 58023FDA +P 11700 8500 +F 0 "GND_73" H 11700 8500 20 0000 C CNN +F 1 "+GND" H 11700 8430 30 0000 C CNN +F 2 "" H 11700 8500 70 0000 C CNN +F 3 "" H 11700 8500 70 0000 C CNN + 1 11700 8500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 FT_MGMT_VCC3V3_2 +U 1 1 58023FD9 +P 11700 7400 +F 0 "FT_MGMT_VCC3V3_2" H 11700 7400 20 0000 C CNN +F 1 "+FT_MGMT_VCC3V3" H 11700 7330 30 0000 C CNN +F 2 "" H 11700 7400 70 0000 C CNN +F 3 "" H 11700 7400 70 0000 C CNN + 1 11700 7400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_74 +U 1 1 58023FD8 +P 2200 4000 +F 0 "GND_74" H 2200 4000 20 0000 C CNN +F 1 "+GND" H 2200 3930 30 0000 C CNN +F 2 "" H 2200 4000 70 0000 C CNN +F 3 "" H 2200 4000 70 0000 C CNN + 1 2200 4000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 FT_MGMT_VCC3V3_3 +U 1 1 58023FD7 +P 9900 7400 +F 0 "FT_MGMT_VCC3V3_3" H 9900 7400 20 0000 C CNN +F 1 "+FT_MGMT_VCC3V3" H 9900 7330 30 0000 C CNN +F 2 "" H 9900 7400 70 0000 C CNN +F 3 "" H 9900 7400 70 0000 C CNN + 1 9900 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VREGIN FT_MGMT_VREGIN +U 1 1 58023FD6 +P 4700 7400 +F 0 "FT_MGMT_VREGIN" H 4700 7400 20 0000 C CNN +F 1 "+FT_MGMT_VREGIN" H 4700 7330 30 0000 C CNN +F 2 "" H 4700 7400 70 0000 C CNN +F 3 "" H 4700 7400 70 0000 C CNN + 1 4700 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 FT_MGMT_VCC3V3_4 +U 1 1 58023FD5 +P 6000 7400 +F 0 "FT_MGMT_VCC3V3_4" H 6000 7400 20 0000 C CNN +F 1 "+FT_MGMT_VCC3V3" H 6000 7330 30 0000 C CNN +F 2 "" H 6000 7400 70 0000 C CNN +F 3 "" H 6000 7400 70 0000 C CNN + 1 6000 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VPHY FT_MGMT_VPHY +U 1 1 58023FD4 +P 7000 7400 +F 0 "FT_MGMT_VPHY" H 7000 7400 20 0000 C CNN +F 1 "+FT_MGMT_VPHY" H 7000 7330 30 0000 C CNN +F 2 "" H 7000 7400 70 0000 C CNN +F 3 "" H 7000 7400 70 0000 C CNN + 1 7000 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 FT_MGMT_VCC3V3_5 +U 1 1 58023FD3 +P 7800 7400 +F 0 "FT_MGMT_VCC3V3_5" H 7800 7400 20 0000 C CNN +F 1 "+FT_MGMT_VCC3V3" H 7800 7330 30 0000 C CNN +F 2 "" H 7800 7400 70 0000 C CNN +F 3 "" H 7800 7400 70 0000 C CNN + 1 7800 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VPLL FT_MGMT_VPLL +U 1 1 58023FD2 +P 8800 7400 +F 0 "FT_MGMT_VPLL" H 8800 7400 20 0000 C CNN +F 1 "+FT_MGMT_VPLL" H 8800 7330 30 0000 C CNN +F 2 "" H 8800 7400 70 0000 C CNN +F 3 "" H 8800 7400 70 0000 C CNN + 1 8800 7400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_75 +U 1 1 58023FD1 +P 4000 4000 +F 0 "GND_75" H 4000 4000 20 0000 C CNN +F 1 "+GND" H 4000 3930 30 0000 C CNN +F 2 "" H 4000 4000 70 0000 C CNN +F 3 "" H 4000 4000 70 0000 C CNN + 1 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VREGIN FT_MGMT_VREGIN_2 +U 1 1 58023FD0 +P 13400 5500 +F 0 "FT_MGMT_VREGIN_2" H 13400 5500 20 0000 C CNN +F 1 "+FT_MGMT_VREGIN" H 13400 5430 30 0000 C CNN +F 2 "" H 13400 5500 70 0000 C CNN +F 3 "" H 13400 5500 70 0000 C CNN + 1 13400 5500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_76 +U 1 1 58023FCF +P 12600 6500 +F 0 "GND_76" H 12600 6500 20 0000 C CNN +F 1 "+GND" H 12600 6430 30 0000 C CNN +F 2 "" H 12600 6500 70 0000 C CNN +F 3 "" H 12600 6500 70 0000 C CNN + 1 12600 6500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_18 +U 1 1 58023FCE +P 11100 2600 +F 0 "VCCO_3V3_18" H 11100 2600 20 0000 C CNN +F 1 "+VCCO_3V3" H 11100 2530 30 0000 C CNN +F 2 "" H 11100 2600 70 0000 C CNN +F 3 "" H 11100 2600 70 0000 C CNN + 1 11100 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 4400 6300 4600 +Wire Wire Line + 6300 4600 6300 4700 +Wire Wire Line + 6300 4700 6200 4700 +Wire Wire Line + 6200 4700 6100 4700 +Wire Wire Line + 6100 4400 6100 4700 +Wire Wire Line + 6500 4600 6300 4600 +Connection ~ 6200 4700 +Connection ~ 6300 4600 +Wire Wire Line + 9100 6200 9100 6300 +Wire Wire Line + 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6000 7400 6000 7800 +Wire Wire Line + 6100 7800 6000 7800 +Wire Wire Line + 7800 7400 7800 7800 +Wire Wire Line + 7900 7800 7800 7800 +Wire Wire Line + 9900 7800 9900 8000 +Wire Wire Line + 9900 7400 9900 7800 +Wire Wire Line + 10200 7800 10200 8000 +Wire Wire Line + 10200 7800 9900 7800 +Connection ~ 9900 7800 +Wire Wire Line + 6700 5700 6500 5700 +Wire Wire Line + 6700 5700 6700 5800 +Wire Wire Line + 7400 5700 6700 5700 +Connection ~ 6700 5700 +Wire Wire Line + 6300 5700 6100 5700 +Wire Wire Line + 6100 5700 6100 5800 +Wire Wire Line + 7400 5400 6100 5400 +Wire Wire Line + 6100 5400 6100 5700 +Connection ~ 6100 5700 +Wire Wire Line + 8400 2700 8400 3200 +Wire Wire Line + 8400 2700 7650 2700 +Text Label 7650 2700 0 48 ~ +FT_MGMT_VPLL +Wire Wire Line + 8800 7800 8300 7800 +Wire Wire Line + 8800 7800 8800 8000 +Wire Wire Line + 8300 7800 8300 8000 +Wire Wire Line + 8800 7400 8800 7800 +Wire Wire Line + 8300 7800 8100 7800 +Connection ~ 8300 7800 +Connection ~ 8800 7800 +Wire Wire Line + 7400 4200 6980 4200 +Wire Wire Line + 4150 3500 3700 3500 +Text Label 4150 3500 0 48 ~ +USB_MGMT_P +Wire Wire Line + 12700 6200 12050 6200 +Wire Wire Line + 8300 2900 8300 3200 +Wire Wire Line + 8300 2900 7650 2900 +Text Label 7650 2900 0 48 ~ +FT_MGMT_VPHY +Wire Wire Line + 7000 7800 6500 7800 +Wire Wire Line + 7000 7800 7000 8000 +Wire Wire Line + 6500 7800 6500 8000 +Wire Wire Line + 7000 7400 7000 7800 +Wire Wire Line + 6500 7800 6300 7800 +Connection ~ 6500 7800 +Connection ~ 7000 7800 +Wire Wire Line + 11100 3500 11000 3500 +Wire Wire Line + 11300 3500 11100 3500 +Wire Wire Line + 11100 3200 11100 3500 +Text GLabel 11300 3500 2 48 Output ~ 0 +FT_MGMT_TXD +Connection ~ 11100 3500 +Wire Wire Line + 11300 3600 11000 3600 +Text GLabel 11300 3600 2 48 Input ~ 0 +FT_MGMT_RXD +Wire Wire Line + 9800 3700 9600 3700 +Text GLabel 9800 3700 2 48 Output ~ 0 +FT_MGMT_RTS +Wire Wire Line + 9800 3800 9600 3800 +Text GLabel 9800 3800 2 48 Input ~ 0 +FT_MGMT_CTS +Wire Wire Line + 9800 3900 9600 3900 +Text GLabel 9800 3900 2 48 UnSpc ~ 0 +FT_MGMT_DTR +Wire Wire Line + 2700 3500 2100 3500 +Wire Wire Line + 2400 3600 2100 3600 +Wire Wire Line + 2400 3600 2400 3700 +Wire Wire Line + 2700 3700 2400 3700 +Wire Wire Line + 13400 5700 13400 6100 +Wire Wire Line + 13400 5500 13400 5700 +Wire Wire Line + 13400 5700 12600 5700 +Wire Wire Line + 13400 6100 13300 6100 +Connection ~ 13400 5700 +Wire Wire Line + 11100 2600 11100 2800 +Wire Wire Line + 10600 3500 9600 3500 +Text Label 9900 3500 0 48 ~ +FT_MGMT_TXD1 +Wire Wire Line + 13500 6300 13300 6300 +Text Label 13500 6300 0 48 ~ 0 +FT_MGMT_TXD1 +Wire Wire Line + 10600 3600 9600 3600 +Text Label 9900 3600 0 48 ~ +FT_MGMT_RXD1 +Wire Wire Line + 12700 6300 12050 6300 +Text Label 12050 6300 0 48 ~ +FT_MGMT_RXD1 +Text Label 6980 4100 0 48 ~ +USB_MGMT_N +Text Label 6980 4200 0 48 ~ +USB_MGMT_P +Text Label 13500 6200 0 48 ~ 0 +USB_MGMT_N +Text Label 12050 6200 0 48 ~ +USB_MGMT_P +Text Label 2100 3600 0 60 ~ +DM_N +Text Label 2100 3500 0 60 ~ +DM_P +$Comp +L Cryptech_Alpha:FT_MGMT_VREGIN FT_MGMT_VREGIN_3 +U 1 1 58023FCD +P 2600 3400 +F 0 "FT_MGMT_VREGIN_3" H 2600 3400 20 0000 C CNN +F 1 "+FT_MGMT_VREGIN" H 2600 3330 30 0000 C CNN +F 2 "" H 2600 3400 70 0000 C CNN +F 3 "" H 2600 3400 70 0000 C CNN + 1 2600 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_77 +U 1 1 58023FCC +P 6300 5800 +F 0 "GND_77" H 6300 5800 20 0000 C CNN +F 1 "+GND" H 6300 5730 30 0000 C CNN +F 2 "" H 6300 5800 70 0000 C CNN +F 3 "" H 6300 5800 70 0000 C CNN + 1 6300 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_78 +U 1 1 58023FCB +P 6500 5800 +F 0 "GND_78" H 6500 5800 20 0000 C CNN +F 1 "+GND" H 6500 5730 30 0000 C CNN +F 2 "" H 6500 5800 70 0000 C CNN +F 3 "" H 6500 5800 70 0000 C CNN + 1 6500 5800 + 1 0 0 -1 +$EndComp +Connection ~ 2600 3400 +Connection ~ 6620 3700 +$Comp +L Cryptech_Alpha:FT232H_SERIAL U9 +U 1 1 58023FCA +P 8500 4700 +F 0 "U9" H 9620 5910 60 0000 L BNN +F 1 "FT232HL-REEL" H 7380 6220 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:LQFP-48" H 7380 6220 60 0001 C CNN +F 3 "" H 7380 6220 60 0000 C CNN + 1 8500 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C97 +U 1 1 58023FC9 +P 9900 8100 +F 0 "C97" H 9590 8180 60 0000 L BNN +F 1 "4.7uF" H 9590 8080 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 9590 8080 60 0001 C CNN +F 3 "" H 9590 8080 60 0000 C CNN + 1 9900 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C98 +U 1 1 58023FC8 +P 10200 8100 +F 0 "C98" H 10300 8200 60 0000 L BNN +F 1 "0.1uF" H 10300 8110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10300 8110 60 0001 C CNN +F 3 "" H 10300 8110 60 0000 C CNN + 1 10200 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C94 +U 1 1 58023FC7 +P 7000 8100 +F 0 "C94" H 7100 8000 60 0000 L BNN +F 1 "0.1uF" H 7100 7900 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7100 7900 60 0001 C CNN +F 3 "" H 7100 7900 60 0000 C CNN + 1 7000 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C92 +U 1 1 58023FC6 +P 6500 8100 +F 0 "C92" H 6213 7984 60 0000 L BNN +F 1 "10uF" H 6190 7910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 6190 7910 60 0001 C CNN +F 3 "" H 6190 7910 60 0000 C CNN + 1 6500 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C96 +U 1 1 58023FC5 +P 8800 8100 +F 0 "C96" H 8900 8000 60 0000 L BNN +F 1 "0.1uF" H 8900 7910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 8900 7910 60 0001 C CNN +F 3 "" H 8900 7910 60 0000 C CNN + 1 8800 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C95 +U 1 1 58023FC4 +P 8300 8100 +F 0 "C95" H 8013 8034 60 0000 L BNN +F 1 "10uF" H 7979 7930 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 7979 7930 60 0001 C CNN +F 3 "" H 7979 7930 60 0000 C CNN + 1 8300 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C99 +U 1 1 58023FC3 +P 11300 8100 +F 0 "C99" H 11000 8000 60 0000 L BNN +F 1 "0.1uF" H 10950 7910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 10950 7910 60 0001 C CNN +F 3 "" H 10950 7910 60 0000 C CNN + 1 11300 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C100 +U 1 1 58023FC2 +P 11700 8100 +F 0 "C100" H 11400 8230 60 0000 L BNN +F 1 "0.1uF" H 11400 8130 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11400 8130 60 0001 C CNN +F 3 "" H 11400 8130 60 0000 C CNN + 1 11700 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C101 +U 1 1 58023FC1 +P 12100 8100 +F 0 "C101" H 12200 8000 60 0000 L BNN +F 1 "0.1uF" H 12210 7910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12210 7910 60 0001 C CNN +F 3 "" H 12210 7910 60 0000 C CNN + 1 12100 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FERRITE_0603MP FB4 +U 1 1 58023FC0 +P 8000 7800 +F 0 "FB4" H 7920 7632 60 0000 L BNN + 1 8000 7800 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:L_0603" H 7920 7632 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R27 +U 1 1 58023FBF +P 6820 4400 +F 0 "R27" H 6930 4545 60 0000 R TNN +F 1 "10k" H 6930 4360 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6930 4360 60 0001 C CNN +F 3 "" H 6930 4360 60 0000 C CNN + 1 6820 4400 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:FERRITE_0603MP FB3 +U 1 1 58023FBE +P 6200 7800 +F 0 "FB3" H 6120 7632 60 0000 L BNN + 1 6200 7800 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:L_0603" H 6120 7632 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:USBMINIB CN2 +U 1 1 58023FBD +P 1700 3600 +F 0 "CN2" H 1288 3190 60 0000 L BNN +F 1 "690-005-299-043" H 1288 3910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:USB-MINIB" H 1288 3910 60 0001 C CNN +F 3 "" H 1288 3910 60 0000 C CNN + 1 1700 3600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:RCLAMP0502ASC-89 IC6 +U 1 1 58023FBC +P 3200 3600 +F 0 "IC6" H 2790 3290 60 0000 L BNN +F 1 "RCLAMP0502A.TCT" H 2790 3280 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:RCLAMP0502A" H 2790 3280 60 0001 C CNN +F 3 "" H 2790 3280 60 0000 C CNN + 1 3200 3600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R88 +U 1 1 58023FBB +P 10800 3500 +F 0 "R88" H 10897 3270 60 0000 R TNN +F 1 "100" H 10890 3360 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10890 3360 60 0001 C CNN +F 3 "" H 10890 3360 60 0000 C CNN + 1 10800 3500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R89 +U 1 1 58023FBA +P 10800 3600 +F 0 "R89" H 11140 3730 60 0000 R TNN +F 1 "100" H 11150 3820 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 11150 3820 60 0001 C CNN +F 3 "" H 11150 3820 60 0000 C CNN + 1 10800 3600 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:M03X2NO_SILK J3 +U 1 1 58023FB9 +P 13000 6200 +F 0 "J3" H 12790 5890 60 0000 L BNN + 1 13000 6200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 12790 5890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C215 +U 1 1 58023FB8 +P 12600 5800 +F 0 "C215" H 12200 5700 60 0000 L BNN +F 1 "0.1uF" H 12200 5600 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12200 5600 60 0001 C CNN +F 3 "" H 12200 5600 60 0000 C CNN + 1 12600 5800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R90 +U 1 1 58023FB7 +P 11100 3000 +F 0 "R90" V 11000 3100 60 0000 L BNN +F 1 "10k" V 11100 3090 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 11100 3090 60 0001 C CNN +F 3 "" H 11100 3090 60 0000 C CNN + 1 11100 3000 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:CRYSTALTHIN Y2 +U 1 1 58023FB6 +P 6400 5700 +F 0 "Y2" H 6470 5800 60 0000 R BNN +F 1 "ABM8G-12.000MHZ-4Y-T3" H 5610 5820 60 0000 R BNN +F 2 "Cryptech_Alpha_Footprints:CRYSTAL_3.2X2.5" H 5610 5820 60 0001 C CNN +F 3 "" H 5610 5820 60 0000 C CNN + 1 6400 5700 + -1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C91 +U 1 1 58023FB5 +P 6300 4200 +F 0 "C91" H 6380 4010 60 0000 L BNN +F 1 "0.1uF" H 6350 3990 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6350 3990 60 0001 C CNN +F 3 "" H 6350 3990 60 0000 C CNN + 1 6300 4200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C89 +U 1 1 58023FB4 +P 6100 4200 +F 0 "C89" H 5660 4215 60 0000 L BNN +F 1 "0.1uF" H 5660 4100 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5660 4100 60 0001 C CNN +F 3 "" H 5660 4100 60 0000 C CNN + 1 6100 4200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R26 +U 1 1 58023FB3 +P 6700 4600 +F 0 "R26" H 6850 4791 60 0000 R TNN +F 1 "12k" H 6850 4870 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6850 4870 60 0001 C CNN +F 3 "" H 6850 4870 60 0000 C CNN + 1 6700 4600 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C93 +U 1 1 58023FB2 +P 6700 6000 +F 0 "C93" H 6600 6000 60 0000 R TNN +F 1 "5pF" H 6580 6090 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6580 6090 60 0001 C CNN +F 3 "" H 6580 6090 60 0000 C CNN + 1 6700 6000 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C90 +U 1 1 58023FB1 +P 6100 6000 +F 0 "C90" H 6400 6000 60 0000 R TNN +F 1 "5pF" H 6400 6100 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6400 6100 60 0001 C CNN +F 3 "" H 6400 6100 60 0000 C CNN + 1 6100 6000 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C87 +U 1 1 58023FB0 +P 4700 8100 +F 0 "C87" H 4413 8184 60 0000 L BNN +F 1 "4.7uF" H 4400 8080 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4400 8080 60 0001 C CNN +F 3 "" H 4400 8080 60 0000 C CNN + 1 4700 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C88 +U 1 1 58023FAF +P 5000 8100 +F 0 "C88" H 5100 8200 60 0000 L BNN +F 1 "0.1uF" H 5100 8110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5100 8110 60 0001 C CNN +F 3 "" H 5100 8110 60 0000 C CNN + 1 5000 8100 + 1 0 0 -1 +$EndComp +NoConn ~ 9600 4000 +NoConn ~ 9600 4100 +NoConn ~ 9600 4200 +NoConn ~ 9600 4400 +NoConn ~ 9600 4500 +NoConn ~ 9600 4600 +NoConn ~ 9600 4700 +NoConn ~ 9600 4800 +NoConn ~ 9600 4900 +NoConn ~ 9600 5000 +NoConn ~ 9600 5100 +NoConn ~ 9600 5200 +NoConn ~ 9600 5300 +NoConn ~ 2100 3700 +NoConn ~ 7400 5000 +NoConn ~ 7400 5100 +NoConn ~ 7400 5200 +$Comp +L Cryptech_Alpha:FT_MGMT_VPLL #PWR? +U 1 1 5AF74540 +P 7650 2700 +F 0 "#PWR?" H 7650 2550 50 0001 C CNN +F 1 "FT_MGMT_VPLL" V 7665 2827 50 0000 L CNN +F 2 "" H 7650 2700 60 0000 C CNN +F 3 "" H 7650 2700 60 0000 C CNN + 1 7650 2700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VPHY #PWR? +U 1 1 5AF74918 +P 7650 2900 +F 0 "#PWR?" H 7650 2750 50 0001 C CNN +F 1 "FT_MGMT_VPHY" V 7665 3028 50 0000 L CNN +F 2 "" H 7650 2900 60 0000 C CNN +F 3 "" H 7650 2900 60 0000 C CNN + 1 7650 2900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VREGIN #PWR? +U 1 1 5AF74D26 +P 6100 3500 +F 0 "#PWR?" H 6100 3350 50 0001 C CNN +F 1 "FT_MGMT_VREGIN" V 6115 3628 50 0000 L CNN +F 2 "" H 6100 3500 60 0000 C CNN +F 3 "" H 6100 3500 60 0000 C CNN + 1 6100 3500 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 #PWR? +U 1 1 5AF74F88 +P 6100 3700 +F 0 "#PWR?" H 6100 3550 50 0001 C CNN +F 1 "FT_MGMT_VCC3V3" V 6115 3828 50 0000 L CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6100 3700 + 0 -1 -1 0 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA8493 +P 8300 7800 +F 0 "#FLG?" H 8300 7875 50 0001 C CNN +F 1 "PWR_FLAG" H 8300 7974 50 0000 C CNN +F 2 "" H 8300 7800 50 0001 C CNN +F 3 "~" H 8300 7800 50 0001 C CNN + 1 8300 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA857D +P 6500 7800 +F 0 "#FLG?" H 6500 7875 50 0001 C CNN +F 1 "PWR_FLAG" H 6500 7974 50 0000 C CNN +F 2 "" H 6500 7800 50 0001 C CNN +F 3 "~" H 6500 7800 50 0001 C CNN + 1 6500 7800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_11.sch b/KiCAD/rev02_11.sch new file mode 100644 index 0000000..6ddc1e3 --- /dev/null +++ b/KiCAD/rev02_11.sch @@ -0,0 +1,747 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 13 27 +Title "rev02_11" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 4600 3100 0 126 ~ 12 +AVR Tiny Tamper Detect MCU +Text Notes 13000 3930 0 84 ~ 12 +Panic button +Text Notes 13200 6100 0 84 ~ 12 +Expansion GPIO +Text Notes 12680 1730 0 60 ~ 12 +Connector for external 3V3 battery.\nPlace a jumper between pins 1-2\nto "emulate" having a battery present. +Text Notes 4100 7000 0 60 ~ 12 +AVR_GPIO* AVR_LED* and AVR_PANIC can be swapped. +Text Notes 13650 10210 0 84 ~ 12 +AVR Tamper circuit +Text Notes 5900 3780 0 60 ~ 12 +U10 +Text Notes 5880 6680 0 60 ~ 12 +ATTINY828R-AU +Text Notes 9700 4570 0 60 ~ 12 +R30 +Text Notes 14300 6300 2 60 ~ 12 +M10LOCK +Text Notes 14300 7550 2 60 ~ 12 +JP5 +Text Notes 13200 4100 0 60 ~ 12 +S2 +Text Notes 14300 2200 2 60 ~ 12 +M03LOCK +Text Notes 14300 2730 2 60 ~ 12 +JP4 +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_3 +U 1 1 58023FAE +P 3500 3600 +F 0 "3V3_BATT_3" H 3500 3600 20 0000 C CNN +F 1 "+3V3_BATT" H 3500 3530 30 0000 C CNN +F 2 "" H 3500 3600 70 0000 C CNN +F 3 "" H 3500 3600 70 0000 C CNN + 1 3500 3600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_79 +U 1 1 58023FAD +P 3500 6700 +F 0 "GND_79" H 3500 6700 20 0000 C CNN +F 1 "+GND" H 3500 6630 30 0000 C CNN +F 2 "" H 3500 6700 70 0000 C CNN +F 3 "" H 3500 6700 70 0000 C CNN + 1 3500 6700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_4 +U 1 1 58023FAC +P 10900 5700 +F 0 "3V3_BATT_4" H 10900 5700 20 0000 C CNN +F 1 "+3V3_BATT" H 10900 5630 30 0000 C CNN +F 2 "" H 10900 5700 70 0000 C CNN +F 3 "" H 10900 5700 70 0000 C CNN + 1 10900 5700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_5 +U 1 1 58023FAB +P 9600 4100 +F 0 "3V3_BATT_5" H 9600 4100 20 0000 C CNN +F 1 "+3V3_BATT" H 9600 4030 30 0000 C CNN +F 2 "" H 9600 4100 70 0000 C CNN +F 3 "" H 9600 4100 70 0000 C CNN + 1 9600 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_80 +U 1 1 58023FAA +P 10900 6700 +F 0 "GND_80" H 10900 6700 20 0000 C CNN +F 1 "+GND" H 10900 6630 30 0000 C CNN +F 2 "" H 10900 6700 70 0000 C CNN +F 3 "" H 10900 6700 70 0000 C CNN + 1 10900 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_81 +U 1 1 58023FA9 +P 2200 4800 +F 0 "GND_81" H 2200 4800 20 0000 C CNN +F 1 "+GND" H 2200 4730 30 0000 C CNN +F 2 "" H 2200 4800 70 0000 C CNN +F 3 "" H 2200 4800 70 0000 C CNN + 1 2200 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_82 +U 1 1 58023FA8 +P 14300 9200 +F 0 "GND_82" H 14300 9200 20 0000 C CNN +F 1 "+GND" H 14300 9130 30 0000 C CNN +F 2 "" H 14300 9200 70 0000 C CNN +F 3 "" H 14300 9200 70 0000 C CNN + 1 14300 9200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_83 +U 1 1 58023FA7 +P 13700 7500 +F 0 "GND_83" H 13700 7500 20 0000 C CNN +F 1 "+GND" H 13700 7430 30 0000 C CNN +F 2 "" H 13700 7500 70 0000 C CNN +F 3 "" H 13700 7500 70 0000 C CNN + 1 13700 7500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_84 +U 1 1 58023FA6 +P 14200 5300 +F 0 "GND_84" H 14200 5300 20 0000 C CNN +F 1 "+GND" H 14200 5230 30 0000 C CNN +F 2 "" H 14200 5300 70 0000 C CNN +F 3 "" H 14200 5300 70 0000 C CNN + 1 14200 5300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_85 +U 1 1 58023FA5 +P 13700 2800 +F 0 "GND_85" H 13700 2800 20 0000 C CNN +F 1 "+GND" H 13700 2730 30 0000 C CNN +F 2 "" H 13700 2800 70 0000 C CNN +F 3 "" H 13700 2800 70 0000 C CNN + 1 13700 2800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_6 +U 1 1 58023FA4 +P 13200 2200 +F 0 "3V3_BATT_6" H 13200 2200 20 0000 C CNN +F 1 "+3V3_BATT" H 13200 2130 30 0000 C CNN +F 2 "" H 13200 2200 70 0000 C CNN +F 3 "" H 13200 2200 70 0000 C CNN + 1 13200 2200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_19 +U 1 1 58023FA3 +P 13700 2200 +F 0 "VCCO_3V3_19" H 13700 2200 20 0000 C CNN +F 1 "+VCCO_3V3" H 13700 2130 30 0000 C CNN +F 2 "" H 13700 2200 70 0000 C CNN +F 3 "" H 13700 2200 70 0000 C CNN + 1 13700 2200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_86 +U 1 1 58023FA2 +P 12800 7500 +F 0 "GND_86" H 12800 7500 20 0000 C CNN +F 1 "+GND" H 12800 7430 30 0000 C CNN +F 2 "" H 12800 7500 70 0000 C CNN +F 3 "" H 12800 7500 70 0000 C CNN + 1 12800 7500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_7 +U 1 1 58023FA1 +P 12800 4400 +F 0 "3V3_BATT_7" H 12800 4400 20 0000 C CNN +F 1 "+3V3_BATT" H 12800 4330 30 0000 C CNN +F 2 "" H 12800 4400 70 0000 C CNN +F 3 "" H 12800 4400 70 0000 C CNN + 1 12800 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 6200 3500 6200 +Wire Wire Line + 3500 6200 3500 6300 +Wire Wire Line + 3500 6300 3500 6700 +Wire Wire Line + 3900 6300 3500 6300 +Connection ~ 3500 6300 +Wire Wire Line + 10900 6200 10800 6200 +Wire Wire Line + 10900 6200 10900 6700 +Wire Wire Line + 1900 4600 1900 4700 +Wire Wire Line + 2200 4700 1900 4700 +Wire Wire Line + 2200 4700 2200 4800 +Wire Wire Line + 2500 4600 2500 4700 +Wire Wire Line + 2500 4700 2200 4700 +Wire Wire Line + 2200 4600 2200 4700 +Connection ~ 2200 4700 +Wire Wire Line + 14300 8700 14200 8700 +Wire Wire Line + 14300 8900 14300 9000 +Wire Wire Line + 14300 8800 14300 8900 +Wire Wire Line + 14300 8700 14300 8800 +Wire Wire Line + 14300 8800 14000 8800 +Wire Wire Line + 14300 9000 14000 9000 +Wire Wire Line + 14300 8900 14200 8900 +Wire Wire Line + 14300 9000 14300 9200 +Connection ~ 14300 8900 +Connection ~ 14300 8800 +Connection ~ 14300 9000 +Wire Wire Line + 13900 7400 13700 7400 +Wire Wire Line + 13700 7400 13700 7500 +Wire Wire Line + 14200 4600 14100 4600 +Wire Wire Line + 14200 4600 14200 4800 +Wire Wire Line + 14200 4800 14200 5100 +Wire Wire Line + 14200 5100 14200 5300 +Wire Wire Line + 14200 4800 14100 4800 +Wire Wire Line + 14200 5100 13800 5100 +Wire Wire Line + 14200 4300 13800 4300 +Wire Wire Line + 14200 4300 14200 4600 +Connection ~ 14200 4800 +Connection ~ 14200 5100 +Connection ~ 14200 4600 +Wire Wire Line + 13900 2600 13700 2600 +Wire Wire Line + 13700 2600 13700 2800 +Wire Wire Line + 12800 7100 12800 7500 +Wire Wire Line + 10100 6200 9600 6200 +Wire Wire Line + 9600 5200 9600 6200 +Wire Wire Line + 9600 5200 8300 5200 +Wire Wire Line + 9600 4800 9600 5200 +Connection ~ 9600 5200 +Text Label 9600 5700 0 48 ~ +AVR_RESET +Wire Wire Line + 10900 6000 10800 6000 +Wire Wire Line + 10900 5700 10900 6000 +Wire Wire Line + 9600 4100 9600 4400 +Wire Wire Line + 3900 4200 3500 4200 +Wire Wire Line + 3500 4100 3500 4200 +Wire Wire Line + 3500 3600 3500 4100 +Wire Wire Line + 3900 4100 3500 4100 +Wire Wire Line + 3500 4100 2500 4100 +Wire Wire Line + 2500 4100 2200 4100 +Wire Wire Line + 2200 4100 1900 4100 +Wire Wire Line + 1900 4100 1900 4300 +Wire Wire Line + 2200 4100 2200 4300 +Wire Wire Line + 2500 4100 2500 4300 +Connection ~ 3500 4100 +Connection ~ 2200 4100 +Connection ~ 2500 4100 +Wire Wire Line + 13900 2500 13200 2500 +Wire Wire Line + 13200 2200 13200 2500 +Wire Wire Line + 12800 4400 12800 4500 +Wire Wire Line + 3900 5000 3070 5000 +Text GLabel 3070 5000 0 48 Output ~ 0 +MKM_CONTROL_AVR_ENA +Wire Wire Line + 9700 5300 8500 5300 +Wire Wire Line + 9700 5300 9700 6100 +Wire Wire Line + 10100 6100 9700 6100 +Wire Wire Line + 8500 5300 8300 5300 +Text GLabel 8440 5300 2 48 Output ~ 0 +MKM_AVR_SCK +Wire Wire Line + 3900 4900 3070 4900 +Text GLabel 3070 4900 0 48 Output ~ 0 +MKM_AVR_CS_N +Wire Wire Line + 8700 5000 8300 5000 +Wire Wire Line + 11100 5000 8700 5000 +Wire Wire Line + 11100 5000 11100 6100 +Wire Wire Line + 11100 6100 10800 6100 +Text GLabel 8440 5000 2 48 Output ~ 0 +MKM_AVR_MOSI +Wire Wire Line + 10100 6000 9800 6000 +Wire Wire Line + 9800 5100 9800 6000 +Wire Wire Line + 9800 5100 8600 5100 +Wire Wire Line + 8600 5100 8300 5100 +Text GLabel 8440 5100 2 48 Input ~ 0 +MKM_AVR_MISO +Wire Wire Line + 13900 8700 13600 8700 +Wire Wire Line + 13200 8700 12610 8700 +Text Label 12610 8700 0 48 ~ +AVR_LED1 +Wire Wire Line + 3900 4400 3170 4400 +Text Label 3170 4400 0 48 ~ +AVR_LED1 +Wire Wire Line + 13700 8800 13290 8800 +Wire Wire Line + 12890 8800 12610 8800 +Text Label 12610 8800 0 48 ~ +AVR_LED2 +Wire Wire Line + 3900 4500 3170 4500 +Text Label 3170 4500 0 48 ~ +AVR_LED2 +Wire Wire Line + 13900 8900 13600 8900 +Wire Wire Line + 13200 8900 12610 8900 +Text Label 12610 8900 0 48 ~ +AVR_LED3 +Wire Wire Line + 3900 4600 3180 4600 +Text Label 3180 4600 0 48 ~ +AVR_LED3 +Wire Wire Line + 13700 9000 13290 9000 +Wire Wire Line + 12890 9000 12610 9000 +Text Label 12610 9000 0 48 ~ +AVR_LED4 +Wire Wire Line + 3900 4700 3170 4700 +Text Label 3170 4700 0 48 ~ +AVR_LED4 +Wire Wire Line + 13900 6600 13500 6600 +Text Label 13500 6600 2 48 ~ 0 +AVR_GPIO_0 +Wire Wire Line + 8500 4100 8300 4100 +Text Label 8500 4100 0 48 ~ +AVR_GPIO_0 +Wire Wire Line + 13900 6700 13500 6700 +Text Label 13500 6700 2 48 ~ 0 +AVR_GPIO_1 +Wire Wire Line + 8500 4200 8300 4200 +Text Label 8500 4200 0 48 ~ +AVR_GPIO_1 +Wire Wire Line + 13900 6800 13500 6800 +Text Label 13500 6800 2 48 ~ 0 +AVR_GPIO_2 +Wire Wire Line + 8500 4300 8300 4300 +Text Label 8500 4300 0 48 ~ +AVR_GPIO_2 +Wire Wire Line + 13900 6900 13500 6900 +Text Label 13500 6900 2 48 ~ 0 +AVR_GPIO_3 +Wire Wire Line + 8500 4400 8300 4400 +Text Label 8500 4400 0 48 ~ +AVR_GPIO_3 +Wire Wire Line + 13900 7000 13500 7000 +Text Label 13500 7000 2 48 ~ 0 +AVR_GPIO_4 +Wire Wire Line + 8500 4500 8300 4500 +Text Label 8500 4500 0 48 ~ +AVR_GPIO_4 +Wire Wire Line + 13900 7100 13500 7100 +Text Label 13500 7100 2 48 ~ 0 +AVR_GPIO_5 +Wire Wire Line + 8500 4600 8300 4600 +Text Label 8500 4600 0 48 ~ +AVR_GPIO_5 +Wire Wire Line + 13900 7200 13500 7200 +Text Label 13500 7200 2 48 ~ 0 +AVR_GPIO_6 +Wire Wire Line + 8500 4700 8300 4700 +Text Label 8500 4700 0 48 ~ +AVR_GPIO_6 +Wire Wire Line + 13900 7300 13500 7300 +Text Label 13500 7300 2 48 ~ 0 +AVR_GPIO_7 +Wire Wire Line + 8500 4800 8300 4800 +Text Label 8500 4800 0 48 ~ +AVR_GPIO_7 +Wire Wire Line + 13200 5100 12800 5100 +Wire Wire Line + 12800 5100 12500 5100 +Wire Wire Line + 12800 4900 12800 5100 +Text Label 12500 5100 0 48 ~ +AVR_PANIC +Connection ~ 12800 5100 +Wire Wire Line + 3900 4800 3170 4800 +Text Label 3170 4800 0 48 ~ +AVR_PANIC +Wire Wire Line + 13900 2400 13700 2400 +Wire Wire Line + 13700 2200 13700 2400 +Wire Wire Line + 3900 5300 3170 5300 +Text GLabel 3170 5300 0 48 BiDi ~ 0 +AVR_GPIO_ARM_0 +Wire Wire Line + 3900 5400 3170 5400 +Text GLabel 3170 5400 0 48 BiDi ~ 0 +AVR_GPIO_ARM_1 +Wire Wire Line + 3900 5700 3170 5700 +Text GLabel 3170 5700 0 48 BiDi ~ 0 +AVR_GPIO_FPGA_0 +Wire Wire Line + 3900 5800 3170 5800 +Text GLabel 3170 5800 0 48 BiDi ~ 0 +AVR_GPIO_FPGA_1 +Wire Wire Line + 12800 6400 12800 6500 +Wire Wire Line + 13900 6500 12800 6500 +Wire Wire Line + 12800 6500 12800 6800 +Connection ~ 12800 6500 +Wire Wire Line + 3900 5100 3070 5100 +Text GLabel 3070 5100 0 48 Output ~ 0 +MKM_CONTROL_FPGA_DIS +Wire Wire Line + 3900 5500 3170 5500 +Text GLabel 3170 5500 0 48 BiDi ~ 0 +AVR_GPIO_ARM_2 +Wire Wire Line + 3900 5600 3170 5600 +Text GLabel 3170 5600 0 48 BiDi ~ 0 +AVR_GPIO_ARM_3 +Wire Wire Line + 3900 5900 3170 5900 +Text GLabel 3170 5900 0 48 BiDi ~ 0 +AVR_GPIO_FPGA_2 +Wire Wire Line + 3900 6000 3170 6000 +Text GLabel 3170 6000 0 48 BiDi ~ 0 +AVR_GPIO_FPGA_3 +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_20 +U 1 1 58023FA0 +P 12800 6400 +F 0 "VCCO_3V3_20" H 12800 6400 20 0000 C CNN +F 1 "+VCCO_3V3" H 12800 6330 30 0000 C CNN +F 2 "" H 12800 6400 70 0000 C CNN +F 3 "" H 12800 6400 70 0000 C CNN + 1 12800 6400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:ATTINY828R-AU U10 +U 1 1 58023F9F +P 6100 5100 +F 0 "U10" H 4070 3570 60 0000 L BNN + 1 6100 5100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:LQFP-32" H 4070 3570 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED10 +U 1 1 58023F9E +P 13800 9000 +F 0 "LED10" V 13770 8316 60 0000 R TNN +F 1 "LTST-C191KRKT" V 13760 7810 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13760 7810 60 0001 C CNN +F 3 "" H 13760 7810 60 0000 C CNN + 1 13800 9000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:M10LOCK JP5 +U 1 1 58023F9D +P 14300 7200 +F 0 "JP5" H 14580 7630 60 0000 R TNN + 1 14300 7200 + -1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:HDR1X10" H 14580 7630 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:TACTILE_SWITCH S2 +U 1 1 58023F9C +P 13500 4700 +F 0 "S2" H 14120 4810 60 0000 L BNN +F 1 "EVQPT9A15" H 13200 5170 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:TACTILE_SWITCH" H 13200 5170 60 0001 C CNN +F 3 "" H 13200 5170 60 0000 C CNN + 1 13500 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:M03LOCK JP4 +U 1 1 58023F9B +P 14200 2500 +F 0 "JP4" H 14380 2830 60 0000 R TNN + 1 14200 2500 + -1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:PLS-3" H 14380 2830 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C105 +U 1 1 58023F9A +P 12800 6900 +F 0 "C105" H 12390 6850 60 0000 L BNN +F 1 "0.1uF" H 12380 6740 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 12380 6740 60 0001 C CNN +F 3 "" H 12380 6740 60 0000 C CNN + 1 12800 6900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R82 +U 1 1 58023F99 +P 12800 4700 +F 0 "R82" V 12771 5047 60 0000 R TNN +F 1 "15k" V 12660 5050 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 12660 5050 60 0001 C CNN +F 3 "" H 12660 5050 60 0000 C CNN + 1 12800 4700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R96 +U 1 1 58023F98 +P 13400 8700 +F 0 "R96" H 13490 8520 60 0000 R TNN +F 1 "330" H 13500 8610 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 13500 8610 60 0001 C CNN +F 3 "" H 13500 8610 60 0000 C CNN + 1 13400 8700 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R95 +U 1 1 58023F97 +P 13090 8800 +F 0 "R95" H 13220 8520 60 0000 R TNN +F 1 "330" H 13230 8610 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 13230 8610 60 0001 C CNN +F 3 "" H 13230 8610 60 0000 C CNN + 1 13090 8800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R31 +U 1 1 58023F96 +P 13400 8900 +F 0 "R31" H 13080 8510 60 0000 R TNN +F 1 "330" H 13090 8600 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 13090 8600 60 0001 C CNN +F 3 "" H 13090 8600 60 0000 C CNN + 1 13400 8900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R97 +U 1 1 58023F95 +P 13090 9000 +F 0 "R97" H 13180 9170 60 0000 R TNN +F 1 "330" H 13190 9260 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 13190 9260 60 0001 C CNN +F 3 "" H 13190 9260 60 0000 C CNN + 1 13090 9000 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:AVR_SPI_PRG_62X3_LOCK JP3 +U 1 1 58023F94 +P 10400 6100 +F 0 "JP3" H 10230 6330 60 0000 L BNN +F 1 "AVR_SPI_PRG_62X3_LOCK" H 9440 5700 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 9440 5700 60 0001 C CNN +F 3 "" H 9440 5700 60 0000 C CNN + 1 10400 6100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R30 +U 1 1 58023F93 +P 9600 4600 +F 0 "R30" V 9510 4555 60 0000 R TNN +F 1 "15k" V 9540 4510 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9540 4510 60 0001 C CNN +F 3 "" H 9540 4510 60 0000 C CNN + 1 9600 4600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0805 C102 +U 1 1 58023F92 +P 1900 4400 +F 0 "C102" H 1580 4400 60 0000 L BNN +F 1 "10uF" H 1570 4290 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0805" H 1570 4290 60 0001 C CNN +F 3 "" H 1570 4290 60 0000 C CNN + 1 1900 4400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C104 +U 1 1 58023F91 +P 2500 4400 +F 0 "C104" H 2630 4400 60 0000 L BNN +F 1 "0.1uF" H 2620 4300 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2620 4300 60 0001 C CNN +F 3 "" H 2620 4300 60 0000 C CNN + 1 2500 4400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C103 +U 1 1 58023F90 +P 2200 4400 +F 0 "C103" H 2230 4490 60 0000 L BNN +F 1 "0.1uF" H 2220 4400 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2220 4400 60 0001 C CNN +F 3 "" H 2220 4400 60 0000 C CNN + 1 2200 4400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED11 +U 1 1 58023F8F +P 14000 8700 +F 0 "LED11" V 13970 8216 60 0000 R TNN +F 1 "LTST-C193TBKT-5A" V 13960 7710 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13960 7710 60 0001 C CNN +F 3 "" H 13960 7710 60 0000 C CNN + 1 14000 8700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED9 +U 1 1 58023F8E +P 13800 8800 +F 0 "LED9" V 13770 8110 60 0000 R TNN +F 1 "LTST-C191KGKT" V 13755 7616 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13755 7616 60 0001 C CNN +F 3 "" H 13755 7616 60 0000 C CNN + 1 13800 8800 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED12 +U 1 1 58023F8D +P 14000 8900 +F 0 "LED12" V 13970 8416 60 0000 R TNN +F 1 "LTST-C191KSKT" V 13960 7920 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 13960 7920 60 0001 C CNN +F 3 "" H 13960 7920 60 0000 C CNN + 1 14000 8900 + 0 -1 -1 0 +$EndComp +NoConn ~ 13200 4300 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AF61081 +P 13200 2500 +F 0 "#FLG?" H 13200 2575 50 0001 C CNN +F 1 "PWR_FLAG" V 13200 2628 50 0000 L CNN +F 2 "" H 13200 2500 50 0001 C CNN +F 3 "~" H 13200 2500 50 0001 C CNN + 1 13200 2500 + 0 -1 -1 0 +$EndComp +Connection ~ 13200 2500 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_12.sch b/KiCAD/rev02_12.sch new file mode 100644 index 0000000..12d1bec --- /dev/null +++ b/KiCAD/rev02_12.sch @@ -0,0 +1,430 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 14 27 +Title "rev02_12" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 12700 5600 0 42 ~ 12 +CS pull-up to disable MKM by\ndefault (allows programming\nof AVR) +Text Notes 11400 3800 0 84 ~ 12 +Master Key Memory +Text Notes 3400 2700 0 84 ~ 12 +SPI mux controlling access to the MKM.\nNormally, the FPGA has R/W access to the MKM but on a\ntamper event the tamper detect MCU (AVR) will grab access\nto the MKM and erase the contents. +Text Notes 7800 6100 0 42 ~ 12 +Make AVR unable to read the\nMKM by installing this jumper +Text Notes 3900 5900 0 42 ~ 12 +AVR access default\ndisabled through pull-up +Text Notes 3800 7000 0 42 ~ 12 +FPGA access default\nenabled through pull-down +Text Notes 13630 10230 0 84 ~ 12 +Master Key Memory +Text Notes 11890 4940 0 60 ~ 12 +U12 +Text Notes 11760 6540 0 60 ~ 12 +23K640-I_SN +Text Notes 7500 6200 1 60 ~ 12 +JP6 +Text Notes 7770 6200 1 60 ~ 12 +JP1Q +Text Notes 5120 4720 0 60 ~ 12 +R80 +Text Notes 5270 7070 2 60 ~ 12 +R81 +Text Notes 5500 5080 0 60 ~ 12 +IC4 +Text Notes 5500 5900 0 60 ~ 12 +74*244DW +$Comp +L power:GND GND_87 +U 1 1 58023F8C +P 11300 6500 +F 0 "GND_87" H 11300 6500 20 0000 C CNN +F 1 "+GND" H 11300 6430 30 0000 C CNN +F 2 "" H 11300 6500 70 0000 C CNN +F 3 "" H 11300 6500 70 0000 C CNN + 1 11300 6500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_8 +U 1 1 58023F8B +P 11300 4200 +F 0 "3V3_BATT_8" H 11300 4200 20 0000 C CNN +F 1 "+3V3_BATT" H 11300 4130 30 0000 C CNN +F 2 "" H 11300 4200 70 0000 C CNN +F 3 "" H 11300 4200 70 0000 C CNN + 1 11300 4200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_9 +U 1 1 58023F8A +P 3300 4100 +F 0 "3V3_BATT_9" H 3300 4100 20 0000 C CNN +F 1 "+3V3_BATT" H 3300 4030 30 0000 C CNN +F 2 "" H 3300 4100 70 0000 C CNN +F 3 "" H 3300 4100 70 0000 C CNN + 1 3300 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_10 +U 1 1 58023F89 +P 10800 4200 +F 0 "3V3_BATT_10" H 10800 4200 20 0000 C CNN +F 1 "+3V3_BATT" H 10800 4130 30 0000 C CNN +F 2 "" H 10800 4200 70 0000 C CNN +F 3 "" H 10800 4200 70 0000 C CNN + 1 10800 4200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_88 +U 1 1 58023F88 +P 11500 4700 +F 0 "GND_88" H 11500 4700 20 0000 C CNN +F 1 "+GND" H 11500 4630 30 0000 C CNN +F 2 "" H 11500 4700 70 0000 C CNN +F 3 "" H 11500 4700 70 0000 C CNN + 1 11500 4700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_89 +U 1 1 58023F87 +P 7600 6400 +F 0 "GND_89" H 7600 6400 20 0000 C CNN +F 1 "+GND" H 7600 6330 30 0000 C CNN +F 2 "" H 7600 6400 70 0000 C CNN +F 3 "" H 7600 6400 70 0000 C CNN + 1 7600 6400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_90 +U 1 1 58023F86 +P 3300 5200 +F 0 "GND_90" H 3300 5200 20 0000 C CNN +F 1 "+GND" H 3300 5130 30 0000 C CNN +F 2 "" H 3300 5200 70 0000 C CNN +F 3 "" H 3300 5200 70 0000 C CNN + 1 3300 5200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_91 +U 1 1 58023F85 +P 5000 7500 +F 0 "GND_91" H 5000 7500 20 0000 C CNN +F 1 "+GND" H 5000 7430 30 0000 C CNN +F 2 "" H 5000 7500 70 0000 C CNN +F 3 "" H 5000 7500 70 0000 C CNN + 1 5000 7500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_11 +U 1 1 58023F84 +P 5000 4100 +F 0 "3V3_BATT_11" H 5000 4100 20 0000 C CNN +F 1 "+3V3_BATT" H 5000 4030 30 0000 C CNN +F 2 "" H 5000 4100 70 0000 C CNN +F 3 "" H 5000 4100 70 0000 C CNN + 1 5000 4100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:3V3_BATT 3V3_BATT_12 +U 1 1 58023F83 +P 10100 4220 +F 0 "3V3_BATT_12" H 10100 4220 20 0000 C CNN +F 1 "+3V3_BATT" H 10100 4150 30 0000 C CNN +F 2 "" H 10100 4220 70 0000 C CNN +F 3 "" H 10100 4220 70 0000 C CNN + 1 10100 4220 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11300 6100 11300 6500 +Wire Wire Line + 11400 6100 11300 6100 +Wire Wire Line + 11500 4600 11500 4700 +Wire Wire Line + 7600 6300 7600 6400 +Wire Wire Line + 3300 5100 3300 5200 +Wire Wire Line + 3300 5000 3300 5100 +Wire Wire Line + 2900 4900 2900 5100 +Wire Wire Line + 3300 5100 2900 5100 +Wire Wire Line + 5000 7400 5000 7500 +Wire Wire Line + 11400 5700 10800 5700 +Wire Wire Line + 10800 5000 10800 5700 +Wire Wire Line + 11400 5600 10100 5600 +Text Label 10100 5600 0 48 ~ +MKM_SCK +Wire Wire Line + 6500 5300 6300 5300 +Wire Wire Line + 6500 5300 6500 6400 +Wire Wire Line + 6500 6400 6300 6400 +Wire Wire Line + 7000 5300 6500 5300 +Text Label 7000 5300 0 48 ~ +MKM_SCK +Wire Wire Line + 11400 5500 10100 5500 +Text Label 10100 5500 0 48 ~ +MKM_MOSI +Wire Wire Line + 6600 6500 6300 6500 +Wire Wire Line + 6600 5400 6600 6500 +Wire Wire Line + 6600 5400 6300 5400 +Wire Wire Line + 7000 5400 6600 5400 +Text Label 7000 5400 0 48 ~ +MKM_MOSI +Wire Wire Line + 11400 5400 10500 5400 +Text Label 10140 5400 0 48 ~ +MKM_CS_N +Wire Wire Line + 6400 6300 6300 6300 +Wire Wire Line + 6400 5200 6400 6300 +Wire Wire Line + 6400 5200 6300 5200 +Wire Wire Line + 7000 5200 6400 5200 +Text Label 7000 5200 0 48 ~ +MKM_CS_N +Wire Wire Line + 13150 5200 12800 5200 +Text Label 13150 5200 2 48 ~ 0 +MKM_MISO +Wire Wire Line + 5300 6600 5200 6600 +Wire Wire Line + 5200 5500 5200 6600 +Wire Wire Line + 5300 5500 5200 5500 +Wire Wire Line + 5200 5500 4800 5500 +Text Label 4800 5500 0 48 ~ +MKM_MISO +Wire Wire Line + 11400 5200 11300 5200 +Wire Wire Line + 11300 4300 11300 5200 +Wire Wire Line + 11300 4200 11300 4300 +Wire Wire Line + 11500 4300 11300 4300 +Wire Wire Line + 3300 4100 3300 4300 +Wire Wire Line + 3300 4300 2900 4300 +Wire Wire Line + 2900 4300 2900 4600 +Wire Wire Line + 3300 4300 3300 4400 +Wire Wire Line + 10800 4200 10800 4600 +Wire Wire Line + 5000 4100 5000 4600 +Wire Wire Line + 10100 4220 10100 4620 +Wire Wire Line + 5000 5700 4550 5700 +Wire Wire Line + 5300 5700 5000 5700 +Wire Wire Line + 5000 5000 5000 5700 +Text GLabel 4550 5700 0 48 Input ~ 0 +MKM_CONTROL_AVR_ENA +Wire Wire Line + 5300 5300 4800 5300 +Text GLabel 4800 5300 0 48 Input ~ 0 +MKM_AVR_SCK +Wire Wire Line + 5300 6300 4610 6300 +Text GLabel 4610 6300 0 48 Input ~ 0 +MKM_FPGA_CS_N +Wire Wire Line + 5300 5200 4800 5200 +Text GLabel 4800 5200 0 48 Input ~ 0 +MKM_AVR_CS_N +Wire Wire Line + 5300 6500 4610 6500 +Text GLabel 4610 6500 0 48 Input ~ 0 +MKM_FPGA_MOSI +Wire Wire Line + 5300 5400 4800 5400 +Text GLabel 4800 5400 0 48 Input ~ 0 +MKM_AVR_MOSI +Wire Wire Line + 6500 6600 6300 6600 +Text GLabel 6500 6600 2 48 Output ~ 0 +MKM_FPGA_MISO +Wire Wire Line + 7600 5500 6300 5500 +Wire Wire Line + 7800 5500 7600 5500 +Wire Wire Line + 7600 5500 7600 5700 +Text GLabel 7800 5500 2 48 Output ~ 0 +MKM_AVR_MISO +Wire Wire Line + 5300 6400 4610 6400 +Text GLabel 4610 6400 0 48 Input ~ 0 +MKM_FPGA_SCK +Wire Wire Line + 5300 6800 5000 6800 +Wire Wire Line + 5000 6800 5000 7000 +Wire Wire Line + 5000 6800 4480 6800 +Text GLabel 4480 6800 0 48 Input ~ 0 +MKM_CONTROL_FPGA_DIS +Wire Wire Line + 10100 5400 10100 5020 +Wire Wire Line + 10500 5400 10100 5400 +$Comp +L Cryptech_Alpha:23K640-I_SN U12 +U 1 1 58023F82 +P 12100 5600 +F 0 "U12" H 11570 4670 60 0000 L BNN + 1 12100 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:SOIC127P600X175-8N" H 11570 4670 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_2 IC4_2 +U 1 1 58023F81 +P 5800 6500 +F 0 "IC4_2" H 5470 5970 60 0000 L BNN +F 1 "MC74AC244DW*" H 5510 6920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5510 6920 60 0001 C CNN +F 3 "" H 5510 6920 60 0000 C CNN + 1 5800 6500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_3 IC4_3 +U 1 1 58023F80 +P 3300 4700 +F 0 "IC4_3" H 3330 4550 60 0000 L BNN +F 1 "MC74AC244DW*" H 3480 4680 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 3480 4680 60 0001 C CNN +F 3 "" H 3480 4680 60 0000 C CNN + 1 3300 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R33 +U 1 1 58023F7F +P 10800 4800 +F 0 "R33" V 10741 4550 60 0000 L BNN +F 1 "4.7k" V 10830 4540 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10830 4540 60 0001 C CNN +F 3 "" H 10830 4540 60 0000 C CNN + 1 10800 4800 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R34 +U 1 1 58023F7E +P 10100 4820 +F 0 "R34" V 10171 5167 60 0000 R TNN +F 1 "4.7k" V 10080 5180 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 10080 5180 60 0001 C CNN +F 3 "" H 10080 5180 60 0000 C CNN + 1 10100 4820 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C106 +U 1 1 58023F7D +P 2900 4700 +F 0 "C106" H 2500 4600 60 0000 L BNN +F 1 "0.1uF" H 2490 4500 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2490 4500 60 0001 C CNN +F 3 "" H 2490 4500 60 0000 C CNN + 1 2900 4700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C107 +U 1 1 58023F7C +P 11500 4400 +F 0 "C107" H 11600 4500 60 0000 L BNN +F 1 "0.1uF" H 11600 4400 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 11600 4400 60 0001 C CNN +F 3 "" H 11600 4400 60 0000 C CNN + 1 11500 4400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:JP1Q JP6 +U 1 1 58023F7B +P 7600 6000 +F 0 "JP6" H 7705 6030 60 0000 L BNN + 1 7600 6000 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:PLS-2" H 7705 6030 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R80 +U 1 1 58023F7A +P 5000 4800 +F 0 "R80" V 4910 4755 60 0000 R TNN +F 1 "4.7k" V 4990 4690 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4990 4690 60 0001 C CNN +F 3 "" H 4990 4690 60 0000 C CNN + 1 5000 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R81 +U 1 1 58023F79 +P 5000 7200 +F 0 "R81" V 5090 7245 60 0000 L BNN +F 1 "4.7k" V 5060 7310 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5060 7310 60 0001 C CNN +F 3 "" H 5060 7310 60 0000 C CNN + 1 5000 7200 + 0 1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_1 IC4 +U 1 1 58023F78 +P 5800 5400 +F 0 "IC4" H 5470 4870 60 0000 L BNN +F 1 "MC74AC244DW*" H 5500 5820 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5500 5820 60 0001 C CNN +F 3 "" H 5500 5820 60 0000 C CNN + 1 5800 5400 + 1 0 0 -1 +$EndComp +NoConn ~ 11400 5900 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_13.sch b/KiCAD/rev02_13.sch new file mode 100644 index 0000000..cf36ec9 --- /dev/null +++ b/KiCAD/rev02_13.sch @@ -0,0 +1,621 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 15 27 +Title "rev02_13" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 1100 4300 0 60 ~ 12 +*) Configuration Interface +Text Notes 1000 8700 0 60 ~ 12 +M[2:0] == 3'b001 => Master SPI +Text Notes 700 7400 0 60 ~ 12 +*) Since VCCO is 3.3V, CFGBVS must be tied High.\n*) Battery is not used\n*) PROG_B is dedicated input -- can be driven by STM32 directly\n*) INIT_B is bi-directional open-drain, must be driven with MOSFET to ground +Text Notes 3700 9800 0 60 ~ 12 +*) "Not DONE" LED, should be of red color +Text Notes 8590 10210 0 54 ~ 12 +FPGA configuration interface +Text Notes 1600 9380 0 60 ~ 12 +R35 +Text Notes 2400 9370 0 60 ~ 12 +R36 +Text Notes 6650 5500 0 60 ~ 12 +2N7002 +Text Notes 6450 5510 0 60 ~ 12 +Q4 +Text Notes 5140 9560 2 60 ~ 12 +R39 +Text Notes 7860 8790 0 60 ~ 12 +C108 +Text Notes 7760 8990 0 60 ~ 12 +0.1~uF +Text Notes 1600 4570 0 60 ~ 12 +U13 +Text Notes 1050 6300 0 60 ~ 12 +XC7A200TFBG484 +$Comp +L power:GND GND_92 +U 1 1 58023F77 +P 2200 6300 +F 0 "GND_92" H 2200 6300 20 0000 C CNN +F 1 "+GND" H 2200 6230 30 0000 C CNN +F 2 "" H 2200 6300 70 0000 C CNN +F 3 "" H 2200 6300 70 0000 C CNN + 1 2200 6300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_93 +U 1 1 58023F76 +P 1500 9800 +F 0 "GND_93" H 1500 9800 20 0000 C CNN +F 1 "+GND" H 1500 9730 30 0000 C CNN +F 2 "" H 1500 9800 70 0000 C CNN +F 3 "" H 1500 9800 70 0000 C CNN + 1 1500 9800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_94 +U 1 1 58023F75 +P 2300 9800 +F 0 "GND_94" H 2300 9800 20 0000 C CNN +F 1 "+GND" H 2300 9730 30 0000 C CNN +F 2 "" H 2300 9800 70 0000 C CNN +F 3 "" H 2300 9800 70 0000 C CNN + 1 2300 9800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_95 +U 1 1 58023F74 +P 5800 6400 +F 0 "GND_95" H 5800 6400 20 0000 C CNN +F 1 "+GND" H 5800 6330 30 0000 C CNN +F 2 "" H 5800 6400 70 0000 C CNN +F 3 "" H 5800 6400 70 0000 C CNN + 1 5800 6400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_96 +U 1 1 58023F73 +P 6600 6400 +F 0 "GND_96" H 6600 6400 20 0000 C CNN +F 1 "+GND" H 6600 6330 30 0000 C CNN +F 2 "" H 6600 6400 70 0000 C CNN +F 3 "" H 6600 6400 70 0000 C CNN + 1 6600 6400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_97 +U 1 1 58023F72 +P 9100 9300 +F 0 "GND_97" H 9100 9300 20 0000 C CNN +F 1 "+GND" H 9100 9230 30 0000 C CNN +F 2 "" H 9100 9300 70 0000 C CNN +F 3 "" H 9100 9300 70 0000 C CNN + 1 9100 9300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_98 +U 1 1 58023F71 +P 7700 9300 +F 0 "GND_98" H 7700 9300 20 0000 C CNN +F 1 "+GND" H 7700 9230 30 0000 C CNN +F 2 "" H 7700 9300 70 0000 C CNN +F 3 "" H 7700 9300 70 0000 C CNN + 1 7700 9300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_21 +U 1 1 58023F70 +P 3100 8200 +F 0 "VCCO_3V3_21" H 3100 8200 20 0000 C CNN +F 1 "+VCCO_3V3" H 3100 8130 30 0000 C CNN +F 2 "" H 3100 8200 70 0000 C CNN +F 3 "" H 3100 8200 70 0000 C CNN + 1 3100 8200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_22 +U 1 1 58023F6F +P 4700 8200 +F 0 "VCCO_3V3_22" H 4700 8200 20 0000 C CNN +F 1 "+VCCO_3V3" H 4700 8130 30 0000 C CNN +F 2 "" H 4700 8200 70 0000 C CNN +F 3 "" H 4700 8200 70 0000 C CNN + 1 4700 8200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_23 +U 1 1 58023F6E +P 7700 8200 +F 0 "VCCO_3V3_23" H 7700 8200 20 0000 C CNN +F 1 "+VCCO_3V3" H 7700 8130 30 0000 C CNN +F 2 "" H 7700 8200 70 0000 C CNN +F 3 "" H 7700 8200 70 0000 C CNN + 1 7700 8200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_24 +U 1 1 58023F6D +P 9100 7400 +F 0 "VCCO_3V3_24" H 9100 7400 20 0000 C CNN +F 1 "+VCCO_3V3" H 9100 7330 30 0000 C CNN +F 2 "" H 9100 7400 70 0000 C CNN +F 3 "" H 9100 7400 70 0000 C CNN + 1 9100 7400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_25 +U 1 1 58023F6C +P 2400 4500 +F 0 "VCCO_3V3_25" H 2400 4500 20 0000 C CNN +F 1 "+VCCO_3V3" H 2400 4430 30 0000 C CNN +F 2 "" H 2400 4500 70 0000 C CNN +F 3 "" H 2400 4500 70 0000 C CNN + 1 2400 4500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_26 +U 1 1 58023F6B +P 6000 4100 +F 0 "VCCO_3V3_26" H 6000 4100 20 0000 C CNN +F 1 "+VCCO_3V3" H 6000 4030 30 0000 C CNN +F 2 "" H 6000 4100 70 0000 C CNN +F 3 "" H 6000 4100 70 0000 C CNN + 1 6000 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2200 4700 2200 6300 +Wire Wire Line + 2200 4700 2000 4700 +Wire Wire Line + 1500 9600 1500 9800 +Wire Wire Line + 2300 9600 2300 9800 +Wire Wire Line + 6000 5600 5800 5600 +Wire Wire Line + 5800 5600 5800 6400 +Wire Wire Line + 6600 6200 6600 6400 +Wire Wire Line + 9100 9100 9100 9300 +Wire Wire Line + 9300 9100 9100 9100 +Wire Wire Line + 9300 9000 9100 9000 +Wire Wire Line + 9100 9000 9100 9100 +Wire Wire Line + 9300 8900 9100 8900 +Wire Wire Line + 9100 8900 9100 9000 +Connection ~ 9100 9100 +Connection ~ 9100 9000 +Wire Wire Line + 7700 9000 7700 9300 +Wire Wire Line + 3100 8200 3100 8400 +Wire Wire Line + 4700 8200 4700 8500 +Wire Wire Line + 9000 7700 9000 7800 +Wire Wire Line + 9100 7700 9000 7700 +Wire Wire Line + 9200 7700 9100 7700 +Wire Wire Line + 9200 7700 9200 7800 +Wire Wire Line + 9100 7700 9100 7800 +Wire Wire Line + 9100 7400 9100 7700 +Connection ~ 9100 7700 +Wire Wire Line + 9300 8400 7700 8400 +Wire Wire Line + 7700 8200 7700 8400 +Wire Wire Line + 7700 8400 7700 8700 +Connection ~ 7700 8400 +Wire Wire Line + 6000 4300 5800 4300 +Wire Wire Line + 6200 4300 6000 4300 +Wire Wire Line + 6200 4300 6200 4500 +Wire Wire Line + 5800 4300 5800 4500 +Wire Wire Line + 6000 4100 6000 4300 +Connection ~ 6000 4300 +Wire Wire Line + 2400 4800 2000 4800 +Wire Wire Line + 2400 4900 2000 4900 +Wire Wire Line + 2400 4800 2400 4900 +Wire Wire Line + 2400 5000 2000 5000 +Wire Wire Line + 2400 4900 2400 5000 +Wire Wire Line + 2400 4500 2400 4800 +Connection ~ 2400 4800 +Connection ~ 2400 4900 +Wire Wire Line + 3400 5700 2000 5700 +Text Label 3400 5700 2 48 ~ 0 +FPGA_M2 +Wire Wire Line + 1500 9000 1500 9200 +Wire Wire Line + 1500 9000 900 9000 +Text Label 900 9000 0 48 ~ 0 +FPGA_M2 +Wire Wire Line + 3400 5800 2000 5800 +Text Label 3400 5800 2 48 ~ 0 +FPGA_JTAG_TCK +Text Label 8430 8500 0 48 ~ +FPGA_JTAG_TCK +Wire Wire Line + 3400 5900 2000 5900 +Text Label 3400 5900 2 48 ~ 0 +FPGA_JTAG_TDI +Wire Wire Line + 9000 8700 8800 8700 +Wire Wire Line + 9300 8700 9000 8700 +Wire Wire Line + 8800 8700 8430 8700 +Text Label 8430 8700 0 48 ~ +FPGA_JTAG_TDI +Wire Wire Line + 3400 6000 2000 6000 +Text Label 3400 6000 2 48 ~ 0 +FPGA_JTAG_TDO +Wire Wire Line + 9300 8800 8430 8800 +Text Label 8430 8800 0 48 ~ +FPGA_JTAG_TDO +Wire Wire Line + 3400 6100 2000 6100 +Text Label 3400 6100 2 48 ~ 0 +FPGA_JTAG_TMS +Wire Wire Line + 9100 8600 8900 8600 +Wire Wire Line + 9300 8600 9100 8600 +Wire Wire Line + 8900 8600 8430 8600 +Text Label 8430 8600 0 48 ~ +FPGA_JTAG_TMS +Wire Wire Line + 6200 4900 6200 5100 +Wire Wire Line + 7600 5100 6200 5100 +Text GLabel 7600 5100 2 48 Input ~ 0 +FPGA_PROGRAM_B +Wire Wire Line + 3940 5300 3240 5300 +Text GLabel 3940 5300 2 48 Input ~ 0 +FPGA_PROGRAM_B +Wire Wire Line + 3400 5100 2000 5100 +Text Label 3400 5100 2 48 ~ 0 +FPGA_DONE_INT +Wire Wire Line + 4700 9400 4700 9500 +Wire Wire Line + 4700 9500 3700 9500 +Wire Wire Line + 5000 9500 4700 9500 +Text Label 3700 9500 0 48 ~ +FPGA_DONE_INT +Connection ~ 4700 9500 +Wire Wire Line + 3400 5500 2000 5500 +Text Label 3400 5500 2 48 ~ 0 +FPGA_M0 +Wire Wire Line + 3100 9000 2500 9000 +Wire Wire Line + 3100 8800 3100 9000 +Text Label 2500 9000 0 48 ~ 0 +FPGA_M0 +Wire Wire Line + 3400 5600 2000 5600 +Text Label 3400 5600 2 48 ~ 0 +FPGA_M1 +Wire Wire Line + 2300 9000 1700 9000 +Wire Wire Line + 2300 9000 2300 9200 +Text Label 1700 9000 0 48 ~ 0 +FPGA_M1 +Wire Wire Line + 5800 4900 5800 5400 +Wire Wire Line + 5800 5400 4800 5400 +Wire Wire Line + 6000 5400 5800 5400 +Text Label 4800 5400 0 48 ~ +FPGA_INIT_B_INT +Connection ~ 5800 5400 +Wire Wire Line + 3940 5200 3240 5200 +Text Label 3940 5200 2 48 ~ 0 +FPGA_INIT_B_INT +Wire Wire Line + 6600 5600 6400 5600 +Wire Wire Line + 6600 5600 6600 5800 +Wire Wire Line + 7600 5600 6600 5600 +Text GLabel 7600 5600 2 48 BiDi ~ 0 +FPGA_INIT_B +Connection ~ 6600 5600 +Wire Wire Line + 4700 8900 4700 9100 +Wire Wire Line + 5700 9500 5400 9500 +Text GLabel 5700 9500 2 48 Output ~ 0 +FPGA_DONE +Wire Wire Line + 3940 5400 3240 5400 +Text GLabel 3940 5400 2 48 Output ~ 0 +FPGA_CFG_SCLK +Wire Wire Line + 2840 5200 2000 5200 +Text Label 2220 5200 0 48 ~ +FPGA_INIT_B_INT1 +Wire Wire Line + 2840 5300 2000 5300 +Text Label 2220 5300 0 48 ~ +FPGA_PROGRAM_B1 +Wire Wire Line + 2840 5400 2000 5400 +Text Label 2220 5400 0 48 ~ +FPGA_CFG_SCLK1 +Wire Wire Line + 9100 8600 9100 8200 +Wire Wire Line + 9200 8500 9200 8200 +Wire Wire Line + 9000 8700 9000 8200 +Wire Wire Line + 9200 8500 9300 8500 +Wire Wire Line + 8430 8500 9200 8500 +Connection ~ 9000 8700 +Connection ~ 9100 8600 +Connection ~ 9200 8500 +$Comp +L Cryptech_Alpha:R-EU_R0402 R35 +U 1 1 58023F6A +P 1500 9400 +F 0 "R35" V 1410 9355 60 0000 R TNN +F 1 "1k" V 1430 9310 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1430 9310 60 0001 C CNN +F 3 "" H 1430 9310 60 0000 C CNN + 1 1500 9400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R39 +U 1 1 58023F69 +P 5200 9500 +F 0 "R39" H 5310 9645 60 0000 R TNN +F 1 "100" H 5220 9650 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5220 9650 60 0001 C CNN +F 3 "" H 5220 9650 60 0000 C CNN + 1 5200 9500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:MA08-1 SV1 +U 1 1 58023F68 +P 9600 8700 +F 0 "SV1" H 9780 9330 60 0000 R TNN +F 1 "MA08-1" H 9560 9330 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:PLS-8" H 9560 9330 60 0001 C CNN +F 3 "" H 9560 9330 60 0000 C CNN + 1 9600 8700 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C108 +U 1 1 58023F67 +P 7700 8800 +F 0 "C108" H 7780 8610 60 0000 L BNN +F 1 "0.1uF" H 7860 8710 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7860 8710 60 0001 C CNN +F 3 "" H 7860 8710 60 0000 C CNN + 1 7700 8800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R43 +U 1 1 58023F66 +P 9000 8000 +F 0 "R43" V 9159 7650 60 0000 R TNN +F 1 "10k" V 9170 7450 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7450 60 0001 C CNN +F 3 "" H 9170 7450 60 0000 C CNN + 1 9000 8000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R44 +U 1 1 58023F65 +P 9100 8000 +F 0 "R44" V 9159 7750 60 0000 R TNN +F 1 "10k" V 9170 7550 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7550 60 0001 C CNN +F 3 "" H 9170 7550 60 0000 C CNN + 1 9100 8000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R45 +U 1 1 58023F64 +P 9200 8000 +F 0 "R45" V 9159 7850 60 0000 R TNN +F 1 "10k" V 9170 7650 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7650 60 0001 C CNN +F 3 "" H 9170 7650 60 0000 C CNN + 1 9200 8000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R62 +U 1 1 58023F63 +P 3040 5200 +F 0 "R62" H 3150 4890 60 0000 R TNN +F 1 "0" H 2940 4890 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 4890 60 0001 C CNN +F 3 "" H 2940 4890 60 0000 C CNN + 1 3040 5200 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R63 +U 1 1 58023F62 +P 3040 5300 +F 0 "R63" H 3150 4960 60 0000 R TNN +F 1 "0" H 2940 4950 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 4950 60 0001 C CNN +F 3 "" H 2940 4950 60 0000 C CNN + 1 3040 5300 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R71 +U 1 1 58023F61 +P 3040 5400 +F 0 "R71" H 3150 5030 60 0000 R TNN +F 1 "0" H 2940 5020 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 5020 60 0001 C CNN +F 3 "" H 2940 5020 60 0000 C CNN + 1 3040 5400 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_1 U13 +U 1 1 58023F60 +P 1800 5400 +F 0 "U13" H 1390 4490 60 0000 L BNN + 1 1800 5400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1390 4490 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R36 +U 1 1 58023F5F +P 2300 9400 +F 0 "R36" V 2210 9355 60 0000 R TNN +F 1 "1k" V 2240 9310 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2240 9310 60 0001 C CNN +F 3 "" H 2240 9310 60 0000 C CNN + 1 2300 9400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R37 +U 1 1 58023F5E +P 3100 8600 +F 0 "R37" V 3159 8450 60 0000 R TNN +F 1 "1k" V 3060 8460 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3060 8460 60 0001 C CNN +F 3 "" H 3060 8460 60 0000 C CNN + 1 3100 8600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R41 +U 1 1 58023F5D +P 6200 4700 +F 0 "R41" V 6271 4547 60 0000 R TNN +F 1 "4.7k" V 6190 4550 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6190 4550 60 0001 C CNN +F 3 "" H 6190 4550 60 0000 C CNN + 1 6200 4700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R40 +U 1 1 58023F5C +P 5800 4700 +F 0 "R40" V 5871 5047 60 0000 R TNN +F 1 "4.7k" V 5780 5050 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5780 5050 60 0001 C CNN +F 3 "" H 5780 5050 60 0000 C CNN + 1 5800 4700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:2N7002 Q4 +U 1 1 58023F5B +P 6200 5500 +F 0 "Q4" H 6310 5245 60 0000 R BNN +F 1 "2N7002P,235" H 6420 5655 60 0000 R BNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 6420 5655 60 0001 C CNN +F 3 "" H 6420 5655 60 0000 C CNN + 1 6200 5500 + -1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R42 +U 1 1 58023F5A +P 6600 6000 +F 0 "R42" V 6559 5850 60 0000 R TNN +F 1 "4.7k" V 6470 5850 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6470 5850 60 0001 C CNN +F 3 "" H 6470 5850 60 0000 C CNN + 1 6600 6000 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED13 +U 1 1 58023F59 +P 4700 9200 +F 0 "LED13" H 4820 9260 60 0000 L BNN +F 1 "LTST-C191KRKT" H 4820 9075 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 4820 9075 60 0001 C CNN +F 3 "" H 4820 9075 60 0000 C CNN + 1 4700 9200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R38 +U 1 1 58023F58 +P 4700 8700 +F 0 "R38" V 4759 8550 60 0000 R TNN +F 1 "330" V 4670 8560 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4670 8560 60 0001 C CNN +F 3 "" H 4670 8560 60 0000 C CNN + 1 4700 8700 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_14.sch b/KiCAD/rev02_14.sch new file mode 100644 index 0000000..dc40131 --- /dev/null +++ b/KiCAD/rev02_14.sch @@ -0,0 +1,190 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 16 27 +Title "rev02_14" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 7500 4300 0 60 ~ 12 +*) Temperature Sensor [NOT USED] +Text Notes 5200 4300 0 60 ~ 12 +*) XADC [NOT USED] +Text Notes 1100 4200 0 60 ~ 12 +*) Transceivers [NOT USED] +Text Notes 8810 10230 0 84 ~ 12 +FPGA unused +Text Notes 6160 4990 0 60 ~ 12 +C109 +Text Notes 6160 5190 0 60 ~ 12 +0.1~uF +$Comp +L power:GND GND_99 +U 1 1 58023F57 +P 8700 5000 +F 0 "GND_99" H 8700 5000 20 0000 C CNN +F 1 "+GND" H 8700 4930 30 0000 C CNN +F 2 "" H 8700 5000 70 0000 C CNN +F 3 "" H 8700 5000 70 0000 C CNN + 1 8700 5000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_100 +U 1 1 58023F56 +P 5700 5400 +F 0 "GND_100" H 5700 5400 20 0000 C CNN +F 1 "+GND" H 5700 5330 30 0000 C CNN +F 2 "" H 5700 5400 70 0000 C CNN +F 3 "" H 5700 5400 70 0000 C CNN + 1 5700 5400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_101 +U 1 1 58023F55 +P 6100 5400 +F 0 "GND_101" H 6100 5400 20 0000 C CNN +F 1 "+GND" H 6100 5330 30 0000 C CNN +F 2 "" H 6100 5400 70 0000 C CNN +F 3 "" H 6100 5400 70 0000 C CNN + 1 6100 5400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FPGA_VCCAUX_1V8 FPGA_VCCAUX_1V8 +U 1 1 58023F54 +P 6100 4500 +F 0 "FPGA_VCCAUX_1V8" H 6100 4500 20 0000 C CNN +F 1 "+FPGA_VCCAUX_1V8" H 6100 4430 30 0000 C CNN +F 2 "" H 6100 4500 70 0000 C CNN +F 3 "" H 6100 4500 70 0000 C CNN + 1 6100 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 5200 5500 5200 +Wire Wire Line + 5700 5200 5700 5400 +Wire Wire Line + 5700 5100 5500 5100 +Wire Wire Line + 5700 5100 5700 5200 +Wire Wire Line + 5700 5000 5500 5000 +Wire Wire Line + 5700 5000 5700 5100 +Wire Wire Line + 6100 5200 6100 5400 +Wire Wire Line + 8700 4800 8500 4800 +Wire Wire Line + 8700 4800 8700 5000 +Wire Wire Line + 8700 4700 8500 4700 +Wire Wire Line + 8700 4700 8700 4800 +Wire Wire Line + 6100 4700 5500 4700 +Wire Wire Line + 6100 4700 6100 4900 +Wire Wire Line + 6100 4500 6100 4700 +$Comp +L Cryptech_Alpha:C-EUC0402 C109 +U 1 1 58023F53 +P 6100 5000 +F 0 "C109" H 6180 4810 60 0000 L BNN +F 1 "0.1uF" H 6420 5020 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6420 5020 60 0001 C CNN +F 3 "" H 6420 5020 60 0000 C CNN + 1 6100 5000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_8 U13_2 +U 1 1 58023F52 +P 1900 7900 +F 0 "U13_2" H 1490 6690 60 0000 L BNN + 1 1900 7900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1490 6690 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_11 U13_3 +U 1 1 58023F51 +P 1900 5000 +F 0 "U13_3" H 1490 4590 60 0000 L BNN + 1 1900 5000 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1490 4590 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_12 U13_4 +U 1 1 58023F50 +P 1900 6000 +F 0 "U13_4" H 1490 5490 60 0000 L BNN + 1 1900 6000 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1490 5490 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_13 U13_5 +U 1 1 58023F4F +P 8300 4700 +F 0 "U13_5" H 7890 4390 60 0000 L BNN + 1 8300 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 7890 4390 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_17 U13_6 +U 1 1 58023F4E +P 5300 4900 +F 0 "U13_6" H 4890 4390 60 0000 L BNN + 1 5300 4900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 4890 4390 60 0001 C CNN +$EndComp +NoConn ~ 5500 4800 +NoConn ~ 5500 4900 +NoConn ~ 2100 4800 +NoConn ~ 2100 4900 +NoConn ~ 2100 5000 +NoConn ~ 2100 5100 +NoConn ~ 2100 5200 +NoConn ~ 2100 5800 +NoConn ~ 2100 5900 +NoConn ~ 2100 6000 +NoConn ~ 2100 6100 +NoConn ~ 2100 6200 +NoConn ~ 2100 6300 +NoConn ~ 2100 6900 +NoConn ~ 2100 7000 +NoConn ~ 2100 7100 +NoConn ~ 2100 7200 +NoConn ~ 2100 7300 +NoConn ~ 2100 7400 +NoConn ~ 2100 7500 +NoConn ~ 2100 7600 +NoConn ~ 2100 7700 +NoConn ~ 2100 7800 +NoConn ~ 2100 7900 +NoConn ~ 2100 8000 +NoConn ~ 2100 8100 +NoConn ~ 2100 8300 +NoConn ~ 2100 8200 +NoConn ~ 2100 8400 +NoConn ~ 2100 8500 +NoConn ~ 2100 8600 +NoConn ~ 2100 8700 +NoConn ~ 2100 8800 +NoConn ~ 2100 8900 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_15.sch b/KiCAD/rev02_15.sch new file mode 100644 index 0000000..15ab3eb --- /dev/null +++ b/KiCAD/rev02_15.sch @@ -0,0 +1,583 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 17 27 +Title "rev02_15" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 7100 4900 0 60 ~ 12 +*) HOLD feature not used\n*) PROM is write-protected by default, to disable\nwrite protection (such as during firmware update),\njumper must be inserted +Text Notes 4800 8600 0 84 ~ 12 +FPGA clock +Text Notes 7100 4200 0 84 ~ 12 +FPGA config memory, 128 Mbit +Text Notes 1260 3930 0 84 ~ 12 +SPI mux to let ARM override access to\nFPGA config memory (to reprogram FPGA) +Text Notes 420 6220 0 42 ~ 12 +Install this jumper to allow\nARM to configure the FPGA +Text Notes 3490 4850 0 42 ~ 12 +ARM access default\ndisabled through pull-up +Text Notes 3190 7830 0 42 ~ 12 +FPGA access default\nenabled through pull-down +Text Notes 430 6540 0 42 ~ 12 +Install this jumper to allow\nARM to configure the FPGA +Text Notes 8520 10210 0 60 ~ 12 +FPGA supporting components +Text Notes 7900 6180 0 60 ~ 12 +IC3 +Text Notes 8460 6180 0 60 ~ 12 +N25Q128A13ES +Text Notes 7700 5900 0 60 ~ 12 +R51 +Text Notes 6800 6900 0 60 ~ 12 +R50 +Text Notes 4460 9590 0 60 ~ 12 +C111 +Text Notes 4460 9790 0 60 ~ 12 +0.01uF +Text Notes 5650 8770 2 60 ~ 12 +R49 +Text Notes 3470 4640 0 60 ~ 12 +R46 +Text Notes 3210 7520 2 60 ~ 12 +R47 +Text Notes 6450 9560 2 60 ~ 12 +R4 +Text Notes 3860 5510 0 60 ~ 12 +IC2 +Text Notes 3860 6330 0 60 ~ 12 +74*244DW +$Comp +L power:GND GND_102 +U 1 1 58023F4D +P 7600 7300 +F 0 "GND_102" H 7600 7300 20 0000 C CNN +F 1 "+GND" H 7600 7230 30 0000 C CNN +F 2 "" H 7600 7300 70 0000 C CNN +F 3 "" H 7600 7300 70 0000 C CNN + 1 7600 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_103 +U 1 1 58023F4C +P 6700 7300 +F 0 "GND_103" H 6700 7300 20 0000 C CNN +F 1 "+GND" H 6700 7230 30 0000 C CNN +F 2 "" H 6700 7300 70 0000 C CNN +F 3 "" H 6700 7300 70 0000 C CNN + 1 6700 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_104 +U 1 1 58023F4B +P 10000 7300 +F 0 "GND_104" H 10000 7300 20 0000 C CNN +F 1 "+GND" H 10000 7230 30 0000 C CNN +F 2 "" H 10000 7300 70 0000 C CNN +F 3 "" H 10000 7300 70 0000 C CNN + 1 10000 7300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_105 +U 1 1 58023F4A +P 5000 10000 +F 0 "GND_105" H 5000 10000 20 0000 C CNN +F 1 "+GND" H 5000 9930 30 0000 C CNN +F 2 "" H 5000 10000 70 0000 C CNN +F 3 "" H 5000 10000 70 0000 C CNN + 1 5000 10000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_106 +U 1 1 58023F49 +P 4400 10000 +F 0 "GND_106" H 4400 10000 20 0000 C CNN +F 1 "+GND" H 4400 9930 30 0000 C CNN +F 2 "" H 4400 10000 70 0000 C CNN +F 3 "" H 4400 10000 70 0000 C CNN + 1 4400 10000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_27 +U 1 1 58023F48 +P 6700 5200 +F 0 "VCCO_3V3_27" H 6700 5200 20 0000 C CNN +F 1 "+VCCO_3V3" H 6700 5130 30 0000 C CNN +F 2 "" H 6700 5200 70 0000 C CNN +F 3 "" H 6700 5200 70 0000 C CNN + 1 6700 5200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_28 +U 1 1 58023F47 +P 4400 8900 +F 0 "VCCO_3V3_28" H 4400 8900 20 0000 C CNN +F 1 "+VCCO_3V3" H 4400 8830 30 0000 C CNN +F 2 "" H 4400 8900 70 0000 C CNN +F 3 "" H 4400 8900 70 0000 C CNN + 1 4400 8900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_29 +U 1 1 58023F46 +P 1660 4630 +F 0 "VCCO_3V3_29" H 1660 4630 20 0000 C CNN +F 1 "+VCCO_3V3" H 1660 4560 30 0000 C CNN +F 2 "" H 1660 4630 70 0000 C CNN +F 3 "" H 1660 4630 70 0000 C CNN + 1 1660 4630 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_107 +U 1 1 58023F45 +P 1660 5630 +F 0 "GND_107" H 1660 5630 20 0000 C CNN +F 1 "+GND" H 1660 5560 30 0000 C CNN +F 2 "" H 1660 5630 70 0000 C CNN +F 3 "" H 1660 5630 70 0000 C CNN + 1 1660 5630 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_30 +U 1 1 58023F44 +P 3360 4300 +F 0 "VCCO_3V3_30" H 3360 4300 20 0000 C CNN +F 1 "+VCCO_3V3" H 3360 4230 30 0000 C CNN +F 2 "" H 3360 4300 70 0000 C CNN +F 3 "" H 3360 4300 70 0000 C CNN + 1 3360 4300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_108 +U 1 1 58023F43 +P 2960 7930 +F 0 "GND_108" H 2960 7930 20 0000 C CNN +F 1 "+GND" H 2960 7860 30 0000 C CNN +F 2 "" H 2960 7930 70 0000 C CNN +F 3 "" H 2960 7930 70 0000 C CNN + 1 2960 7930 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 6600 7600 7300 +Wire Wire Line + 7700 6600 7600 6600 +Wire Wire Line + 6700 7100 6700 7300 +Wire Wire Line + 10000 7000 10000 7300 +Wire Wire Line + 5000 9700 5000 10000 +Wire Wire Line + 5100 9700 5000 9700 +Wire Wire Line + 4400 9800 4400 10000 +Wire Wire Line + 1660 5530 1660 5630 +Wire Wire Line + 1660 5430 1660 5530 +Wire Wire Line + 1260 5330 1260 5530 +Wire Wire Line + 1660 5530 1260 5530 +Wire Wire Line + 2960 7830 2960 7930 +Wire Wire Line + 7600 5500 7600 5700 +Wire Wire Line + 7600 5500 6700 5500 +Wire Wire Line + 6700 5200 6700 5500 +Wire Wire Line + 9400 6300 9150 6300 +Wire Wire Line + 9400 5500 9400 6300 +Wire Wire Line + 9400 5500 7600 5500 +Wire Wire Line + 9400 6400 9150 6400 +Wire Wire Line + 9400 6300 9400 6400 +Wire Wire Line + 10000 6400 10000 6700 +Wire Wire Line + 10000 6400 9400 6400 +Wire Wire Line + 4400 9300 4400 9500 +Wire Wire Line + 5000 9300 4400 9300 +Wire Wire Line + 5100 9300 5000 9300 +Wire Wire Line + 4400 8900 4400 9300 +Wire Wire Line + 5400 8900 5000 8900 +Wire Wire Line + 5000 8900 5000 9300 +Wire Wire Line + 1660 4730 1660 4830 +Wire Wire Line + 1660 4630 1660 4730 +Wire Wire Line + 1260 4730 1260 5030 +Wire Wire Line + 1660 4730 1260 4730 +Wire Wire Line + 3360 4420 3360 4500 +Wire Wire Line + 3360 4300 3360 4420 +Wire Wire Line + 9770 6500 9150 6500 +Text Label 9150 6500 0 48 ~ +FPGA_PROM_SCLK +Wire Wire Line + 4860 5730 4660 5730 +Wire Wire Line + 4860 5730 4860 6830 +Wire Wire Line + 4860 6830 4660 6830 +Wire Wire Line + 5160 5730 4860 5730 +Text Label 5160 5730 0 48 ~ +FPGA_PROM_SCLK +Wire Wire Line + 9770 6600 9150 6600 +Text Label 9150 6600 0 48 ~ +FPGA_PROM_MOSI +Wire Wire Line + 4960 6930 4660 6930 +Wire Wire Line + 4960 5830 4960 6930 +Wire Wire Line + 4960 5830 4660 5830 +Wire Wire Line + 5160 5830 4960 5830 +Text Label 5160 5830 0 48 ~ +FPGA_PROM_MOSI +Wire Wire Line + 7700 6300 7600 6300 +Wire Wire Line + 7600 6100 7600 6300 +Wire Wire Line + 7600 6300 6900 6300 +Text Label 6900 6300 0 48 ~ +FPGA_PROM_CS_N +Wire Wire Line + 4760 6730 4660 6730 +Wire Wire Line + 4760 5630 4760 6730 +Wire Wire Line + 4760 5630 4660 5630 +Wire Wire Line + 5160 5630 4760 5630 +Text Label 5160 5630 0 48 ~ +FPGA_PROM_CS_N +Wire Wire Line + 7700 6400 6900 6400 +Text Label 6900 6400 0 48 ~ +FPGA_PROM_MISO +Wire Wire Line + 3660 5930 3560 5930 +Wire Wire Line + 3560 5930 2980 5930 +Wire Wire Line + 3660 7030 3560 7030 +Wire Wire Line + 3560 5930 3560 7030 +Text Label 2980 5930 0 48 ~ +FPGA_PROM_MISO +Wire Wire Line + 7700 6500 6700 6500 +Wire Wire Line + 6700 6500 6700 6700 +Text Label 6900 6500 0 48 ~ +FPGA_PROM_W_N +Wire Wire Line + 7000 9500 6700 9500 +Text GLabel 6700 9500 0 48 Input ~ 0 +FPGA_GCLK +Wire Wire Line + 6200 9300 6100 9300 +Wire Wire Line + 6200 8900 6200 9300 +Wire Wire Line + 6200 8900 5800 8900 +Wire Wire Line + 3660 6830 3090 6830 +Text GLabel 3090 6830 0 48 Input ~ 0 +FPGA_CFG_SCLK +Wire Wire Line + 3660 6930 3090 6930 +Text GLabel 3090 6930 0 48 Input ~ 0 +FPGA_CFG_MOSI +Wire Wire Line + 3660 6730 3090 6730 +Text GLabel 3090 6730 0 48 Input ~ 0 +FPGA_CFG_CS_N +Wire Wire Line + 5160 7030 4660 7030 +Text GLabel 5160 7030 2 48 Output ~ 0 +FPGA_CFG_MISO +Wire Wire Line + 3660 5630 2980 5630 +Text GLabel 2980 5630 0 48 Input ~ 0 +ARM_FPGA_CFG_CS_N +Wire Wire Line + 3660 5830 2980 5830 +Text GLabel 2980 5830 0 48 Input ~ 0 +ARM_FPGA_CFG_MOSI +Wire Wire Line + 5160 5930 4660 5930 +Text GLabel 5160 5930 2 48 Output ~ 0 +ARM_FPGA_CFG_MISO +Wire Wire Line + 3660 5730 2980 5730 +Text GLabel 2980 5730 0 48 Input ~ 0 +ARM_FPGA_CFG_SCLK +Text Label 3360 5510 1 48 ~ +SPI_A_TRISTATE +Text Label 3060 7230 0 48 ~ +SPI_B_TRISTATE +Text GLabel 430 6430 0 48 Input ~ 0 +FPGA_CFG_CTRL_FPGA_DIS +Wire Wire Line + 6300 9500 6100 9500 +Text Notes 5320 9730 0 54 ~ 12 +GND +Text Notes 5320 9330 0 54 ~ 12 +VCC +Text Notes 5760 9660 0 54 ~ 12 +FO +Text Notes 5750 9300 0 54 ~ 12 +OE +Text Notes 1890 6120 0 60 ~ 12 +1 +Text Notes 2190 6120 0 60 ~ 12 +2 +Text Notes 1890 6220 0 60 ~ 12 +3 +Text Notes 2190 6220 0 60 ~ 12 +4 +Text Notes 1890 6320 0 60 ~ 12 +5 +Text Notes 2190 6320 0 60 ~ 12 +6 +Wire Wire Line + 3360 4900 3360 6130 +Wire Wire Line + 2960 7230 2960 7430 +Wire Wire Line + 3660 7230 2960 7230 +Wire Wire Line + 2960 6230 2960 7230 +Wire Wire Line + 2360 6230 2960 6230 +Wire Wire Line + 1560 6430 430 6430 +Wire Wire Line + 1560 6230 1560 6430 +Wire Wire Line + 1760 6230 1560 6230 +Wire Wire Line + 1640 6830 420 6830 +Wire Wire Line + 1640 6330 1640 6830 +Wire Wire Line + 1760 6330 1640 6330 +Wire Wire Line + 2710 6330 2360 6330 +Wire Wire Line + 2710 4420 2710 6330 +Wire Wire Line + 3360 4420 2710 4420 +Text Label 420 6830 0 48 ~ +FPGA_PROM_W_N +Wire Wire Line + 3360 6130 2360 6130 +Wire Wire Line + 3660 6130 3360 6130 +Wire Wire Line + 430 6130 1760 6130 +Text GLabel 430 6130 0 48 Input ~ 0 +FPGA_CFG_CTRL_ARM_ENA +Connection ~ 3360 4420 +$Comp +L Cryptech_Alpha:N25Q128A13ES IC3 +U 1 1 58023F42 +P 8400 6550 +F 0 "IC3" H 7890 6290 60 0000 L BNN +F 1 "N25Q128A13ESE*" H 8100 6920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO08" H 8100 6920 60 0001 C CNN +F 3 "" H 8100 6920 60 0000 C CNN + 1 8400 6550 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R4 +U 1 1 58023F41 +P 6500 9500 +F 0 "R4" H 6610 9645 60 0000 R TNN +F 1 "0" H 6460 9660 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6460 9660 60 0001 C CNN +F 3 "" H 6460 9660 60 0000 C CNN + 1 6500 9500 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_1 IC2 +U 1 1 58023F40 +P 4160 5830 +F 0 "IC2" H 3830 5300 60 0000 L BNN +F 1 "MC74AC244DW*" H 3850 5300 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 3850 5300 60 0001 C CNN +F 3 "" H 3850 5300 60 0000 C CNN + 1 4160 5830 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_2 IC2_2 +U 1 1 58023F3F +P 4160 6930 +F 0 "IC2_2" H 3830 6400 60 0000 L BNN +F 1 "MC74AC244DW*" H 3860 6390 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 3860 6390 60 0001 C CNN +F 3 "" H 3860 6390 60 0000 C CNN + 1 4160 6930 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:74*244DW_3 IC2_3 +U 1 1 58023F3E +P 1660 5130 +F 0 "IC2_3" H 1690 4980 60 0000 L BNN +F 1 "MC74AC244DW*" H 1860 5110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 1860 5110 60 0001 C CNN +F 3 "" H 1860 5110 60 0000 C CNN + 1 1660 5130 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:ASF* Q5 +U 1 1 58023F3D +P 5600 9500 +F 0 "Q5" H 5270 9070 60 0000 L BNN +F 1 "ASFL1-50.000MHZ-EK-T" H 5080 9830 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:ASF" H 5080 9830 60 0001 C CNN +F 3 "" H 5080 9830 60 0000 C CNN + 1 5600 9500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:M03X2NO_SILK JP7 +U 1 1 58023F3C +P 2060 6230 +F 0 "JP7" H 1850 5920 60 0000 L BNN + 1 2060 6230 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 1850 5920 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R51 +U 1 1 58023F3B +P 7600 5900 +F 0 "R51" V 7510 5855 60 0000 R TNN +F 1 "4.7k" V 7510 5810 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 7510 5810 60 0001 C CNN +F 3 "" H 7510 5810 60 0000 C CNN + 1 7600 5900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R50 +U 1 1 58023F3A +P 6700 6900 +F 0 "R50" V 6610 6855 60 0000 R TNN +F 1 "4.7k" V 6620 6800 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 6620 6800 60 0001 C CNN +F 3 "" H 6620 6800 60 0000 C CNN + 1 6700 6900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C111 +U 1 1 58023F39 +P 4400 9600 +F 0 "C111" H 4480 9410 60 0000 L BNN + 1 4400 9600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4480 9410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R49 +U 1 1 58023F38 +P 5600 8900 +F 0 "R49" H 5710 9045 60 0000 R TNN +F 1 "0" H 5710 9060 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5710 9060 60 0001 C CNN +F 3 "" H 5710 9060 60 0000 C CNN + 1 5600 8900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C112 +U 1 1 58023F37 +P 10000 6800 +F 0 "C112" H 9660 6615 60 0000 L BNN +F 1 "0.1uF" H 9660 6530 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 9660 6530 60 0001 C CNN +F 3 "" H 9660 6530 60 0000 C CNN + 1 10000 6800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C110 +U 1 1 58023F36 +P 1260 5130 +F 0 "C110" H 1320 5145 60 0000 L BNN +F 1 "0.1uF" H 1320 4920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 1320 4920 60 0001 C CNN +F 3 "" H 1320 4920 60 0000 C CNN + 1 1260 5130 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R46 +U 1 1 58023F35 +P 3360 4700 +F 0 "R46" V 3270 4655 60 0000 R TNN +F 1 "4.7k" V 3340 4590 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3340 4590 60 0001 C CNN +F 3 "" H 3340 4590 60 0000 C CNN + 1 3360 4700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R47 +U 1 1 58023F34 +P 2960 7630 +F 0 "R47" V 3050 7675 60 0000 L BNN +F 1 "4.7k" V 3040 7710 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3040 7710 60 0001 C CNN +F 3 "" H 3040 7710 60 0000 C CNN + 1 2960 7630 + 0 1 1 0 +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_16.sch b/KiCAD/rev02_16.sch new file mode 100644 index 0000000..10ad9bb --- /dev/null +++ b/KiCAD/rev02_16.sch @@ -0,0 +1,214 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 18 27 +Title "rev02_16" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 1500 4100 0 60 ~ 12 +*) Middle Right Bank +Text Notes 4800 4000 0 60 ~ 12 +*) Upper Left Bank +Text Notes 2400 4800 0 60 ~ 12 +*) Completely unused banks\nstill must be powered +Text Notes 5900 4700 0 60 ~ 12 +*) Completely unused banks\nstill must be powered +Text Notes 8600 10230 0 84 ~ 12 +FPGA unused banks +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_31 +U 1 1 58023F33 +P 2300 4300 +F 0 "VCCO_3V3_31" H 2300 4300 20 0000 C CNN +F 1 "+VCCO_3V3" H 2300 4230 30 0000 C CNN +F 2 "" H 2300 4300 70 0000 C CNN +F 3 "" H 2300 4300 70 0000 C CNN + 1 2300 4300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_32 +U 1 1 58023F32 +P 5800 4200 +F 0 "VCCO_3V3_32" H 5800 4200 20 0000 C CNN +F 1 "+VCCO_3V3" H 5800 4130 30 0000 C CNN +F 2 "" H 5800 4200 70 0000 C CNN +F 3 "" H 5800 4200 70 0000 C CNN + 1 5800 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 4500 2100 4500 +Wire Wire Line + 2300 4500 2300 4600 +Wire Wire Line + 2300 4600 2300 4700 +Wire Wire Line + 2300 4700 2300 4800 +Wire Wire Line + 2300 4800 2100 4800 +Wire Wire Line + 2300 4700 2100 4700 +Wire Wire Line + 2300 4600 2100 4600 +Wire Wire Line + 2300 4300 2300 4500 +Wire Wire Line + 2300 5000 2100 5000 +Wire Wire Line + 2300 4900 2300 5000 +Wire Wire Line + 2300 4800 2300 4900 +Wire Wire Line + 2300 4900 2100 4900 +Wire Wire Line + 5800 4400 5600 4400 +Wire Wire Line + 5800 4400 5800 4500 +Wire Wire Line + 5800 4500 5800 4600 +Wire Wire Line + 5800 4600 5800 4700 +Wire Wire Line + 5800 4700 5600 4700 +Wire Wire Line + 5800 4600 5600 4600 +Wire Wire Line + 5800 4500 5600 4500 +Wire Wire Line + 5800 4200 5800 4400 +Wire Wire Line + 5800 4900 5600 4900 +Wire Wire Line + 5800 4800 5800 4900 +Wire Wire Line + 5800 4700 5800 4800 +Wire Wire Line + 5800 4800 5600 4800 +$Comp +L Cryptech_Alpha:XC7A200TFBG484_4 U13_7 +U 1 1 58023F31 +P 1900 7200 +F 0 "U13_7" H 1490 4190 60 0000 L BNN + 1 1900 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1490 4190 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_7 U13_8 +U 1 1 58023F30 +P 5400 7100 +F 0 "U13_8" H 4990 4090 60 0000 L BNN + 1 5400 7100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 4990 4090 60 0001 C CNN +$EndComp +NoConn ~ 2100 5100 +NoConn ~ 2100 5200 +NoConn ~ 2100 5300 +NoConn ~ 2100 5400 +NoConn ~ 2100 5500 +NoConn ~ 2100 5600 +NoConn ~ 2100 5700 +NoConn ~ 2100 5800 +NoConn ~ 2100 5900 +NoConn ~ 2100 6000 +NoConn ~ 2100 6100 +NoConn ~ 2100 6200 +NoConn ~ 2100 6300 +NoConn ~ 2100 6400 +NoConn ~ 2100 6500 +NoConn ~ 2100 6700 +NoConn ~ 2100 6600 +NoConn ~ 2100 6800 +NoConn ~ 2100 6900 +NoConn ~ 2100 7000 +NoConn ~ 2100 7100 +NoConn ~ 2100 7300 +NoConn ~ 2100 7200 +NoConn ~ 2100 7400 +NoConn ~ 2100 7500 +NoConn ~ 2100 7600 +NoConn ~ 2100 7700 +NoConn ~ 2100 7800 +NoConn ~ 2100 7900 +NoConn ~ 2100 8000 +NoConn ~ 2100 8100 +NoConn ~ 2100 8200 +NoConn ~ 2100 8300 +NoConn ~ 5600 5000 +NoConn ~ 5600 5100 +NoConn ~ 5600 5200 +NoConn ~ 5600 5300 +NoConn ~ 5600 5400 +NoConn ~ 5600 5500 +NoConn ~ 5600 5600 +NoConn ~ 5600 5700 +NoConn ~ 5600 5800 +NoConn ~ 5600 5900 +NoConn ~ 5600 6000 +NoConn ~ 5600 6100 +NoConn ~ 5600 6200 +NoConn ~ 5600 6300 +NoConn ~ 5600 6400 +NoConn ~ 5600 6500 +NoConn ~ 5600 6600 +NoConn ~ 5600 6700 +NoConn ~ 5600 6800 +NoConn ~ 5600 6900 +NoConn ~ 5600 7000 +NoConn ~ 5600 7100 +NoConn ~ 5600 7200 +NoConn ~ 5600 7400 +NoConn ~ 5600 7300 +NoConn ~ 5600 7500 +NoConn ~ 5600 7700 +NoConn ~ 5600 7600 +NoConn ~ 5600 7900 +NoConn ~ 5600 7800 +NoConn ~ 5600 8000 +NoConn ~ 5600 8100 +NoConn ~ 5600 8200 +NoConn ~ 5600 8300 +NoConn ~ 5600 8400 +NoConn ~ 5600 8500 +NoConn ~ 5600 8600 +NoConn ~ 5600 8800 +NoConn ~ 5600 8700 +NoConn ~ 5600 8900 +NoConn ~ 5600 9000 +NoConn ~ 5600 9100 +NoConn ~ 5600 9200 +NoConn ~ 5600 9300 +NoConn ~ 5600 9400 +NoConn ~ 5600 9500 +NoConn ~ 5600 9600 +NoConn ~ 5600 9800 +NoConn ~ 5600 9900 +NoConn ~ 5600 9700 +NoConn ~ 2100 8400 +NoConn ~ 2100 8500 +NoConn ~ 2100 8600 +NoConn ~ 2100 8700 +NoConn ~ 2100 8800 +NoConn ~ 2100 8900 +NoConn ~ 2100 9000 +NoConn ~ 2100 9300 +NoConn ~ 2100 9100 +NoConn ~ 2100 9200 +NoConn ~ 2100 9400 +NoConn ~ 2100 9500 +NoConn ~ 2100 9600 +NoConn ~ 2100 9700 +NoConn ~ 2100 9800 +NoConn ~ 2100 9900 +NoConn ~ 2100 10000 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_17.sch b/KiCAD/rev02_17.sch new file mode 100644 index 0000000..f61c061 --- /dev/null +++ b/KiCAD/rev02_17.sch @@ -0,0 +1,372 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 19 27 +Title "rev02_17" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6050 4500 0 60 ~ 12 +*) Bottom Bank +Text Notes 1000 4100 0 60 ~ 12 +*) Lower Left Bank +Text Notes 8480 5140 0 60 ~ 12 +FMC_A[...] signals can be swapped +Text Notes 8140 7850 0 60 ~ 12 +<-- FMC_CLK signal _MUST_ go\ninto either W11 or V13 (i.e. into\none of the two positive (master)\nsides of the two available\nMRCC differential pairs) +Text Notes 3260 5160 0 60 ~ 12 +FMC_D[...] signals can be swapped +Text Notes 2900 8700 0 60 ~ 12 +<-- FMC_* control signals\n can be swapped +Text Notes 8580 10230 0 84 ~ 12 +FPGA FMC interface +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_33 +U 1 1 58023F2F +P 2000 4400 +F 0 "VCCO_3V3_33" H 2000 4400 20 0000 C CNN +F 1 "+VCCO_3V3" H 2000 4330 30 0000 C CNN +F 2 "" H 2000 4400 70 0000 C CNN +F 3 "" H 2000 4400 70 0000 C CNN + 1 2000 4400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_34 +U 1 1 58023F2E +P 7000 4700 +F 0 "VCCO_3V3_34" H 7000 4700 20 0000 C CNN +F 1 "+VCCO_3V3" H 7000 4630 30 0000 C CNN +F 2 "" H 7000 4700 70 0000 C CNN +F 3 "" H 7000 4700 70 0000 C CNN + 1 7000 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 5100 1800 5100 +Wire Wire Line + 2000 5000 2000 5100 +Wire Wire Line + 2000 4900 2000 5000 +Wire Wire Line + 2000 4800 2000 4900 +Wire Wire Line + 2000 4700 2000 4800 +Wire Wire Line + 2000 4600 2000 4700 +Wire Wire Line + 2000 4600 1800 4600 +Wire Wire Line + 2000 4700 1800 4700 +Wire Wire Line + 2000 4800 1800 4800 +Wire Wire Line + 2000 4900 1800 4900 +Wire Wire Line + 2000 5000 1800 5000 +Wire Wire Line + 2000 4400 2000 4600 +Wire Wire Line + 7000 5000 6750 5000 +Wire Wire Line + 7000 4700 7000 5000 +Wire Wire Line + 7000 5100 6750 5100 +Wire Wire Line + 7000 5000 7000 5100 +Wire Wire Line + 7000 5200 6750 5200 +Wire Wire Line + 7000 5100 7000 5200 +Wire Wire Line + 7000 5300 6750 5300 +Wire Wire Line + 7000 5200 7000 5300 +Wire Wire Line + 7000 5400 6750 5400 +Wire Wire Line + 7000 5300 7000 5400 +Wire Wire Line + 7890 7800 6750 7800 +Text GLabel 7890 7800 2 48 Output ~ 0 +FMC_CLK +Wire Wire Line + 2950 5200 1800 5200 +Wire Wire Line + 2950 5300 1800 5300 +Wire Wire Line + 2950 5400 1800 5400 +Text GLabel 2950 5400 2 48 BiDi ~ 0 +FMC_D2 +Wire Wire Line + 2950 5500 1800 5500 +Text GLabel 2950 5500 2 48 BiDi ~ 0 +FMC_D3 +Wire Wire Line + 2950 5600 1800 5600 +Text GLabel 7900 6800 2 48 BiDi ~ 0 +FMC_D4 +Text GLabel 7900 7300 2 48 BiDi ~ 0 +FMC_D5 +Text GLabel 7900 7600 2 48 BiDi ~ 0 +FMC_D6 +Wire Wire Line + 2950 5900 1800 5900 +Text GLabel 7900 7700 2 48 BiDi ~ 0 +FMC_D7 +Wire Wire Line + 2950 6100 1800 6100 +Wire Wire Line + 2950 6200 1800 6200 +Wire Wire Line + 2950 6300 1800 6300 +Wire Wire Line + 2950 6400 1800 6400 +Wire Wire Line + 2950 6500 1800 6500 +Text GLabel 2950 6500 2 48 BiDi ~ 0 +FMC_D13 +Wire Wire Line + 2950 6600 1800 6600 +Text GLabel 2950 6600 2 48 BiDi ~ 0 +FMC_D14 +Wire Wire Line + 2950 6700 1800 6700 +Text GLabel 2950 6800 2 48 BiDi ~ 0 +FMC_D15 +Wire Wire Line + 2950 6800 1800 6800 +Text GLabel 2950 6700 2 48 BiDi ~ 0 +FMC_D16 +Wire Wire Line + 2950 6900 1800 6900 +Text GLabel 2950 6900 2 48 BiDi ~ 0 +FMC_D17 +Wire Wire Line + 2950 7000 1800 7000 +Text GLabel 2950 7000 2 48 BiDi ~ 0 +FMC_D18 +Wire Wire Line + 2950 7100 1800 7100 +Text GLabel 2950 7100 2 48 BiDi ~ 0 +FMC_D19 +Wire Wire Line + 2950 7200 1800 7200 +Text GLabel 2950 7200 2 48 BiDi ~ 0 +FMC_D20 +Wire Wire Line + 2950 7300 1800 7300 +Text GLabel 2950 7300 2 48 BiDi ~ 0 +FMC_D21 +Wire Wire Line + 2950 7400 1800 7400 +Text GLabel 2950 7400 2 48 BiDi ~ 0 +FMC_D22 +Wire Wire Line + 2950 7500 1800 7500 +Text GLabel 2950 7500 2 48 BiDi ~ 0 +FMC_D23 +Wire Wire Line + 2950 7700 1800 7700 +Text GLabel 2950 7700 2 48 BiDi ~ 0 +FMC_D25 +Text GLabel 2950 8400 2 48 Input ~ 0 +FMC_NE1 +Wire Wire Line + 2960 8700 1800 8700 +Text GLabel 2960 8700 2 48 Output ~ 0 +FMC_NWAIT +Wire Wire Line + 2960 8800 1800 8800 +Text GLabel 2960 8800 2 48 Input ~ 0 +FMC_NWE +Wire Wire Line + 7900 5500 6750 5500 +Text GLabel 7900 5500 2 48 Input ~ 0 +FMC_A0 +Wire Wire Line + 7900 5600 6750 5600 +Text GLabel 7900 5800 2 48 Input ~ 0 +FMC_A1 +Wire Wire Line + 7900 5700 6750 5700 +Text GLabel 7900 5700 2 48 Input ~ 0 +FMC_A2 +Wire Wire Line + 7900 5800 6750 5800 +Text GLabel 7900 5600 2 48 Input ~ 0 +FMC_A3 +Wire Wire Line + 7900 5900 6750 5900 +Text GLabel 7900 5900 2 48 Input ~ 0 +FMC_A4 +Wire Wire Line + 7900 6000 6750 6000 +Text GLabel 7900 6000 2 48 Input ~ 0 +FMC_A5 +Wire Wire Line + 7900 6100 6750 6100 +Text GLabel 7900 6100 2 48 Input ~ 0 +FMC_A6 +Wire Wire Line + 7900 6200 6750 6200 +Text GLabel 7900 6200 2 48 Input ~ 0 +FMC_A7 +Wire Wire Line + 7900 6300 6750 6300 +Text GLabel 7900 6300 2 48 Input ~ 0 +FMC_A8 +Wire Wire Line + 7900 6400 6750 6400 +Text GLabel 7900 6400 2 48 Input ~ 0 +FMC_A9 +Wire Wire Line + 7900 6500 6750 6500 +Text GLabel 7900 6500 2 48 Input ~ 0 +FMC_A10 +Wire Wire Line + 7900 6600 6750 6600 +Text GLabel 7900 6700 2 48 Input ~ 0 +FMC_A11 +Wire Wire Line + 7900 6700 6750 6700 +Text GLabel 7900 7100 2 48 Input ~ 0 +FMC_A12 +Wire Wire Line + 7900 6800 6750 6800 +Text GLabel 2950 5600 2 48 Input ~ 0 +FMC_A13 +Wire Wire Line + 7900 6900 6750 6900 +Text GLabel 7900 6900 2 48 Input ~ 0 +FMC_A14 +Wire Wire Line + 7900 7000 6750 7000 +Text GLabel 2970 9600 2 48 Input ~ 0 +FMC_A15 +Wire Wire Line + 7900 7100 6750 7100 +Text GLabel 7900 7000 2 48 Input ~ 0 +FMC_A16 +Text GLabel 2970 9500 2 48 Input ~ 0 +FMC_A17 +Wire Wire Line + 7900 7300 6750 7300 +Text GLabel 2970 9800 2 48 Input ~ 0 +FMC_A18 +Wire Wire Line + 7900 7500 6750 7500 +Wire Wire Line + 7900 7600 6750 7600 +Wire Wire Line + 7900 7700 6750 7700 +Wire Wire Line + 7900 7900 6750 7900 +Wire Wire Line + 7900 8000 6750 8000 +Wire Wire Line + 7900 8100 6750 8100 +Wire Bus Line + 9070 5000 8470 5000 +Text Label 8470 5000 0 60 ~ +FMC_A[0..25] +Wire Bus Line + 3860 5000 3260 5000 +Text Label 3260 5000 0 60 ~ +FMC_D[0..31] +Wire Wire Line + 2970 9600 1800 9600 +Wire Wire Line + 2970 9200 1800 9200 +Text GLabel 2970 9100 2 48 BiDi ~ 0 +FMC_D0 +Wire Wire Line + 2970 9100 1800 9100 +Text GLabel 2970 9200 2 48 BiDi ~ 0 +FMC_D1 +Wire Wire Line + 2970 9800 1800 9800 +Wire Wire Line + 2970 9500 1800 9500 +Text GLabel 7900 7500 2 48 BiDi ~ 0 +FMC_D24 +Text GLabel 7900 7900 2 48 BiDi ~ 0 +FMC_D26 +Text GLabel 7900 6600 2 48 BiDi ~ 0 +FMC_D27 +Text GLabel 7910 8700 2 48 Input ~ 0 +FMC_NOE +Wire Wire Line + 7910 8700 6750 8700 +Wire Wire Line + 2950 8400 1800 8400 +Text GLabel 2950 5900 2 48 Output ~ 0 +MKM_FPGA_CS_N +Text GLabel 2950 6400 2 48 Output ~ 0 +MKM_FPGA_SCK +Text GLabel 2950 6100 2 48 Output ~ 0 +MKM_FPGA_MOSI +Text GLabel 2950 6200 2 48 Input ~ 0 +MKM_FPGA_MISO +Text GLabel 2950 6300 2 48 Output ~ 0 +FPGA_GPIO_LED_0 +Text GLabel 2950 5300 2 48 Output ~ 0 +FPGA_GPIO_LED_1 +$Comp +L Cryptech_Alpha:XC7A200TFBG484_2 U13_9 +U 1 1 58023F2D +P 6550 6900 +F 0 "U13_9" H 6140 4690 60 0000 L BNN + 1 6550 6900 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 6140 4690 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_6 U13_10 +U 1 1 58023F2C +P 1600 7300 +F 0 "U13_10" H 1190 4290 60 0000 L BNN + 1 1600 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1190 4290 60 0001 C CNN +$EndComp +NoConn ~ 1800 5700 +NoConn ~ 1800 5800 +NoConn ~ 1800 6000 +NoConn ~ 1800 7600 +NoConn ~ 1800 7800 +NoConn ~ 1800 7900 +NoConn ~ 1800 8000 +NoConn ~ 1800 8100 +NoConn ~ 1800 8200 +NoConn ~ 1800 8300 +NoConn ~ 1800 8500 +NoConn ~ 1800 8600 +NoConn ~ 1800 8900 +NoConn ~ 1800 9000 +NoConn ~ 1800 9400 +NoConn ~ 1800 9300 +NoConn ~ 1800 9700 +NoConn ~ 1800 9900 +NoConn ~ 1800 10000 +NoConn ~ 1800 10100 +NoConn ~ 6750 8200 +NoConn ~ 6750 8300 +NoConn ~ 6750 8400 +NoConn ~ 6750 8500 +NoConn ~ 6750 8600 +NoConn ~ 6750 8800 +NoConn ~ 6750 8900 +NoConn ~ 6750 7400 +NoConn ~ 6750 7200 +NoConn ~ 2950 5200 +NoConn ~ 7900 8000 +NoConn ~ 7900 8100 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_18.sch b/KiCAD/rev02_18.sch new file mode 100644 index 0000000..10c7020 --- /dev/null +++ b/KiCAD/rev02_18.sch @@ -0,0 +1,815 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 20 27 +Title "rev02_18" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 4700 4100 0 60 ~ 12 +*) FPGA Power Subsystem -- AUX and I/O +Text Notes 7500 5100 0 60 ~ 12 +*) VCCAUX = 0.75V x (1 + 205 / 147) = 1.796V\n*) VCCO = 0.75V x (1 + 205 / 59) = 3.356\n*) Minimal load current is 2 mA:\n1.8V / 470 Ohm = ~~4mA\n3.3V / 470 Ohm = ~~7mA\n*) Light-load mode is enabled +Text Notes 6700 8500 0 60 ~ 12 +This is the 3V3 rail that powers\nboth the FPGA and the ARM as well\nas various other components. +Text Notes 8450 10220 0 66 ~ 12 +FPGA voltage regulators +Text Notes 1160 5190 0 60 ~ 12 +C113 +Text Notes 1160 5390 0 60 ~ 12 +22~uF +Text Notes 1710 6350 0 60 ~ 12 +R53 +Text Notes 1690 5170 0 60 ~ 12 +R52 +Text Notes 4040 5090 0 60 ~ 12 +R56 +Text Notes 4400 5700 0 60 ~ 12 +R57 +Text Notes 5630 5560 0 60 ~ 12 +R60 +Text Notes 1160 8390 0 60 ~ 12 +C114 +Text Notes 1160 8590 0 60 ~ 12 +22~uF +Text Notes 1730 9530 0 60 ~ 12 +R55 +Text Notes 1660 8390 0 60 ~ 12 +R54 +Text Notes 4040 8270 0 60 ~ 12 +R58 +Text Notes 4070 8880 0 60 ~ 12 +R59 +Text Notes 5600 8690 0 60 ~ 12 +R61 +Text Notes 2160 6390 0 60 ~ 12 +C115 +Text Notes 2160 6590 0 60 ~ 12 +0.047~uF +Text Notes 2160 9590 0 60 ~ 12 +C116 +Text Notes 2160 9790 0 60 ~ 12 +0.047~uF +Text Notes 4660 8190 0 60 ~ 12 +C118 +Text Notes 4660 8390 0 60 ~ 12 +27pF +Text Notes 4660 4990 0 60 ~ 12 +C117 +Text Notes 4660 5190 0 60 ~ 12 +27pF +Text Notes 5060 5490 0 60 ~ 12 +C119 +Text Notes 5060 5690 0 60 ~ 12 +47uF +Text Notes 5060 8690 0 60 ~ 12 +C120 +Text Notes 5060 8890 0 60 ~ 12 +47uF +$Comp +L power:GND GND_109 +U 1 1 58023F2B +P 2800 6700 +F 0 "GND_109" H 2800 6700 20 0000 C CNN +F 1 "+GND" H 2800 6630 30 0000 C CNN +F 2 "" H 2800 6700 70 0000 C CNN +F 3 "" H 2800 6700 70 0000 C CNN + 1 2800 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_110 +U 1 1 58023F2A +P 3300 6700 +F 0 "GND_110" H 3300 6700 20 0000 C CNN +F 1 "+GND" H 3300 6630 30 0000 C CNN +F 2 "" H 3300 6700 70 0000 C CNN +F 3 "" H 3300 6700 70 0000 C CNN + 1 3300 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_111 +U 1 1 58023F29 +P 2100 6700 +F 0 "GND_111" H 2100 6700 20 0000 C CNN +F 1 "+GND" H 2100 6630 30 0000 C CNN +F 2 "" H 2100 6700 70 0000 C CNN +F 3 "" H 2100 6700 70 0000 C CNN + 1 2100 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_112 +U 1 1 58023F28 +P 1100 5600 +F 0 "GND_112" H 1100 5600 20 0000 C CNN +F 1 "+GND" H 1100 5530 30 0000 C CNN +F 2 "" H 1100 5600 70 0000 C CNN +F 3 "" H 1100 5600 70 0000 C CNN + 1 1100 5600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_113 +U 1 1 58023F27 +P 1600 6700 +F 0 "GND_113" H 1600 6700 20 0000 C CNN +F 1 "+GND" H 1600 6630 30 0000 C CNN +F 2 "" H 1600 6700 70 0000 C CNN +F 3 "" H 1600 6700 70 0000 C CNN + 1 1600 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_114 +U 1 1 58023F26 +P 4300 6000 +F 0 "GND_114" H 4300 6000 20 0000 C CNN +F 1 "+GND" H 4300 5930 30 0000 C CNN +F 2 "" H 4300 6000 70 0000 C CNN +F 3 "" H 4300 6000 70 0000 C CNN + 1 4300 6000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_115 +U 1 1 58023F25 +P 5000 6000 +F 0 "GND_115" H 5000 6000 20 0000 C CNN +F 1 "+GND" H 5000 5930 30 0000 C CNN +F 2 "" H 5000 6000 70 0000 C CNN +F 3 "" H 5000 6000 70 0000 C CNN + 1 5000 6000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_116 +U 1 1 58023F24 +P 5500 6000 +F 0 "GND_116" H 5500 6000 20 0000 C CNN +F 1 "+GND" H 5500 5930 30 0000 C CNN +F 2 "" H 5500 6000 70 0000 C CNN +F 3 "" H 5500 6000 70 0000 C CNN + 1 5500 6000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_117 +U 1 1 58023F23 +P 2800 9900 +F 0 "GND_117" H 2800 9900 20 0000 C CNN +F 1 "+GND" H 2800 9830 30 0000 C CNN +F 2 "" H 2800 9900 70 0000 C CNN +F 3 "" H 2800 9900 70 0000 C CNN + 1 2800 9900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_118 +U 1 1 58023F22 +P 3300 9900 +F 0 "GND_118" H 3300 9900 20 0000 C CNN +F 1 "+GND" H 3300 9830 30 0000 C CNN +F 2 "" H 3300 9900 70 0000 C CNN +F 3 "" H 3300 9900 70 0000 C CNN + 1 3300 9900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_119 +U 1 1 58023F21 +P 2100 9900 +F 0 "GND_119" H 2100 9900 20 0000 C CNN +F 1 "+GND" H 2100 9830 30 0000 C CNN +F 2 "" H 2100 9900 70 0000 C CNN +F 3 "" H 2100 9900 70 0000 C CNN + 1 2100 9900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_120 +U 1 1 58023F20 +P 1100 8800 +F 0 "GND_120" H 1100 8800 20 0000 C CNN +F 1 "+GND" H 1100 8730 30 0000 C CNN +F 2 "" H 1100 8800 70 0000 C CNN +F 3 "" H 1100 8800 70 0000 C CNN + 1 1100 8800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_121 +U 1 1 58023F1F +P 1600 9900 +F 0 "GND_121" H 1600 9900 20 0000 C CNN +F 1 "+GND" H 1600 9830 30 0000 C CNN +F 2 "" H 1600 9900 70 0000 C CNN +F 3 "" H 1600 9900 70 0000 C CNN + 1 1600 9900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_122 +U 1 1 58023F1E +P 4300 9200 +F 0 "GND_122" H 4300 9200 20 0000 C CNN +F 1 "+GND" H 4300 9130 30 0000 C CNN +F 2 "" H 4300 9200 70 0000 C CNN +F 3 "" H 4300 9200 70 0000 C CNN + 1 4300 9200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_123 +U 1 1 58023F1D +P 5000 9200 +F 0 "GND_123" H 5000 9200 20 0000 C CNN +F 1 "+GND" H 5000 9130 30 0000 C CNN +F 2 "" H 5000 9200 70 0000 C CNN +F 3 "" H 5000 9200 70 0000 C CNN + 1 5000 9200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_124 +U 1 1 58023F1C +P 5500 9200 +F 0 "GND_124" H 5500 9200 20 0000 C CNN +F 1 "+GND" H 5500 9130 30 0000 C CNN +F 2 "" H 5500 9200 70 0000 C CNN +F 3 "" H 5500 9200 70 0000 C CNN + 1 5500 9200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0 +U 1 1 58023F1B +P 1100 4600 +F 0 "VCC_5V0" H 1100 4600 20 0000 C CNN +F 1 "+VCC_5V0" H 1100 4530 30 0000 C CNN +F 2 "" H 1100 4600 70 0000 C CNN +F 3 "" H 1100 4600 70 0000 C CNN + 1 1100 4600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_2 +U 1 1 58023F1A +P 1100 7800 +F 0 "VCC_5V0_2" H 1100 7800 20 0000 C CNN +F 1 "+VCC_5V0" H 1100 7730 30 0000 C CNN +F 2 "" H 1100 7800 70 0000 C CNN +F 3 "" H 1100 7800 70 0000 C CNN + 1 1100 7800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 6600 2800 6700 +Wire Wire Line + 3300 6600 3300 6700 +Wire Wire Line + 2100 6600 2100 6700 +Wire Wire Line + 1100 5400 1100 5600 +Wire Wire Line + 1600 6600 1600 6700 +Wire Wire Line + 4300 5900 4300 6000 +Wire Wire Line + 5000 5700 5000 6000 +Wire Wire Line + 5500 5800 5500 6000 +Wire Wire Line + 2800 9800 2800 9900 +Wire Wire Line + 3300 9800 3300 9900 +Wire Wire Line + 2100 9800 2100 9900 +Wire Wire Line + 1100 8600 1100 8800 +Wire Wire Line + 1600 9800 1600 9900 +Wire Wire Line + 4300 9100 4300 9200 +Wire Wire Line + 5000 8900 5000 9200 +Wire Wire Line + 5500 9000 5500 9200 +Wire Wire Line + 7000 4800 6000 4800 +Text Label 7000 4800 2 48 ~ 0 +FPGA_VCCAUX_1V8 +Wire Wire Line + 7000 8000 6000 8000 +Text Label 7000 8000 0 48 ~ 0 +VCCO_3V3 +Wire Wire Line + 2100 6200 2100 6300 +Wire Wire Line + 2300 6200 2100 6200 +Wire Wire Line + 2300 4800 2100 4800 +Wire Wire Line + 2100 4800 1600 4800 +Wire Wire Line + 1600 4800 1100 4800 +Wire Wire Line + 1100 4600 1100 4800 +Wire Wire Line + 2300 5000 2100 5000 +Wire Wire Line + 2100 4800 2100 5000 +Wire Wire Line + 1100 4800 1100 5100 +Wire Wire Line + 1600 4800 1600 5000 +Connection ~ 2100 4800 +Connection ~ 1100 4800 +Connection ~ 1600 4800 +Wire Wire Line + 2300 8000 2100 8000 +Wire Wire Line + 2100 8000 1600 8000 +Wire Wire Line + 1600 8000 1100 8000 +Wire Wire Line + 1100 7800 1100 8000 +Wire Wire Line + 2300 8200 2100 8200 +Wire Wire Line + 2100 8000 2100 8200 +Wire Wire Line + 1100 8000 1100 8300 +Wire Wire Line + 1600 8000 1600 8200 +Connection ~ 2100 8000 +Connection ~ 1100 8000 +Connection ~ 1600 8000 +Wire Wire Line + 2300 5200 1900 5200 +Wire Wire Line + 1900 4150 1900 5200 +Text GLabel 1900 4150 0 48 Input ~ 0 +PWR_ENA_VCCAUX +Wire Wire Line + 1600 5800 1600 6200 +Wire Wire Line + 2300 5800 1600 5800 +Wire Wire Line + 2300 5600 1600 5600 +Wire Wire Line + 1600 5400 1600 5600 +Wire Wire Line + 4300 4800 3900 4800 +Wire Wire Line + 4300 4800 4300 4900 +Wire Wire Line + 4600 4800 4600 4900 +Wire Wire Line + 4600 4800 4300 4800 +Wire Wire Line + 5000 4800 5000 5400 +Wire Wire Line + 5000 4800 4600 4800 +Wire Wire Line + 5500 4800 5500 5400 +Wire Wire Line + 5500 4800 5000 4800 +Wire Wire Line + 5600 4800 5500 4800 +Connection ~ 4300 4800 +Connection ~ 4600 4800 +Connection ~ 5000 4800 +Connection ~ 5500 4800 +Wire Wire Line + 4300 5300 4300 5400 +Wire Wire Line + 4300 5400 3900 5400 +Wire Wire Line + 4600 5200 4600 5400 +Wire Wire Line + 4600 5400 4300 5400 +Wire Wire Line + 4300 5400 4300 5500 +Connection ~ 4300 5400 +Wire Wire Line + 2100 9400 2100 9500 +Wire Wire Line + 2300 9400 2100 9400 +Wire Wire Line + 1600 9000 1600 9400 +Wire Wire Line + 2300 9000 1600 9000 +Wire Wire Line + 2300 8800 1600 8800 +Wire Wire Line + 1600 8600 1600 8800 +Wire Wire Line + 4010 8000 3900 8000 +Wire Wire Line + 4300 8000 4010 8000 +Wire Wire Line + 4300 8000 4300 8100 +Wire Wire Line + 4600 8000 4600 8100 +Wire Wire Line + 4600 8000 4300 8000 +Wire Wire Line + 5000 8000 5000 8600 +Wire Wire Line + 5000 8000 4600 8000 +Wire Wire Line + 5500 8000 5500 8600 +Wire Wire Line + 5500 8000 5000 8000 +Wire Wire Line + 5600 8000 5500 8000 +Connection ~ 4300 8000 +Connection ~ 4600 8000 +Connection ~ 5000 8000 +Connection ~ 5500 8000 +Wire Wire Line + 4300 8500 4300 8600 +Wire Wire Line + 4300 8600 3900 8600 +Wire Wire Line + 4600 8400 4600 8600 +Wire Wire Line + 4600 8600 4300 8600 +Wire Wire Line + 4300 8600 4300 8700 +Connection ~ 4300 8600 +Wire Wire Line + 2300 8400 1900 8400 +Wire Wire Line + 1900 7500 1900 8400 +Wire Wire Line + 1900 7500 1800 7500 +Text GLabel 1400 7500 0 48 Input ~ 0 +PWR_ENA_VCCO +Wire Wire Line + 4000 6200 3900 6200 +Wire Wire Line + 4000 6200 4000 6500 +Text GLabel 4000 6500 2 48 Output ~ 0 +POK_VCCAUX +Wire Wire Line + 4000 9400 3900 9400 +Wire Wire Line + 4000 9400 4000 9700 +Text GLabel 4000 9700 2 48 Output ~ 0 +POK_VCCO +Text Notes 2700 4440 0 60 ~ 12 +U14 +Text Notes 3090 4420 0 60 ~ 12 +EN6347QI +Wire Wire Line + 2300 4700 2300 4600 +Wire Wire Line + 2300 4800 2300 4700 +Wire Wire Line + 3900 4700 3900 4600 +Wire Wire Line + 3900 4800 3900 4700 +Wire Wire Line + 3900 4900 3900 4800 +Wire Wire Line + 3900 5000 3900 4900 +Wire Wire Line + 3900 5100 3900 5000 +Wire Wire Line + 3900 5200 3900 5100 +Text Notes 2700 7640 0 60 ~ 12 +U14 +Text Notes 3090 7630 0 60 ~ 12 +EN6347QI +Wire Wire Line + 2100 7800 2300 7800 +Wire Wire Line + 2100 7900 2100 7800 +Wire Wire Line + 2100 8000 2100 7900 +Wire Wire Line + 2100 7900 2300 7900 +Wire Wire Line + 4010 7800 3900 7800 +Wire Wire Line + 4010 7900 4010 7800 +Wire Wire Line + 4010 8000 4010 7900 +Wire Wire Line + 4010 7900 3900 7900 +Wire Wire Line + 4010 8100 3900 8100 +Wire Wire Line + 4010 8000 4010 8100 +Wire Wire Line + 4010 8200 3900 8200 +Wire Wire Line + 4010 8100 4010 8200 +Wire Wire Line + 4010 8300 3900 8300 +Wire Wire Line + 4010 8200 4010 8300 +Wire Wire Line + 4010 8400 3900 8400 +Wire Wire Line + 4010 8300 4010 8400 +Wire Wire Line + 1400 7500 1800 7500 +Connection ~ 2100 7900 +Connection ~ 2300 4800 +Connection ~ 2300 4700 +Connection ~ 3900 5100 +Connection ~ 3900 5000 +Connection ~ 3900 4900 +Connection ~ 3900 4800 +Connection ~ 3900 4700 +Connection ~ 4010 8300 +Connection ~ 4010 8200 +Connection ~ 4010 8100 +Connection ~ 4010 8000 +Connection ~ 4010 7900 +$Comp +L Cryptech_Alpha:C-EUC1210 C113 +U 1 1 58023F19 +P 1100 5200 +F 0 "C113" H 1180 5010 60 0000 L BNN + 1 1100 5200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1180 5010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R54 +U 1 1 58023F18 +P 1600 8400 +F 0 "R54" V 1510 8355 60 0000 R TNN +F 1 "4.7k" V 1490 8350 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1490 8350 60 0001 C CNN +F 3 "" H 1490 8350 60 0000 C CNN + 1 1600 8400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R58 +U 1 1 58023F17 +P 4300 8300 +F 0 "R58" V 4210 8255 60 0000 R TNN +F 1 "205k" V 4250 8560 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4250 8560 60 0001 C CNN +F 3 "" H 4250 8560 60 0000 C CNN + 1 4300 8300 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R59 +U 1 1 58023F16 +P 4300 8900 +F 0 "R59" V 4210 8855 60 0000 R TNN +F 1 "59k" V 4240 9130 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4240 9130 60 0001 C CNN +F 3 "" H 4240 9130 60 0000 C CNN + 1 4300 8900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R61 +U 1 1 58023F15 +P 5500 8800 +F 0 "R61" V 5410 8755 60 0000 R TNN +F 1 "470" V 5520 8700 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5520 8700 60 0001 C CNN +F 3 "" H 5520 8700 60 0000 C CNN + 1 5500 8800 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:BLM31PG330SN1_1206 FB6 +U 1 1 58023F14 +P 5800 8100 +F 0 "FB6" H 5650 8300 60 0000 L BNN +F 1 "BLM31PG330SN1" H 5630 8010 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:L_1206" H 5630 8010 60 0001 C CNN +F 3 "" H 5630 8010 60 0000 C CNN + 1 5800 8100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C115 +U 1 1 58023F13 +P 2100 6400 +F 0 "C115" H 2180 6210 60 0000 L BNN + 1 2100 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2180 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C116 +U 1 1 58023F12 +P 2100 9600 +F 0 "C116" H 2180 9410 60 0000 L BNN + 1 2100 9600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2180 9410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C118 +U 1 1 58023F11 +P 4600 8200 +F 0 "C118" H 4680 8010 60 0000 L BNN + 1 4600 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C117 +U 1 1 58023F10 +P 4600 5000 +F 0 "C117" H 4680 4810 60 0000 L BNN + 1 4600 5000 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 4810 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C119 +U 1 1 58023F0F +P 5000 5500 +F 0 "C119" H 5080 5310 60 0000 L BNN + 1 5000 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 5080 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R53 +U 1 1 58023F0E +P 1600 6400 +F 0 "R53" V 1510 6355 60 0000 R TNN +F 1 "62k" V 1550 6290 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1550 6290 60 0001 C CNN +F 3 "" H 1550 6290 60 0000 C CNN + 1 1600 6400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C120 +U 1 1 58023F0D +P 5000 8700 +F 0 "C120" H 5080 8510 60 0000 L BNN + 1 5000 8700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 5080 8510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:EN6347QI U14 +U 1 1 58023F0C +P 3100 5500 +F 0 "U14" H 2740 6590 60 0000 L BNN + 1 3100 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:QFN38" H 2740 6590 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:EN6347QI U15 +U 1 1 58023F0B +P 3100 8700 +F 0 "U15" H 2740 9790 60 0000 L BNN + 1 3100 8700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:QFN38" H 2740 9790 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R52 +U 1 1 58023F0A +P 1600 5200 +F 0 "R52" V 1510 5155 60 0000 R TNN +F 1 "4.7k" V 1540 5120 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1540 5120 60 0001 C CNN +F 3 "" H 1540 5120 60 0000 C CNN + 1 1600 5200 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R56 +U 1 1 58023F09 +P 4300 5100 +F 0 "R56" V 4210 5055 60 0000 R TNN +F 1 "205k" V 4220 5360 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4220 5360 60 0001 C CNN +F 3 "" H 4220 5360 60 0000 C CNN + 1 4300 5100 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R57 +U 1 1 58023F08 +P 4300 5700 +F 0 "R57" V 4210 5655 60 0000 R TNN +F 1 "147k" V 4210 5610 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4210 5610 60 0001 C CNN +F 3 "" H 4210 5610 60 0000 C CNN + 1 4300 5700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R60 +U 1 1 58023F07 +P 5500 5600 +F 0 "R60" V 5410 5555 60 0000 R TNN +F 1 "470" V 5450 5470 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5450 5470 60 0001 C CNN +F 3 "" H 5450 5470 60 0000 C CNN + 1 5500 5600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:BLM31PG330SN1_1206 FB5 +U 1 1 58023F06 +P 5800 4900 +F 0 "FB5" H 5650 5100 60 0000 L BNN +F 1 "BLM31PG330SN1" H 5640 4810 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:L_1206" H 5640 4810 60 0001 C CNN +F 3 "" H 5640 4810 60 0000 C CNN + 1 5800 4900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C114 +U 1 1 58023F05 +P 1100 8400 +F 0 "C114" H 1180 8210 60 0000 L BNN + 1 1100 8400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1180 8210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R55 +U 1 1 58023F04 +P 1600 9600 +F 0 "R55" V 1510 9555 60 0000 R TNN +F 1 "62k" V 1570 9470 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1570 9470 60 0001 C CNN +F 3 "" H 1570 9470 60 0000 C CNN + 1 1600 9600 + 0 -1 -1 0 +$EndComp +NoConn ~ 3900 5800 +NoConn ~ 3900 9000 +Wire Wire Line + 7000 4800 7000 4500 +$Comp +L Cryptech_Alpha:FPGA_VCCAUX_1V8 #PWR? +U 1 1 5AF45C1F +P 7000 4500 +F 0 "#PWR?" H 7000 4350 50 0001 C CNN +F 1 "FPGA_VCCAUX_1V8" H 7015 4673 50 0000 C CNN +F 2 "" H 7000 4500 60 0000 C CNN +F 3 "" H 7000 4500 60 0000 C CNN + 1 7000 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7000 8000 7000 7800 +$Comp +L Cryptech_Alpha:VCCO_3V3 #PWR? +U 1 1 5AF49BC2 +P 7000 7800 +F 0 "#PWR?" H 7000 7650 50 0001 C CNN +F 1 "VCCO_3V3" H 7015 7973 50 0000 C CNN +F 2 "" H 7000 7800 60 0000 C CNN +F 3 "" H 7000 7800 60 0000 C CNN + 1 7000 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA31D0 +P 6050 4800 +F 0 "#FLG?" H 6050 4875 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 4974 50 0000 C CNN +F 2 "" H 6050 4800 50 0001 C CNN +F 3 "~" H 6050 4800 50 0001 C CNN + 1 6050 4800 + 1 0 0 -1 +$EndComp +Connection ~ 6050 4800 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB3F33 +P 6050 8000 +F 0 "#FLG?" H 6050 8075 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 8174 50 0000 C CNN +F 2 "" H 6050 8000 50 0001 C CNN +F 3 "~" H 6050 8000 50 0001 C CNN + 1 6050 8000 + 1 0 0 -1 +$EndComp +Connection ~ 6050 8000 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_19.sch b/KiCAD/rev02_19.sch new file mode 100644 index 0000000..9f12bd2 --- /dev/null +++ b/KiCAD/rev02_19.sch @@ -0,0 +1,631 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 21 27 +Title "rev02_19" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 1000 4000 0 60 ~ 12 +*) Upper Right Bank +Text Notes 3290 7510 0 60 ~ 12 +*) FPGA_GCLK signal _MUST_ go into either D17 or C18\n(i.e. into one of the two positive (master) sides\nof the two available MRCC differential pairs) +Text Notes 3260 7850 0 60 ~ 12 +*) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped +Text Notes 6930 3910 0 60 ~ 12 +*) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank. +Text Notes 3300 6500 0 60 ~ 12 +NOTE: One of the FPGA_GPIO_* pins\nshould be connected to one of the\nMRCC pins.\nThe non-MRCC GPIO signals should be\nlength matched to within 500 ps of\nthe MRCC signal. +Text Notes 8840 10230 0 84 ~ 12 +FPGA GPIO +Text Notes 8950 4500 2 60 ~ 12 +MA08-2 +Text Notes 8950 5530 2 60 ~ 12 +SV2 +Text Notes 8950 6400 2 60 ~ 12 +MA08-2 +Text Notes 8950 7430 2 60 ~ 12 +SV3 +Text Notes 7260 5090 0 60 ~ 12 +C121 +Text Notes 7260 5290 0 60 ~ 12 +0.1~uF +Text Notes 7260 6990 0 60 ~ 12 +C122 +Text Notes 7260 7190 0 60 ~ 12 +0.1~uF +$Comp +L power:GND GND_125 +U 1 1 58023F03 +P 7200 5600 +F 0 "GND_125" H 7200 5600 20 0000 C CNN +F 1 "+GND" H 7200 5530 30 0000 C CNN +F 2 "" H 7200 5600 70 0000 C CNN +F 3 "" H 7200 5600 70 0000 C CNN + 1 7200 5600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_126 +U 1 1 58023F02 +P 8400 5600 +F 0 "GND_126" H 8400 5600 20 0000 C CNN +F 1 "+GND" H 8400 5530 30 0000 C CNN +F 2 "" H 8400 5600 70 0000 C CNN +F 3 "" H 8400 5600 70 0000 C CNN + 1 8400 5600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_127 +U 1 1 58023F01 +P 9200 5600 +F 0 "GND_127" H 9200 5600 20 0000 C CNN +F 1 "+GND" H 9200 5530 30 0000 C CNN +F 2 "" H 9200 5600 70 0000 C CNN +F 3 "" H 9200 5600 70 0000 C CNN + 1 9200 5600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_128 +U 1 1 58023F00 +P 7200 7500 +F 0 "GND_128" H 7200 7500 20 0000 C CNN +F 1 "+GND" H 7200 7430 30 0000 C CNN +F 2 "" H 7200 7500 70 0000 C CNN +F 3 "" H 7200 7500 70 0000 C CNN + 1 7200 7500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_129 +U 1 1 58023EFF +P 8400 7500 +F 0 "GND_129" H 8400 7500 20 0000 C CNN +F 1 "+GND" H 8400 7430 30 0000 C CNN +F 2 "" H 8400 7500 70 0000 C CNN +F 3 "" H 8400 7500 70 0000 C CNN + 1 8400 7500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_130 +U 1 1 58023EFE +P 9200 7500 +F 0 "GND_130" H 9200 7500 20 0000 C CNN +F 1 "+GND" H 9200 7430 30 0000 C CNN +F 2 "" H 9200 7500 70 0000 C CNN +F 3 "" H 9200 7500 70 0000 C CNN + 1 9200 7500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_35 +U 1 1 58023EFD +P 2100 4200 +F 0 "VCCO_3V3_35" H 2100 4200 20 0000 C CNN +F 1 "+VCCO_3V3" H 2100 4130 30 0000 C CNN +F 2 "" H 2100 4200 70 0000 C CNN +F 3 "" H 2100 4200 70 0000 C CNN + 1 2100 4200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_36 +U 1 1 58023EFC +P 7200 4300 +F 0 "VCCO_3V3_36" H 7200 4300 20 0000 C CNN +F 1 "+VCCO_3V3" H 7200 4230 30 0000 C CNN +F 2 "" H 7200 4300 70 0000 C CNN +F 3 "" H 7200 4300 70 0000 C CNN + 1 7200 4300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_37 +U 1 1 58023EFB +P 7200 6200 +F 0 "VCCO_3V3_37" H 7200 6200 20 0000 C CNN +F 1 "+VCCO_3V3" H 7200 6130 30 0000 C CNN +F 2 "" H 7200 6200 70 0000 C CNN +F 3 "" H 7200 6200 70 0000 C CNN + 1 7200 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_131 +U 1 1 58023EFA +P 9300 9100 +F 0 "GND_131" H 9300 9100 20 0000 C CNN +F 1 "+GND" H 9300 9030 30 0000 C CNN +F 2 "" H 9300 9100 70 0000 C CNN +F 3 "" H 9300 9100 70 0000 C CNN + 1 9300 9100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7200 5300 7200 5600 +Wire Wire Line + 8400 5200 8400 5600 +Wire Wire Line + 8500 5200 8400 5200 +Wire Wire Line + 8500 4900 8400 4900 +Wire Wire Line + 8400 4900 8400 5200 +Wire Wire Line + 9200 5200 9100 5200 +Wire Wire Line + 9200 5200 9200 5600 +Wire Wire Line + 9200 4900 9100 4900 +Wire Wire Line + 9200 4900 9200 5200 +Wire Wire Line + 7200 7200 7200 7500 +Wire Wire Line + 8400 7100 8400 7500 +Wire Wire Line + 8500 7100 8400 7100 +Wire Wire Line + 8500 6800 8400 6800 +Wire Wire Line + 8400 6800 8400 7100 +Wire Wire Line + 9200 7100 9100 7100 +Wire Wire Line + 9200 7100 9200 7500 +Wire Wire Line + 9200 6800 9100 6800 +Wire Wire Line + 9200 6800 9200 7100 +Wire Wire Line + 9300 8900 9300 9100 +Wire Wire Line + 9300 8900 9200 8900 +Wire Wire Line + 9300 8800 9000 8800 +Wire Wire Line + 9300 8800 9300 8900 +Wire Wire Line + 9300 8700 9200 8700 +Wire Wire Line + 9300 8600 9000 8600 +Wire Wire Line + 9300 8600 9300 8700 +Wire Wire Line + 9300 8700 9300 8800 +Wire Wire Line + 2100 4400 1900 4400 +Wire Wire Line + 2100 4400 2100 4500 +Wire Wire Line + 2100 4500 2100 4600 +Wire Wire Line + 2100 4600 2100 4700 +Wire Wire Line + 2100 4700 2100 4800 +Wire Wire Line + 2100 4800 1900 4800 +Wire Wire Line + 2100 4700 1900 4700 +Wire Wire Line + 2100 4600 1900 4600 +Wire Wire Line + 2100 4500 1900 4500 +Wire Wire Line + 2100 4200 2100 4400 +Wire Wire Line + 2100 4900 1900 4900 +Wire Wire Line + 2100 4800 2100 4900 +Wire Wire Line + 8400 4500 7200 4500 +Wire Wire Line + 7200 4300 7200 4500 +Wire Wire Line + 7200 4500 7200 5000 +Wire Wire Line + 8500 4800 8400 4800 +Wire Wire Line + 8400 4700 8400 4800 +Wire Wire Line + 8400 4500 8400 4700 +Wire Wire Line + 9200 4700 9100 4700 +Wire Wire Line + 9200 4500 9200 4700 +Wire Wire Line + 9200 4500 8400 4500 +Wire Wire Line + 9200 4800 9100 4800 +Wire Wire Line + 9200 4700 9200 4800 +Wire Wire Line + 8500 4700 8400 4700 +Wire Wire Line + 8400 6400 7200 6400 +Wire Wire Line + 7200 6200 7200 6400 +Wire Wire Line + 7200 6400 7200 6900 +Wire Wire Line + 8500 6700 8400 6700 +Wire Wire Line + 8400 6600 8400 6700 +Wire Wire Line + 8400 6400 8400 6600 +Wire Wire Line + 9200 6600 9100 6600 +Wire Wire Line + 9200 6400 9200 6600 +Wire Wire Line + 9200 6400 8400 6400 +Wire Wire Line + 9200 6700 9100 6700 +Wire Wire Line + 9200 6600 9200 6700 +Wire Wire Line + 8500 6600 8400 6600 +Wire Wire Line + 3100 8100 1900 8100 +Text GLabel 3100 8100 2 48 UnSpc ~ 0 +AVR_GPIO_FPGA_0 +Wire Wire Line + 3100 8200 1900 8200 +Text GLabel 3100 8200 2 48 UnSpc ~ 0 +AVR_GPIO_FPGA_1 +Wire Wire Line + 3100 5200 1900 5200 +Text GLabel 3100 5200 2 48 UnSpc ~ 0 +FPGA_IRQ_N_0 +Wire Wire Line + 3100 5300 1900 5300 +Text GLabel 3100 5300 2 48 UnSpc ~ 0 +FPGA_IRQ_N_1 +Wire Wire Line + 3100 5400 1900 5400 +Text GLabel 3100 5400 2 48 UnSpc ~ 0 +FPGA_IRQ_N_2 +Wire Wire Line + 3100 5500 1900 5500 +Text GLabel 3100 5500 2 48 UnSpc ~ 0 +FPGA_IRQ_N_3 +Wire Wire Line + 3100 5600 1900 5600 +Text GLabel 3100 5800 2 48 BiDi ~ 0 +FPGA_GPIO_A_0 +Wire Wire Line + 8500 5000 7600 5000 +Text GLabel 7600 5000 0 48 BiDi ~ 0 +FPGA_GPIO_A_0 +Wire Wire Line + 3100 5700 1900 5700 +Text GLabel 3100 5700 2 48 BiDi ~ 0 +FPGA_GPIO_A_1 +Wire Wire Line + 10000 5000 9100 5000 +Text GLabel 10000 5000 2 48 BiDi ~ 0 +FPGA_GPIO_A_1 +Wire Wire Line + 3100 5800 1900 5800 +Text GLabel 3100 6900 2 48 BiDi ~ 0 +FPGA_GPIO_A_2 +Wire Wire Line + 8500 5100 7600 5100 +Text GLabel 7600 5100 0 48 BiDi ~ 0 +FPGA_GPIO_A_2 +Text GLabel 3100 7000 2 48 BiDi ~ 0 +FPGA_GPIO_A_3 +Wire Wire Line + 10000 5100 9100 5100 +Text GLabel 10000 5100 2 48 BiDi ~ 0 +FPGA_GPIO_A_3 +Text GLabel 3100 6500 2 48 BiDi ~ 0 +FPGA_GPIO_A_4 +Wire Wire Line + 8500 5300 7600 5300 +Text GLabel 7600 5300 0 48 BiDi ~ 0 +FPGA_GPIO_A_4 +Wire Wire Line + 3100 6100 1900 6100 +Text GLabel 3100 6600 2 48 BiDi ~ 0 +FPGA_GPIO_A_5 +Wire Wire Line + 10000 5300 9100 5300 +Text GLabel 10000 5300 2 48 BiDi ~ 0 +FPGA_GPIO_A_5 +Text GLabel 3100 6700 2 48 BiDi ~ 0 +FPGA_GPIO_A_6 +Wire Wire Line + 8500 5400 7600 5400 +Text GLabel 7600 5400 0 48 BiDi ~ 0 +FPGA_GPIO_A_6 +Wire Wire Line + 3100 6300 1900 6300 +Text GLabel 3100 6300 2 48 BiDi ~ 0 +FPGA_GPIO_A_7 +Wire Wire Line + 10000 5400 9100 5400 +Text GLabel 10000 5400 2 48 BiDi ~ 0 +FPGA_GPIO_A_7 +Wire Wire Line + 3100 6400 1900 6400 +Text GLabel 3100 6800 2 48 BiDi ~ 0 +FPGA_GPIO_B_0 +Wire Wire Line + 8500 6900 7600 6900 +Text GLabel 7600 6900 0 48 BiDi ~ 0 +FPGA_GPIO_B_0 +Wire Wire Line + 3100 6500 1900 6500 +Text GLabel 3100 5600 2 48 BiDi ~ 0 +FPGA_GPIO_B_1 +Wire Wire Line + 10000 6900 9100 6900 +Text GLabel 10000 6900 2 48 BiDi ~ 0 +FPGA_GPIO_B_1 +Wire Wire Line + 3100 6600 1900 6600 +Text GLabel 3100 6400 2 48 BiDi ~ 0 +FPGA_GPIO_B_2 +Wire Wire Line + 8500 7000 7600 7000 +Text GLabel 7600 7000 0 48 BiDi ~ 0 +FPGA_GPIO_B_2 +Wire Wire Line + 3100 6700 1900 6700 +Text GLabel 3100 6100 2 48 BiDi ~ 0 +FPGA_GPIO_B_3 +Wire Wire Line + 10000 7000 9100 7000 +Text GLabel 10000 7000 2 48 BiDi ~ 0 +FPGA_GPIO_B_3 +Wire Wire Line + 3100 6800 1900 6800 +Text GLabel 3100 7500 2 48 BiDi ~ 0 +FPGA_GPIO_B_4 +Wire Wire Line + 8500 7200 7600 7200 +Text GLabel 7600 7200 0 48 BiDi ~ 0 +FPGA_GPIO_B_4 +Wire Wire Line + 3100 6900 1900 6900 +Text GLabel 3100 9200 2 48 BiDi ~ 0 +FPGA_GPIO_B_5 +Wire Wire Line + 10000 7200 9100 7200 +Text GLabel 10000 7200 2 48 BiDi ~ 0 +FPGA_GPIO_B_5 +Wire Wire Line + 3100 7000 1900 7000 +Text GLabel 3100 8800 2 48 BiDi ~ 0 +FPGA_GPIO_B_6 +Wire Wire Line + 8500 7300 7600 7300 +Text GLabel 7600 7300 0 48 BiDi ~ 0 +FPGA_GPIO_B_6 +Text GLabel 3100 8900 2 48 BiDi ~ 0 +FPGA_GPIO_B_7 +Wire Wire Line + 10000 7300 9100 7300 +Text GLabel 10000 7300 2 48 BiDi ~ 0 +FPGA_GPIO_B_7 +Wire Wire Line + 3100 7300 1900 7300 +Text GLabel 3100 7300 2 48 UnSpc ~ 0 +FPGA_GCLK +Wire Wire Line + 7890 8700 7300 8700 +Text GLabel 7300 8700 0 48 Input ~ 0 +FPGA_GPIO_LED_2 +Wire Wire Line + 8200 8600 7300 8600 +Text GLabel 7300 8600 0 48 Input ~ 0 +FPGA_GPIO_LED_3 +Wire Wire Line + 7890 8900 7300 8900 +Text GLabel 7300 8900 0 48 Input ~ 0 +FPGA_GPIO_LED_0 +Wire Wire Line + 8200 8800 7300 8800 +Text GLabel 7300 8800 0 48 Input ~ 0 +FPGA_GPIO_LED_1 +Wire Wire Line + 8900 8900 8290 8900 +Wire Wire Line + 8700 8800 8600 8800 +Wire Wire Line + 8900 8700 8290 8700 +Wire Wire Line + 8700 8600 8600 8600 +Wire Wire Line + 3100 7200 1900 7200 +Text GLabel 3100 7200 2 48 Output ~ 0 +FPGA_ENTROPY_DISABLE +Wire Wire Line + 3100 8300 1900 8300 +Text GLabel 3100 8300 2 48 UnSpc ~ 0 +AVR_GPIO_FPGA_2 +Wire Wire Line + 3100 8400 1900 8400 +Text GLabel 3100 8400 2 48 UnSpc ~ 0 +AVR_GPIO_FPGA_3 +Wire Wire Line + 3100 7500 1900 7500 +Wire Wire Line + 3100 8800 1900 8800 +Wire Wire Line + 3100 8900 1900 8900 +Wire Wire Line + 3100 9200 1900 9200 +$Comp +L Cryptech_Alpha:MA08-2 SV2 +U 1 1 58023EF9 +P 8800 5000 +F 0 "SV2" H 8980 5630 60 0000 R TNN + 1 8800 5000 + -1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:PLD-16" H 8980 5630 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R99 +U 1 1 58023EF8 +P 8400 8600 +F 0 "R99" H 8490 8420 60 0000 R TNN +F 1 "330" H 8500 8510 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8500 8510 60 0001 C CNN +F 3 "" H 8500 8510 60 0000 C CNN + 1 8400 8600 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R98 +U 1 1 58023EF7 +P 8090 8700 +F 0 "R98" H 8220 8420 60 0000 R TNN +F 1 "330" H 8230 8510 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8230 8510 60 0001 C CNN +F 3 "" H 8230 8510 60 0000 C CNN + 1 8090 8700 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R64 +U 1 1 58023EF6 +P 8400 8800 +F 0 "R64" H 8080 8410 60 0000 R TNN +F 1 "330" H 8090 8500 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8090 8500 60 0001 C CNN +F 3 "" H 8090 8500 60 0000 C CNN + 1 8400 8800 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R100 +U 1 1 58023EF5 +P 8090 8900 +F 0 "R100" H 8180 9070 60 0000 R TNN +F 1 "330" H 8190 9160 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8190 9160 60 0001 C CNN +F 3 "" H 8190 9160 60 0000 C CNN + 1 8090 8900 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:MA08-2 SV3 +U 1 1 58023EF4 +P 8800 6900 +F 0 "SV3" H 8980 7530 60 0000 R TNN + 1 8800 6900 + -1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:PLD-16" H 8980 7530 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C121 +U 1 1 58023EF3 +P 7200 5100 +F 0 "C121" H 7280 4910 60 0000 L BNN +F 1 "0.1uF" H 7320 5010 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7320 5010 60 0001 C CNN +F 3 "" H 7320 5010 60 0000 C CNN + 1 7200 5100 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C122 +U 1 1 58023EF2 +P 7200 7000 +F 0 "C122" H 7280 6810 60 0000 L BNN +F 1 "0.1uF" H 7330 6910 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7330 6910 60 0001 C CNN +F 3 "" H 7330 6910 60 0000 C CNN + 1 7200 7000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED17 +U 1 1 58023EF1 +P 9000 8900 +F 0 "LED17" V 8960 8526 60 0000 R TNN +F 1 "LTST-C193TBKT-5A" V 8960 8220 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8960 8220 60 0001 C CNN +F 3 "" H 8960 8220 60 0000 C CNN + 1 9000 8900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED15 +U 1 1 58023EF0 +P 8800 8800 +F 0 "LED15" V 8760 8226 60 0000 R TNN +F 1 "LTST-C191KGKT" V 8760 7920 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8760 7920 60 0001 C CNN +F 3 "" H 8760 7920 60 0000 C CNN + 1 8800 8800 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED16 +U 1 1 58023EEF +P 9000 8700 +F 0 "LED16" V 8960 8326 60 0000 R TNN +F 1 "LTST-C191KSKT" V 8960 8030 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8960 8030 60 0001 C CNN +F 3 "" H 8960 8030 60 0000 C CNN + 1 9000 8700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED14 +U 1 1 58023EEE +P 8800 8600 +F 0 "LED14" V 8760 8026 60 0000 R TNN +F 1 "LTST-C191KRKT" V 8760 7720 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8760 7720 60 0001 C CNN +F 3 "" H 8760 7720 60 0000 C CNN + 1 8800 8600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_5 U13_11 +U 1 1 58023EED +P 1700 7100 +F 0 "U13_11" H 1290 4090 60 0000 L BNN + 1 1700 7100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1290 4090 60 0001 C CNN +$EndComp +NoConn ~ 1900 5000 +NoConn ~ 1900 5100 +NoConn ~ 1900 5900 +NoConn ~ 1900 6000 +NoConn ~ 1900 7100 +NoConn ~ 1900 7400 +NoConn ~ 1900 7600 +NoConn ~ 1900 7700 +NoConn ~ 1900 7800 +NoConn ~ 1900 8000 +NoConn ~ 1900 7900 +NoConn ~ 1900 8500 +NoConn ~ 1900 8600 +NoConn ~ 1900 8700 +NoConn ~ 1900 9000 +NoConn ~ 1900 9100 +NoConn ~ 1900 9300 +NoConn ~ 1900 9400 +NoConn ~ 1900 9500 +NoConn ~ 1900 9600 +NoConn ~ 1900 9700 +NoConn ~ 1900 9800 +NoConn ~ 1900 9900 +NoConn ~ 1900 6200 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_20.sch b/KiCAD/rev02_20.sch new file mode 100644 index 0000000..443d139 --- /dev/null +++ b/KiCAD/rev02_20.sch @@ -0,0 +1,262 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 22 27 +Title "rev02_20" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 1600 4100 0 60 ~ 12 +*) Lower Right Bank +Text Notes 3820 7410 0 60 ~ 12 +DIGITIZED_NOISE signal should go into\neither W19 or Y18 (i.e. into one of the two\npositive (master) sides of the two available\nMRCC differential pairs) +Text Notes 6500 4100 0 60 ~ 12 +*) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank. +Text Notes 4800 6500 0 60 ~ 12 +<-- FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped +Text Notes 4980 4810 0 60 ~ 12 +<-- Disable pull-ups on all pins during configuration +Text Notes 8500 10220 0 84 ~ 12 +FPGA MKM interface +Text Notes 4280 4890 0 60 ~ 12 +R65 +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_38 +U 1 1 58023EEC +P 4200 4300 +F 0 "VCCO_3V3_38" H 4200 4300 20 0000 C CNN +F 1 "+VCCO_3V3" H 4200 4230 30 0000 C CNN +F 2 "" H 4200 4300 70 0000 C CNN +F 3 "" H 4200 4300 70 0000 C CNN + 1 4200 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 7400 2400 7400 +Text GLabel 3600 7400 2 48 Input ~ 0 +DIGITIZED_NOISE +Wire Wire Line + 3600 6500 2400 6500 +Text GLabel 3600 6500 2 48 Output ~ 0 +FPGA_GPIO_LED_2 +Wire Wire Line + 3600 6600 2400 6600 +Text GLabel 3600 6600 2 48 Output ~ 0 +FPGA_GPIO_LED_3 +Wire Wire Line + 3600 6400 2400 6400 +Wire Wire Line + 2900 5600 2400 5600 +Wire Wire Line + 2600 4500 2400 4500 +Wire Wire Line + 2600 4500 2600 4600 +Wire Wire Line + 2600 4600 2600 4700 +Wire Wire Line + 2600 4700 2600 4800 +Wire Wire Line + 2600 4800 2600 4900 +Wire Wire Line + 2600 4900 2400 4900 +Wire Wire Line + 2600 4800 2400 4800 +Wire Wire Line + 2600 4700 2400 4700 +Wire Wire Line + 2600 4600 2400 4600 +Wire Wire Line + 2900 4500 2600 4500 +Wire Wire Line + 4200 4300 4200 4500 +Wire Wire Line + 2600 4900 2600 5000 +Wire Wire Line + 2600 5000 2400 5000 +Wire Wire Line + 3600 5200 3500 5200 +Text GLabel 3600 5200 2 48 UnSpc ~ 0 +FPGA_CFG_MOSI +Wire Wire Line + 3600 5300 3500 5300 +Text GLabel 3600 5300 2 48 Input ~ 0 +FPGA_CFG_MISO +Wire Wire Line + 3600 6200 3500 6200 +Text GLabel 3600 6200 2 48 Output ~ 0 +FPGA_CFG_CS_N +Wire Wire Line + 3100 5300 2400 5300 +Text Label 2460 5300 2 48 ~ 0 +FPGA_CFG_MISO1 +Wire Wire Line + 3100 5200 2400 5200 +Text Label 2460 5200 2 48 ~ 0 +FPGA_CFG_MOSI1 +Wire Wire Line + 3100 6200 2400 6200 +Text Label 2460 6200 2 48 ~ 0 +FPGA_CFG_CS_N1 +Text GLabel 3600 7000 2 48 Input ~ 0 +FMC_A19 +Text GLabel 3600 7100 2 48 Input ~ 0 +FMC_A20 +Wire Wire Line + 3600 7000 2400 7000 +Wire Wire Line + 3600 7100 2400 7100 +Text GLabel 3610 8100 2 48 Input ~ 0 +FMC_A21 +Wire Wire Line + 3610 8100 2400 8100 +Text GLabel 3600 6800 2 48 Input ~ 0 +FMC_A22 +Text GLabel 3600 6900 2 48 Input ~ 0 +FMC_A23 +Wire Wire Line + 3600 6900 2400 6900 +Wire Wire Line + 3600 6800 2400 6800 +Text GLabel 3600 8500 2 48 Input ~ 0 +FMC_A24 +Wire Wire Line + 3600 8500 2400 8500 +Text GLabel 3600 8000 2 48 Input ~ 0 +FMC_A25 +Wire Wire Line + 3600 8000 2400 8000 +Text GLabel 3600 7600 2 48 BiDi ~ 0 +FMC_D8 +Wire Wire Line + 3600 7600 2400 7600 +Text GLabel 3600 6700 2 48 BiDi ~ 0 +FMC_D9 +Wire Wire Line + 3600 6700 2400 6700 +Text GLabel 3600 7500 2 48 BiDi ~ 0 +FMC_D10 +Wire Wire Line + 3600 7500 2400 7500 +Text GLabel 3600 7200 2 48 BiDi ~ 0 +FMC_D12 +Wire Wire Line + 3600 7200 2400 7200 +Text GLabel 3600 7300 2 48 BiDi ~ 0 +FMC_D28 +Wire Wire Line + 3600 7300 2400 7300 +Text GLabel 3600 7800 2 48 BiDi ~ 0 +FMC_D29 +Wire Wire Line + 3600 7800 2400 7800 +Text GLabel 3100 5500 2 48 BiDi ~ 0 +FMC_D30 +Wire Wire Line + 3100 5500 2400 5500 +Text GLabel 3100 5400 2 48 BiDi ~ 0 +FMC_D31 +Wire Wire Line + 3100 5400 2400 5400 +Text GLabel 3600 8300 2 48 UnSpc ~ 0 +FMC_NL +Wire Wire Line + 3600 8300 2400 8300 +Text GLabel 3600 10000 2 48 BiDi ~ 0 +FMC_D11 +Wire Wire Line + 3600 10000 2400 10000 +Wire Wire Line + 4200 5600 2900 5600 +Wire Wire Line + 4200 5000 4200 5600 +Wire Wire Line + 4200 4500 2900 4500 +Wire Wire Line + 4200 4600 4200 4500 +$Comp +L Cryptech_Alpha:R-EU_R0402 R65 +U 1 1 58023EEB +P 4200 4800 +F 0 "R65" V 4110 4755 60 0000 R TNN +F 1 "1k" V 4030 4730 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 4030 4730 60 0001 C CNN +F 3 "" H 4030 4730 60 0000 C CNN + 1 4200 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R83 +U 1 1 58023EEA +P 3300 5200 +F 0 "R83" H 3410 5120 60 0000 R TNN +F 1 "0" H 3220 5120 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3220 5120 60 0001 C CNN +F 3 "" H 3220 5120 60 0000 C CNN + 1 3300 5200 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R84 +U 1 1 58023EE9 +P 3300 5300 +F 0 "R84" H 3400 5480 60 0000 R TNN +F 1 "0" H 3210 5470 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3210 5470 60 0001 C CNN +F 3 "" H 3210 5470 60 0000 C CNN + 1 3300 5300 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0603 R85 +U 1 1 58023EE8 +P 3300 6200 +F 0 "R85" H 3180 6200 60 0000 R TNN +F 1 "0" H 3170 6300 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 3170 6300 60 0001 C CNN +F 3 "" H 3170 6300 60 0000 C CNN + 1 3300 6200 + -1 0 0 1 +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_3 U13_12 +U 1 1 58023EE7 +P 2200 7200 +F 0 "U13_12" H 1790 4190 60 0000 L BNN + 1 2200 7200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1790 4190 60 0001 C CNN +$EndComp +NoConn ~ 2400 5700 +NoConn ~ 2400 5900 +NoConn ~ 2400 5800 +NoConn ~ 2400 6000 +NoConn ~ 2400 6100 +NoConn ~ 2400 6300 +NoConn ~ 2400 7700 +NoConn ~ 2400 7900 +NoConn ~ 2400 8200 +NoConn ~ 2400 8400 +NoConn ~ 2400 8600 +NoConn ~ 2400 8700 +NoConn ~ 2400 8800 +NoConn ~ 2400 8900 +NoConn ~ 2400 9000 +NoConn ~ 2400 9100 +NoConn ~ 2400 9200 +NoConn ~ 2400 9300 +NoConn ~ 2400 9400 +NoConn ~ 2400 9500 +NoConn ~ 2400 9600 +NoConn ~ 2400 9700 +NoConn ~ 2400 9800 +NoConn ~ 2400 9900 +NoConn ~ 2400 5100 +NoConn ~ 3600 6400 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_21.sch b/KiCAD/rev02_21.sch new file mode 100644 index 0000000..8bb433b --- /dev/null +++ b/KiCAD/rev02_21.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 23 27 +Title "rev02_21" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 8100 4600 0 60 ~ 12 +*) Power - AUX +Text Notes 5000 4600 0 60 ~ 12 +*) Power - CORE & BRAM +Text Notes 2000 4500 0 60 ~ 12 +*) Ground Pins +Text Notes 8460 10210 0 66 ~ 12 +FPGA power and ground +$Comp +L power:GND GND_132 +U 1 1 58023EE6 +P 2000 9700 +F 0 "GND_132" H 2000 9700 20 0000 C CNN +F 1 "+GND" H 2000 9630 30 0000 C CNN +F 2 "" H 2000 9700 70 0000 C CNN +F 3 "" H 2000 9700 70 0000 C CNN + 1 2000 9700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_133 +U 1 1 58023EE5 +P 3800 9600 +F 0 "GND_133" H 3800 9600 20 0000 C CNN +F 1 "+GND" H 3800 9530 30 0000 C CNN +F 2 "" H 3800 9600 70 0000 C CNN +F 3 "" H 3800 9600 70 0000 C CNN + 1 3800 9600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FPGA_VCCINT_1V0 FPGA_VCCINT_1V0 +U 1 1 58023EE4 +P 6000 4900 +F 0 "FPGA_VCCINT_1V0" H 6000 4900 20 0000 C CNN +F 1 "+FPGA_VCCINT_1V0" H 6000 4830 30 0000 C CNN +F 2 "" H 6000 4900 70 0000 C CNN +F 3 "" H 6000 4900 70 0000 C CNN + 1 6000 4900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:FPGA_VCCAUX_1V8 FPGA_VCCAUX_1V8_2 +U 1 1 58023EE3 +P 9000 4900 +F 0 "FPGA_VCCAUX_1V8_2" H 9000 4900 20 0000 C CNN +F 1 "+FPGA_VCCAUX_1V8" H 9000 4830 30 0000 C CNN +F 2 "" H 9000 4900 70 0000 C CNN +F 3 "" H 9000 4900 70 0000 C CNN + 1 9000 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 9500 1800 9500 +Wire Wire Line + 2000 9500 2000 9700 +Wire Wire Line + 2000 9400 1800 9400 +Wire Wire Line + 2000 9400 2000 9500 +Wire Wire Line + 2000 9000 1800 9000 +Wire Wire Line + 2000 9000 2000 9100 +Wire Wire Line + 2000 9100 2000 9200 +Wire Wire Line + 2000 9200 2000 9300 +Wire Wire Line + 2000 9300 2000 9400 +Wire Wire Line + 2000 9100 1800 9100 +Wire Wire Line + 2000 9200 1800 9200 +Wire Wire Line + 2000 9300 1800 9300 +Wire Wire Line + 2000 8900 1800 8900 +Wire Wire Line + 2000 8900 2000 9000 +Wire Wire Line + 2000 8800 1800 8800 +Wire Wire Line + 2000 8800 2000 8900 +Wire Wire Line + 2000 8700 1800 8700 +Wire Wire Line + 2000 8700 2000 8800 +Wire Wire Line + 2000 8600 1800 8600 +Wire Wire Line + 2000 8600 2000 8700 +Wire Wire Line + 2000 8500 1800 8500 +Wire Wire Line + 2000 8500 2000 8600 +Wire Wire Line + 2000 8400 1800 8400 +Wire Wire Line + 2000 8400 2000 8500 +Wire Wire Line + 2000 8300 1800 8300 +Wire Wire Line + 2000 8300 2000 8400 +Wire Wire Line + 2000 8200 1800 8200 +Wire Wire Line + 2000 8200 2000 8300 +Wire Wire Line + 2000 8100 1800 8100 +Wire Wire Line + 2000 8100 2000 8200 +Wire Wire Line + 2000 8000 1800 8000 +Wire Wire Line + 2000 8000 2000 8100 +Wire Wire Line + 2000 7900 1800 7900 +Wire Wire Line + 2000 7900 2000 8000 +Wire Wire Line + 2000 7800 1800 7800 +Wire Wire Line + 2000 7800 2000 7900 +Wire Wire Line + 2000 7700 1800 7700 +Wire Wire Line + 2000 7700 2000 7800 +Wire Wire Line + 2000 7600 1800 7600 +Wire Wire Line + 2000 7600 2000 7700 +Wire Wire Line + 2000 7500 1800 7500 +Wire Wire Line + 2000 7500 2000 7600 +Wire Wire Line + 2000 7400 1800 7400 +Wire Wire Line + 2000 7400 2000 7500 +Wire Wire Line + 2000 7300 1800 7300 +Wire Wire Line + 2000 7300 2000 7400 +Wire Wire Line + 2000 7200 1800 7200 +Wire Wire Line + 2000 7200 2000 7300 +Wire Wire Line + 2000 7100 1800 7100 +Wire Wire Line + 2000 7100 2000 7200 +Wire Wire Line + 2000 7000 1800 7000 +Wire Wire Line + 2000 7000 2000 7100 +Wire Wire Line + 2000 6900 1800 6900 +Wire Wire Line + 2000 6900 2000 7000 +Wire Wire Line + 2000 6800 1800 6800 +Wire Wire Line + 2000 6800 2000 6900 +Wire Wire Line + 2000 6700 1800 6700 +Wire Wire Line + 2000 6700 2000 6800 +Wire Wire Line + 2000 6600 1800 6600 +Wire Wire Line + 2000 6600 2000 6700 +Wire Wire Line + 2000 6500 1800 6500 +Wire Wire Line + 2000 6500 2000 6600 +Wire Wire Line + 2000 6400 1800 6400 +Wire Wire Line + 2000 6400 2000 6500 +Wire Wire Line + 2000 6300 1800 6300 +Wire Wire Line + 2000 6300 2000 6400 +Wire Wire Line + 2000 6200 1800 6200 +Wire Wire Line + 2000 6200 2000 6300 +Wire Wire Line + 2000 6100 1800 6100 +Wire Wire Line + 2000 6100 2000 6200 +Wire Wire Line + 2000 6000 1800 6000 +Wire Wire Line + 2000 6000 2000 6100 +Wire Wire Line + 2000 5900 1800 5900 +Wire Wire Line + 2000 5900 2000 6000 +Wire Wire Line + 2000 5800 1800 5800 +Wire Wire Line + 2000 5800 2000 5900 +Wire Wire Line + 2000 5700 1800 5700 +Wire Wire Line + 2000 5700 2000 5800 +Wire Wire Line + 2000 5600 1800 5600 +Wire Wire Line + 2000 5600 2000 5700 +Wire Wire Line + 2000 5500 1800 5500 +Wire Wire Line + 2000 5500 2000 5600 +Wire Wire Line + 2000 5400 1800 5400 +Wire Wire Line + 2000 5400 2000 5500 +Wire Wire Line + 2000 5300 1800 5300 +Wire Wire Line + 2000 5300 2000 5400 +Wire Wire Line + 2000 5200 1800 5200 +Wire Wire Line + 2000 5200 2000 5300 +Wire Wire Line + 3800 9400 3600 9400 +Wire Wire Line + 3800 9400 3800 9600 +Wire Wire Line + 3800 5200 3600 5200 +Wire Wire Line + 3800 5200 3800 5300 +Wire Wire Line + 3800 5300 3800 5400 +Wire Wire Line + 3800 5400 3800 5500 +Wire Wire Line + 3800 5500 3800 5600 +Wire Wire Line + 3800 5600 3800 5700 +Wire Wire Line + 3800 5700 3800 5800 +Wire Wire Line + 3800 5800 3800 5900 +Wire Wire Line + 3800 5900 3800 6000 +Wire Wire Line + 3800 6000 3800 6100 +Wire Wire Line + 3800 6100 3800 6200 +Wire Wire Line + 3800 6200 3800 6300 +Wire Wire Line + 3800 6300 3800 6400 +Wire Wire Line + 3800 6400 3800 6500 +Wire Wire Line + 3800 6500 3800 6600 +Wire Wire Line + 3800 6600 3800 6700 +Wire Wire Line + 3800 6700 3800 6800 +Wire Wire Line + 3800 6800 3800 6900 +Wire Wire Line + 3800 6900 3800 7000 +Wire Wire Line + 3800 7000 3800 7100 +Wire Wire Line + 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Line + 6000 6200 6000 6300 +Wire Wire Line + 6000 6400 5800 6400 +Wire Wire Line + 6000 6300 6000 6400 +Wire Wire Line + 6000 6500 5800 6500 +Wire Wire Line + 6000 6400 6000 6500 +Wire Wire Line + 6000 7200 5800 7200 +Wire Wire Line + 6000 7100 6000 7200 +Wire Wire Line + 6000 7000 6000 7100 +Wire Wire Line + 6000 6900 6000 7000 +Wire Wire Line + 6000 6800 6000 6900 +Wire Wire Line + 6000 6700 6000 6800 +Wire Wire Line + 6000 6600 6000 6700 +Wire Wire Line + 6000 6500 6000 6600 +Wire Wire Line + 6000 6600 5800 6600 +Wire Wire Line + 6000 6700 5800 6700 +Wire Wire Line + 6000 6800 5800 6800 +Wire Wire Line + 6000 6900 5800 6900 +Wire Wire Line + 6000 7000 5800 7000 +Wire Wire Line + 6000 7100 5800 7100 +Wire Wire Line + 9000 5100 8800 5100 +Wire Wire Line + 9000 5100 9000 5200 +Wire Wire Line + 9000 5200 9000 5300 +Wire Wire Line + 9000 5300 9000 5400 +Wire Wire Line + 9000 5400 9000 5500 +Wire Wire Line + 9000 5500 8800 5500 +Wire Wire Line + 9000 5400 8800 5400 +Wire Wire Line + 9000 5300 8800 5300 +Wire Wire Line + 9000 5200 8800 5200 +Wire Wire Line + 9000 4900 9000 5100 +$Comp +L Cryptech_Alpha:XC7A200TFBG484_9 U13_13 +U 1 1 58023EE2 +P 1600 7300 +F 0 "U13_13" H 1190 4890 60 0000 L BNN + 1 1600 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_10 U13_14 +U 1 1 58023EE1 +P 3400 7300 +F 0 "U13_14" H 2990 4990 60 0000 L BNN + 1 3400 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 2990 4990 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_14 U13_15 +U 1 1 58023EE0 +P 8600 5300 +F 0 "U13_15" H 8190 4890 60 0000 L BNN + 1 8600 5300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 8190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_15 U13_16 +U 1 1 58023EDF +P 5600 5200 +F 0 "U13_16" H 5190 4890 60 0000 L BNN + 1 5600 5200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 5190 4890 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:XC7A200TFBG484_16 U13_17 +U 1 1 58023EDE +P 5600 6600 +F 0 "U13_17" H 5190 7410 60 0000 L TNN + 1 5600 6600 + 1 0 0 1 +F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 5190 7410 60 0001 C CNN +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_22.sch b/KiCAD/rev02_22.sch new file mode 100644 index 0000000..0a7814e --- /dev/null +++ b/KiCAD/rev02_22.sch @@ -0,0 +1,1356 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 24 27 +Title "rev02_22" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 7000 5300 0 60 ~ 12 +<-- Place small 0.47 uF caps right under the BGA package\n<-- Place medium 4.7 uF caps very close to the BGA\n package\n<-- Place large 47 uF and 330 uF caps not far\n from the BGA package\n<-- Distribute smaller caps evenly under the BGA package\n<-- Distribute larger caps evenly around the BGA package +Text Notes 2800 4200 0 60 ~ 12 +*) Decoupling capacitors for VCCINT and VCCBRAM +Text Notes 6600 8500 0 60 ~ 12 +<-- Place small 0.47 uF caps right under the BGA package\n<-- Place medium 4.7 uF caps very close to the BGA package\n<-- Place large 47 uF caps not far from the BGA package\n<-- Try to place smaller caps next to FPGA balls +Text Notes 2800 7500 0 60 ~ 12 +*) Decoupling capacitors for VCCAUX +Text Notes 8620 10190 0 48 ~ 12 +FPGA CORE and AUX capacitors +Text Notes 3760 4690 0 60 ~ 12 +C140 +Text Notes 3760 4890 0 60 ~ 12 +4.7uF +Text Notes 1360 6490 0 60 ~ 12 +C125 +Text Notes 1360 6690 0 60 ~ 12 +0.47uF +Text Notes 2560 4690 0 60 ~ 12 +C133 +Text Notes 2560 4890 0 60 ~ 12 +47uF +Text Notes 1360 5590 0 60 ~ 12 +C124 +Text Notes 1360 5790 0 60 ~ 12 +0.47uF +Text Notes 1860 5590 0 60 ~ 12 +C128 +Text Notes 1860 5790 0 60 ~ 12 +0.47uF +Text Notes 2360 5590 0 60 ~ 12 +C130 +Text Notes 2360 5790 0 60 ~ 12 +0.47uF +Text Notes 2860 5590 0 60 ~ 12 +C134 +Text Notes 2860 5790 0 60 ~ 12 +0.47uF +Text Notes 1860 6490 0 60 ~ 12 +C129 +Text Notes 1860 6690 0 60 ~ 12 +0.47uF +Text Notes 2360 6490 0 60 ~ 12 +C131 +Text Notes 2360 6690 0 60 ~ 12 +0.47uF +Text Notes 2860 6490 0 60 ~ 12 +C135 +Text Notes 2860 6690 0 60 ~ 12 +0.47uF +Text Notes 3360 6490 0 60 ~ 12 +C138 +Text Notes 3360 6690 0 60 ~ 12 +0.47uF +Text Notes 3860 6490 0 60 ~ 12 +C142 +Text Notes 3860 6690 0 60 ~ 12 +0.47uF +Text Notes 4360 6490 0 60 ~ 12 +C146 +Text Notes 4360 6690 0 60 ~ 12 +0.47uF +Text Notes 4860 6490 0 60 ~ 12 +C150 +Text Notes 4860 6690 0 60 ~ 12 +0.47uF +Text Notes 5360 6490 0 60 ~ 12 +C154 +Text Notes 5360 6690 0 60 ~ 12 +0.47uF +Text Notes 5860 6490 0 60 ~ 12 +C158 +Text Notes 5860 6690 0 60 ~ 12 +0.47uF +Text Notes 6360 6490 0 60 ~ 12 +C162 +Text Notes 6360 6690 0 60 ~ 12 +0.47uF +Text Notes 6860 6490 0 60 ~ 12 +C163 +Text Notes 6860 6690 0 60 ~ 12 +0.47uF +Text Notes 4060 8090 0 60 ~ 12 +C143 +Text Notes 4060 8290 0 60 ~ 12 +0.47uF +Text Notes 4560 8090 0 60 ~ 12 +C147 +Text Notes 4560 8290 0 60 ~ 12 +0.47uF +Text Notes 5060 8090 0 60 ~ 12 +C151 +Text Notes 5060 8290 0 60 ~ 12 +0.47uF +Text Notes 5560 8090 0 60 ~ 12 +C155 +Text Notes 5560 8290 0 60 ~ 12 +0.47uF +Text Notes 6060 8090 0 60 ~ 12 +C159 +Text Notes 6060 8290 0 60 ~ 12 +0.47uF +Text Notes 7360 6490 0 60 ~ 12 +C164 +Text Notes 7360 6690 0 60 ~ 12 +0.47uF +Text Notes 4260 4690 0 60 ~ 12 +C144 +Text Notes 4260 4890 0 60 ~ 12 +4.7uF +Text Notes 4760 4690 0 60 ~ 12 +C148 +Text Notes 4760 4890 0 60 ~ 12 +4.7uF +Text Notes 5260 4690 0 60 ~ 12 +C152 +Text Notes 5260 4890 0 60 ~ 12 +4.7uF +Text Notes 5760 4690 0 60 ~ 12 +C156 +Text Notes 5760 4890 0 60 ~ 12 +4.7uF +Text Notes 6260 4690 0 60 ~ 12 +C160 +Text Notes 6260 4890 0 60 ~ 12 +4.7uF +Text Notes 3760 5590 0 60 ~ 12 +C141 +Text Notes 3760 5790 0 60 ~ 12 +4.7uF +Text Notes 4260 5590 0 60 ~ 12 +C145 +Text Notes 4260 5790 0 60 ~ 12 +4.7uF +Text Notes 4760 5590 0 60 ~ 12 +C149 +Text Notes 4760 5790 0 60 ~ 12 +4.7uF +Text Notes 5260 5590 0 60 ~ 12 +C153 +Text Notes 5260 5790 0 60 ~ 12 +4.7uF +Text Notes 5760 5590 0 60 ~ 12 +C157 +Text Notes 5760 5790 0 60 ~ 12 +4.7uF +Text Notes 6260 5590 0 60 ~ 12 +C161 +Text Notes 6260 5790 0 60 ~ 12 +4.7uF +Text Notes 2360 8090 0 60 ~ 12 +C132 +Text Notes 2360 8290 0 60 ~ 12 +4.7uF +Text Notes 2860 8090 0 60 ~ 12 +C136 +Text Notes 2860 8290 0 60 ~ 12 +4.7uF +Text Notes 3360 8090 0 60 ~ 12 +C139 +Text Notes 3360 8290 0 60 ~ 12 +4.7uF +Text Notes 3060 4690 0 60 ~ 12 +C137 +Text Notes 3060 4890 0 60 ~ 12 +47uF +Text Notes 1660 8090 0 60 ~ 12 +C126 +Text Notes 1660 8290 0 60 ~ 12 +47uF +$Comp +L power:GND GND_134 +U 1 1 58023EDD +P 1300 5000 +F 0 "GND_134" H 1300 5000 20 0000 C CNN +F 1 "+GND" H 1300 4930 30 0000 C CNN +F 2 "" H 1300 5000 70 0000 C CNN +F 3 "" H 1300 5000 70 0000 C CNN + 1 1300 5000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_135 +U 1 1 58023EDC +P 1800 5000 +F 0 "GND_135" H 1800 5000 20 0000 C CNN +F 1 "+GND" H 1800 4930 30 0000 C CNN +F 2 "" H 1800 5000 70 0000 C CNN +F 3 "" H 1800 5000 70 0000 C CNN + 1 1800 5000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_136 +U 1 1 58023EDB +P 3700 5900 +F 0 "GND_136" H 3700 5900 20 0000 C CNN +F 1 "+GND" H 3700 5830 30 0000 C CNN +F 2 "" H 3700 5900 70 0000 C CNN +F 3 "" H 3700 5900 70 0000 C CNN + 1 3700 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_137 +U 1 1 58023EDA +P 4200 5900 +F 0 "GND_137" H 4200 5900 20 0000 C CNN +F 1 "+GND" H 4200 5830 30 0000 C CNN +F 2 "" H 4200 5900 70 0000 C CNN +F 3 "" H 4200 5900 70 0000 C CNN + 1 4200 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_138 +U 1 1 58023ED9 +P 4700 5900 +F 0 "GND_138" H 4700 5900 20 0000 C CNN +F 1 "+GND" H 4700 5830 30 0000 C CNN +F 2 "" H 4700 5900 70 0000 C CNN +F 3 "" H 4700 5900 70 0000 C CNN + 1 4700 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_139 +U 1 1 58023ED8 +P 5200 5900 +F 0 "GND_139" H 5200 5900 20 0000 C CNN +F 1 "+GND" H 5200 5830 30 0000 C CNN +F 2 "" H 5200 5900 70 0000 C CNN +F 3 "" H 5200 5900 70 0000 C CNN + 1 5200 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_140 +U 1 1 58023ED7 +P 5700 5900 +F 0 "GND_140" H 5700 5900 20 0000 C CNN +F 1 "+GND" H 5700 5830 30 0000 C CNN +F 2 "" H 5700 5900 70 0000 C CNN +F 3 "" H 5700 5900 70 0000 C CNN + 1 5700 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_141 +U 1 1 58023ED6 +P 6200 5900 +F 0 "GND_141" H 6200 5900 20 0000 C CNN +F 1 "+GND" H 6200 5830 30 0000 C CNN +F 2 "" H 6200 5900 70 0000 C CNN +F 3 "" H 6200 5900 70 0000 C CNN + 1 6200 5900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_142 +U 1 1 58023ED5 +P 3700 5000 +F 0 "GND_142" H 3700 5000 20 0000 C CNN +F 1 "+GND" H 3700 4930 30 0000 C CNN +F 2 "" H 3700 5000 70 0000 C CNN +F 3 "" H 3700 5000 70 0000 C CNN + 1 3700 5000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_143 +U 1 1 58023ED4 +P 4200 5000 +F 0 "GND_143" H 4200 5000 20 0000 C CNN +F 1 "+GND" H 4200 4930 30 0000 C CNN +F 2 "" H 4200 5000 70 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~ 1800 6300 +Connection ~ 2300 6300 +Connection ~ 6300 6300 +Connection ~ 6800 6300 +Connection ~ 2800 6300 +Connection ~ 3300 6300 +Connection ~ 3800 6300 +Connection ~ 4300 6300 +Connection ~ 4800 6300 +Connection ~ 5300 6300 +Connection ~ 5800 6300 +Connection ~ 1300 4500 +$Comp +L Cryptech_Alpha:C-EUC0603 C140 +U 1 1 58023EB1 +P 3700 4700 +F 0 "C140" H 3780 4510 60 0000 L BNN + 1 3700 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3780 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C135 +U 1 1 58023EB0 +P 2800 6500 +F 0 "C135" H 2880 6310 60 0000 L BNN + 1 2800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C138 +U 1 1 58023EAF +P 3300 6500 +F 0 "C138" H 3380 6310 60 0000 L BNN + 1 3300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C142 +U 1 1 58023EAE +P 3800 6500 +F 0 "C142" H 3880 6310 60 0000 L BNN + 1 3800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C146 +U 1 1 58023EAD +P 4300 6500 +F 0 "C146" H 4380 6310 60 0000 L BNN + 1 4300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C150 +U 1 1 58023EAC +P 4800 6500 +F 0 "C150" H 4880 6310 60 0000 L BNN + 1 4800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C154 +U 1 1 58023EAB +P 5300 6500 +F 0 "C154" H 5380 6310 60 0000 L BNN + 1 5300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C158 +U 1 1 58023EAA +P 5800 6500 +F 0 "C158" H 5880 6310 60 0000 L BNN + 1 5800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C162 +U 1 1 58023EA9 +P 6300 6500 +F 0 "C162" H 6380 6310 60 0000 L BNN + 1 6300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C163 +U 1 1 58023EA8 +P 6800 6500 +F 0 "C163" H 6880 6310 60 0000 L BNN + 1 6800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C143 +U 1 1 58023EA7 +P 4000 8100 +F 0 "C143" H 4080 7910 60 0000 L BNN + 1 4000 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4080 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C125 +U 1 1 58023EA6 +P 1300 6500 +F 0 "C125" H 1380 6310 60 0000 L BNN + 1 1300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 1380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C147 +U 1 1 58023EA5 +P 4500 8100 +F 0 "C147" H 4580 7910 60 0000 L BNN + 1 4500 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4580 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C151 +U 1 1 58023EA4 +P 5000 8100 +F 0 "C151" H 5080 7910 60 0000 L BNN + 1 5000 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5080 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C155 +U 1 1 58023EA3 +P 5500 8100 +F 0 "C155" H 5580 7910 60 0000 L BNN + 1 5500 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5580 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C159 +U 1 1 58023EA2 +P 6000 8100 +F 0 "C159" H 6080 7910 60 0000 L BNN + 1 6000 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6080 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C164 +U 1 1 58023EA1 +P 7300 6500 +F 0 "C164" H 7380 6310 60 0000 L BNN + 1 7300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7380 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C144 +U 1 1 58023EA0 +P 4200 4700 +F 0 "C144" H 4280 4510 60 0000 L BNN + 1 4200 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4280 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C148 +U 1 1 58023E9F +P 4700 4700 +F 0 "C148" H 4780 4510 60 0000 L BNN + 1 4700 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4780 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C152 +U 1 1 58023E9E +P 5200 4700 +F 0 "C152" H 5280 4510 60 0000 L BNN + 1 5200 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 5280 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C156 +U 1 1 58023E9D +P 5700 4700 +F 0 "C156" H 5780 4510 60 0000 L BNN + 1 5700 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 5780 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C160 +U 1 1 58023E9C +P 6200 4700 +F 0 "C160" H 6280 4510 60 0000 L BNN + 1 6200 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 6280 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C133 +U 1 1 58023E9B +P 2500 4700 +F 0 "C133" H 2580 4510 60 0000 L BNN + 1 2500 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 2580 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C141 +U 1 1 58023E9A +P 3700 5600 +F 0 "C141" H 3780 5410 60 0000 L BNN + 1 3700 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3780 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C145 +U 1 1 58023E99 +P 4200 5600 +F 0 "C145" H 4280 5410 60 0000 L BNN + 1 4200 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4280 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C149 +U 1 1 58023E98 +P 4700 5600 +F 0 "C149" H 4780 5410 60 0000 L BNN + 1 4700 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 4780 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C153 +U 1 1 58023E97 +P 5200 5600 +F 0 "C153" H 5280 5410 60 0000 L BNN + 1 5200 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 5280 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C157 +U 1 1 58023E96 +P 5700 5600 +F 0 "C157" H 5780 5410 60 0000 L BNN + 1 5700 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 5780 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C161 +U 1 1 58023E95 +P 6200 5600 +F 0 "C161" H 6280 5410 60 0000 L BNN + 1 6200 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 6280 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C132 +U 1 1 58023E94 +P 2300 8100 +F 0 "C132" H 2380 7910 60 0000 L BNN + 1 2300 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 2380 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C136 +U 1 1 58023E93 +P 2800 8100 +F 0 "C136" H 2880 7910 60 0000 L BNN + 1 2800 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 2880 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C139 +U 1 1 58023E92 +P 3300 8100 +F 0 "C139" H 3380 7910 60 0000 L BNN + 1 3300 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3380 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C137 +U 1 1 58023E91 +P 3000 4700 +F 0 "C137" H 3080 4510 60 0000 L BNN + 1 3000 4700 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 3080 4510 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C124 +U 1 1 58023E90 +P 1300 5600 +F 0 "C124" H 1380 5410 60 0000 L BNN + 1 1300 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 1380 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C126 +U 1 1 58023E8F +P 1600 8100 +F 0 "C126" H 1680 7910 60 0000 L BNN + 1 1600 8100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1680 7910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:CP_E-035X080 C123 +U 1 1 58023E8E +P 1300 4790 +F 0 "C123" V 1325 4665 60 0000 R TNN +F 1 "330uF" V 1210 4697 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_D" H 1210 4697 60 0001 C CNN +F 3 "" H 1210 4697 60 0000 C CNN + 1 1300 4790 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:CP_E-035X080 C127 +U 1 1 58023E8D +P 1800 4790 +F 0 "C127" V 1825 4665 60 0000 R TNN +F 1 "330uF" V 1710 4697 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:C_D" H 1710 4697 60 0001 C CNN +F 3 "" H 1710 4697 60 0000 C CNN + 1 1800 4790 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C128 +U 1 1 58023E8C +P 1800 5600 +F 0 "C128" H 1880 5410 60 0000 L BNN + 1 1800 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 1880 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C130 +U 1 1 58023E8B +P 2300 5600 +F 0 "C130" H 2380 5410 60 0000 L BNN + 1 2300 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2380 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C134 +U 1 1 58023E8A +P 2800 5600 +F 0 "C134" H 2880 5410 60 0000 L BNN + 1 2800 5600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2880 5410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C129 +U 1 1 58023E89 +P 1800 6500 +F 0 "C129" H 1880 6310 60 0000 L BNN + 1 1800 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 1880 6310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C131 +U 1 1 58023E88 +P 2300 6500 +F 0 "C131" H 2380 6310 60 0000 L BNN + 1 2300 6500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2380 6310 60 0001 C CNN +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_23.sch b/KiCAD/rev02_23.sch new file mode 100644 index 0000000..4759fe6 --- /dev/null +++ b/KiCAD/rev02_23.sch @@ -0,0 +1,1286 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 25 27 +Title "rev02_23" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6600 5000 0 60 ~ 12 +<-- Place small 0.47 uF caps right under the BGA package\n<-- Place medium 4.7 uF caps very close to the BGA package\n<-- Place large 47 uF caps not far from the BGA package\n<-- Place one of four 47 uF caps on every side of the BGA p.\n<-- Distribute six sets of caps among six FPGA I/O banks +Text Notes 2500 4100 0 60 ~ 12 +*) Decoupling capacitors for VCCO +Text Notes 8490 10200 0 54 ~ 12 +FPGA VCCO bypass capacitors +Text Notes 4660 4590 0 60 ~ 12 +C181 +Text Notes 4660 4790 0 60 ~ 12 +0.47uF +Text Notes 5160 4590 0 60 ~ 12 +C187 +Text Notes 5160 4790 0 60 ~ 12 +0.47uF +Text Notes 5660 4590 0 60 ~ 12 +C193 +Text Notes 5660 4790 0 60 ~ 12 +0.47uF +Text Notes 6160 4590 0 60 ~ 12 +C199 +Text Notes 6160 4790 0 60 ~ 12 +0.47uF +Text Notes 4660 5490 0 60 ~ 12 +C182 +Text Notes 4660 5690 0 60 ~ 12 +0.47uF +Text Notes 5160 5490 0 60 ~ 12 +C188 +Text Notes 5160 5690 0 60 ~ 12 +0.47uF +Text Notes 5660 5490 0 60 ~ 12 +C194 +Text Notes 5660 5690 0 60 ~ 12 +0.47uF +Text Notes 6160 5490 0 60 ~ 12 +C200 +Text Notes 6160 5690 0 60 ~ 12 +0.47uF +Text Notes 4660 6390 0 60 ~ 12 +C183 +Text Notes 4660 6590 0 60 ~ 12 +0.47uF +Text Notes 5160 6390 0 60 ~ 12 +C189 +Text Notes 5160 6590 0 60 ~ 12 +0.47uF +Text Notes 5660 6390 0 60 ~ 12 +C195 +Text Notes 5660 6590 0 60 ~ 12 +0.47uF +Text Notes 6160 6390 0 60 ~ 12 +C201 +Text Notes 6160 6590 0 60 ~ 12 +0.47uF +Text Notes 4660 7290 0 60 ~ 12 +C184 +Text Notes 4660 7490 0 60 ~ 12 +0.47uF +Text Notes 5160 7290 0 60 ~ 12 +C190 +Text Notes 5160 7490 0 60 ~ 12 +0.47uF +Text Notes 5660 7290 0 60 ~ 12 +C196 +Text Notes 5660 7490 0 60 ~ 12 +0.47uF +Text Notes 6160 7290 0 60 ~ 12 +C202 +Text Notes 6160 7490 0 60 ~ 12 +0.47uF +Text Notes 4660 8190 0 60 ~ 12 +C185 +Text Notes 4660 8390 0 60 ~ 12 +0.47uF +Text Notes 5160 8190 0 60 ~ 12 +C191 +Text Notes 5160 8390 0 60 ~ 12 +0.47uF +Text Notes 5660 8190 0 60 ~ 12 +C197 +Text Notes 5660 8390 0 60 ~ 12 +0.47uF +Text Notes 6160 8190 0 60 ~ 12 +C203 +Text Notes 6160 8390 0 60 ~ 12 +0.47uF +Text Notes 4660 9090 0 60 ~ 12 +C186 +Text Notes 4660 9290 0 60 ~ 12 +0.47uF +Text Notes 5160 9090 0 60 ~ 12 +C192 +Text Notes 5160 9290 0 60 ~ 12 +0.47uF +Text Notes 5660 9090 0 60 ~ 12 +C198 +Text Notes 5660 9290 0 60 ~ 12 +0.47uF +Text Notes 6160 9090 0 60 ~ 12 +C204 +Text Notes 6160 9290 0 60 ~ 12 +0.47uF +Text Notes 3460 4590 0 60 ~ 12 +C169 +Text Notes 3460 4790 0 60 ~ 12 +4.7uF +Text Notes 3960 4590 0 60 ~ 12 +C175 +Text Notes 3960 4790 0 60 ~ 12 +4.7uF +Text Notes 3960 5490 0 60 ~ 12 +C176 +Text Notes 3960 5690 0 60 ~ 12 +4.7uF +Text Notes 3460 5490 0 60 ~ 12 +C170 +Text Notes 3460 5690 0 60 ~ 12 +4.7uF +Text Notes 3460 6390 0 60 ~ 12 +C171 +Text Notes 3460 6590 0 60 ~ 12 +4.7uF +Text Notes 3960 6390 0 60 ~ 12 +C177 +Text Notes 3960 6590 0 60 ~ 12 +4.7uF +Text Notes 3960 7290 0 60 ~ 12 +C178 +Text Notes 3960 7490 0 60 ~ 12 +4.7uF +Text Notes 3460 7290 0 60 ~ 12 +C172 +Text Notes 3460 7490 0 60 ~ 12 +4.7uF +Text Notes 3460 8190 0 60 ~ 12 +C173 +Text Notes 3460 8390 0 60 ~ 12 +4.7uF +Text Notes 3960 8190 0 60 ~ 12 +C179 +Text Notes 3960 8390 0 60 ~ 12 +4.7uF +Text Notes 3960 9090 0 60 ~ 12 +C180 +Text Notes 3960 9290 0 60 ~ 12 +4.7uF +Text Notes 3460 9090 0 60 ~ 12 +C174 +Text Notes 3460 9290 0 60 ~ 12 +4.7uF +Text Notes 1060 4590 0 60 ~ 12 +C165 +Text Notes 1060 4790 0 60 ~ 12 +47uF +Text Notes 1560 4590 0 60 ~ 12 +C166 +Text Notes 1560 4790 0 60 ~ 12 +47uF +Text Notes 2060 4590 0 60 ~ 12 +C167 +Text Notes 2060 4790 0 60 ~ 12 +47uF +Text Notes 2560 4590 0 60 ~ 12 +C168 +Text Notes 2560 4790 0 60 ~ 12 +47uF +$Comp +L power:GND GND_176 +U 1 1 58023E87 +P 1000 4900 +F 0 "GND_176" H 1000 4900 20 0000 C CNN +F 1 "+GND" H 1000 4830 30 0000 C CNN +F 2 "" H 1000 4900 70 0000 C CNN +F 3 "" H 1000 4900 70 0000 C CNN + 1 1000 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_177 +U 1 1 58023E86 +P 1500 4900 +F 0 "GND_177" H 1500 4900 20 0000 C CNN +F 1 "+GND" H 1500 4830 30 0000 C CNN +F 2 "" H 1500 4900 70 0000 C CNN +F 3 "" H 1500 4900 70 0000 C CNN + 1 1500 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_178 +U 1 1 58023E85 +P 2000 4900 +F 0 "GND_178" H 2000 4900 20 0000 C CNN +F 1 "+GND" H 2000 4830 30 0000 C CNN +F 2 "" H 2000 4900 70 0000 C CNN +F 3 "" H 2000 4900 70 0000 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_179 +U 1 1 58023E84 +P 2500 4900 +F 0 "GND_179" H 2500 4900 20 0000 C CNN +F 1 "+GND" H 2500 4830 30 0000 C CNN +F 2 "" H 2500 4900 70 0000 C CNN +F 3 "" H 2500 4900 70 0000 C CNN + 1 2500 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_180 +U 1 1 58023E83 +P 3400 4900 +F 0 "GND_180" H 3400 4900 20 0000 C CNN +F 1 "+GND" H 3400 4830 30 0000 C CNN +F 2 "" H 3400 4900 70 0000 C CNN +F 3 "" H 3400 4900 70 0000 C CNN + 1 3400 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_181 +U 1 1 58023E82 +P 3900 4900 +F 0 "GND_181" H 3900 4900 20 0000 C CNN +F 1 "+GND" H 3900 4830 30 0000 C CNN +F 2 "" H 3900 4900 70 0000 C CNN +F 3 "" H 3900 4900 70 0000 C CNN + 1 3900 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_182 +U 1 1 58023E81 +P 4600 4900 +F 0 "GND_182" H 4600 4900 20 0000 C CNN +F 1 "+GND" H 4600 4830 30 0000 C CNN +F 2 "" H 4600 4900 70 0000 C CNN +F 3 "" H 4600 4900 70 0000 C CNN + 1 4600 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_183 +U 1 1 58023E80 +P 5100 4900 +F 0 "GND_183" H 5100 4900 20 0000 C CNN +F 1 "+GND" H 5100 4830 30 0000 C CNN +F 2 "" H 5100 4900 70 0000 C CNN +F 3 "" H 5100 4900 70 0000 C CNN + 1 5100 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_184 +U 1 1 58023E7F +P 5600 4900 +F 0 "GND_184" H 5600 4900 20 0000 C CNN +F 1 "+GND" H 5600 4830 30 0000 C CNN +F 2 "" H 5600 4900 70 0000 C CNN +F 3 "" H 5600 4900 70 0000 C CNN + 1 5600 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_185 +U 1 1 58023E7E +P 6100 4900 +F 0 "GND_185" H 6100 4900 20 0000 C CNN +F 1 "+GND" H 6100 4830 30 0000 C CNN +F 2 "" H 6100 4900 70 0000 C CNN +F 3 "" H 6100 4900 70 0000 C CNN + 1 6100 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_186 +U 1 1 58023E7D +P 3400 5800 +F 0 "GND_186" H 3400 5800 20 0000 C CNN +F 1 "+GND" H 3400 5730 30 0000 C CNN +F 2 "" H 3400 5800 70 0000 C CNN +F 3 "" H 3400 5800 70 0000 C CNN + 1 3400 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_187 +U 1 1 58023E7C +P 3900 5800 +F 0 "GND_187" H 3900 5800 20 0000 C CNN +F 1 "+GND" H 3900 5730 30 0000 C CNN +F 2 "" H 3900 5800 70 0000 C CNN +F 3 "" H 3900 5800 70 0000 C CNN + 1 3900 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_188 +U 1 1 58023E7B +P 4600 5800 +F 0 "GND_188" H 4600 5800 20 0000 C CNN +F 1 "+GND" H 4600 5730 30 0000 C CNN +F 2 "" H 4600 5800 70 0000 C CNN +F 3 "" H 4600 5800 70 0000 C CNN + 1 4600 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_189 +U 1 1 58023E7A +P 5100 5800 +F 0 "GND_189" H 5100 5800 20 0000 C CNN +F 1 "+GND" H 5100 5730 30 0000 C CNN +F 2 "" H 5100 5800 70 0000 C CNN +F 3 "" H 5100 5800 70 0000 C CNN + 1 5100 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_190 +U 1 1 58023E79 +P 5600 5800 +F 0 "GND_190" H 5600 5800 20 0000 C CNN +F 1 "+GND" H 5600 5730 30 0000 C CNN +F 2 "" H 5600 5800 70 0000 C CNN +F 3 "" H 5600 5800 70 0000 C CNN + 1 5600 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_191 +U 1 1 58023E78 +P 6100 5800 +F 0 "GND_191" H 6100 5800 20 0000 C CNN +F 1 "+GND" H 6100 5730 30 0000 C CNN +F 2 "" H 6100 5800 70 0000 C CNN +F 3 "" H 6100 5800 70 0000 C CNN + 1 6100 5800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_192 +U 1 1 58023E77 +P 3400 6700 +F 0 "GND_192" H 3400 6700 20 0000 C CNN +F 1 "+GND" H 3400 6630 30 0000 C CNN +F 2 "" H 3400 6700 70 0000 C CNN +F 3 "" H 3400 6700 70 0000 C CNN + 1 3400 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_193 +U 1 1 58023E76 +P 3900 6700 +F 0 "GND_193" H 3900 6700 20 0000 C CNN +F 1 "+GND" H 3900 6630 30 0000 C CNN +F 2 "" H 3900 6700 70 0000 C CNN +F 3 "" H 3900 6700 70 0000 C CNN + 1 3900 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_194 +U 1 1 58023E75 +P 4600 6700 +F 0 "GND_194" H 4600 6700 20 0000 C CNN +F 1 "+GND" H 4600 6630 30 0000 C CNN +F 2 "" H 4600 6700 70 0000 C CNN +F 3 "" H 4600 6700 70 0000 C CNN + 1 4600 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_195 +U 1 1 58023E74 +P 5100 6700 +F 0 "GND_195" H 5100 6700 20 0000 C CNN +F 1 "+GND" H 5100 6630 30 0000 C CNN +F 2 "" H 5100 6700 70 0000 C CNN +F 3 "" H 5100 6700 70 0000 C CNN + 1 5100 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_196 +U 1 1 58023E73 +P 5600 6700 +F 0 "GND_196" H 5600 6700 20 0000 C CNN +F 1 "+GND" H 5600 6630 30 0000 C CNN +F 2 "" H 5600 6700 70 0000 C CNN +F 3 "" H 5600 6700 70 0000 C CNN + 1 5600 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_197 +U 1 1 58023E72 +P 6100 6700 +F 0 "GND_197" H 6100 6700 20 0000 C CNN +F 1 "+GND" H 6100 6630 30 0000 C CNN +F 2 "" H 6100 6700 70 0000 C CNN +F 3 "" H 6100 6700 70 0000 C CNN + 1 6100 6700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_198 +U 1 1 58023E71 +P 3400 7600 +F 0 "GND_198" H 3400 7600 20 0000 C CNN +F 1 "+GND" H 3400 7530 30 0000 C CNN +F 2 "" H 3400 7600 70 0000 C CNN +F 3 "" H 3400 7600 70 0000 C CNN + 1 3400 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_199 +U 1 1 58023E70 +P 3900 7600 +F 0 "GND_199" H 3900 7600 20 0000 C CNN +F 1 "+GND" H 3900 7530 30 0000 C CNN +F 2 "" H 3900 7600 70 0000 C CNN +F 3 "" H 3900 7600 70 0000 C CNN + 1 3900 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_200 +U 1 1 58023E6F +P 4600 7600 +F 0 "GND_200" H 4600 7600 20 0000 C CNN +F 1 "+GND" H 4600 7530 30 0000 C CNN +F 2 "" H 4600 7600 70 0000 C CNN +F 3 "" H 4600 7600 70 0000 C CNN + 1 4600 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_201 +U 1 1 58023E6E +P 5100 7600 +F 0 "GND_201" H 5100 7600 20 0000 C CNN +F 1 "+GND" H 5100 7530 30 0000 C CNN +F 2 "" H 5100 7600 70 0000 C CNN +F 3 "" H 5100 7600 70 0000 C CNN + 1 5100 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_202 +U 1 1 58023E6D +P 5600 7600 +F 0 "GND_202" H 5600 7600 20 0000 C CNN +F 1 "+GND" H 5600 7530 30 0000 C CNN +F 2 "" H 5600 7600 70 0000 C CNN +F 3 "" H 5600 7600 70 0000 C CNN + 1 5600 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_203 +U 1 1 58023E6C +P 6100 7600 +F 0 "GND_203" H 6100 7600 20 0000 C CNN +F 1 "+GND" H 6100 7530 30 0000 C CNN +F 2 "" H 6100 7600 70 0000 C CNN +F 3 "" H 6100 7600 70 0000 C CNN + 1 6100 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_204 +U 1 1 58023E6B +P 3400 8500 +F 0 "GND_204" H 3400 8500 20 0000 C CNN +F 1 "+GND" H 3400 8430 30 0000 C CNN +F 2 "" H 3400 8500 70 0000 C CNN +F 3 "" H 3400 8500 70 0000 C CNN + 1 3400 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_205 +U 1 1 58023E6A +P 3900 8500 +F 0 "GND_205" H 3900 8500 20 0000 C CNN +F 1 "+GND" H 3900 8430 30 0000 C CNN +F 2 "" H 3900 8500 70 0000 C CNN +F 3 "" H 3900 8500 70 0000 C CNN + 1 3900 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_206 +U 1 1 58023E69 +P 4600 8500 +F 0 "GND_206" H 4600 8500 20 0000 C CNN +F 1 "+GND" H 4600 8430 30 0000 C CNN +F 2 "" H 4600 8500 70 0000 C CNN +F 3 "" H 4600 8500 70 0000 C CNN + 1 4600 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_207 +U 1 1 58023E68 +P 5100 8500 +F 0 "GND_207" H 5100 8500 20 0000 C CNN +F 1 "+GND" H 5100 8430 30 0000 C CNN +F 2 "" H 5100 8500 70 0000 C CNN +F 3 "" H 5100 8500 70 0000 C CNN + 1 5100 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_208 +U 1 1 58023E67 +P 5600 8500 +F 0 "GND_208" H 5600 8500 20 0000 C CNN +F 1 "+GND" H 5600 8430 30 0000 C CNN +F 2 "" H 5600 8500 70 0000 C CNN +F 3 "" H 5600 8500 70 0000 C CNN + 1 5600 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_209 +U 1 1 58023E66 +P 6100 8500 +F 0 "GND_209" H 6100 8500 20 0000 C CNN +F 1 "+GND" H 6100 8430 30 0000 C CNN +F 2 "" H 6100 8500 70 0000 C CNN +F 3 "" H 6100 8500 70 0000 C CNN + 1 6100 8500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_210 +U 1 1 58023E65 +P 3400 9400 +F 0 "GND_210" H 3400 9400 20 0000 C CNN +F 1 "+GND" H 3400 9330 30 0000 C CNN +F 2 "" H 3400 9400 70 0000 C CNN +F 3 "" H 3400 9400 70 0000 C CNN + 1 3400 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_211 +U 1 1 58023E64 +P 3900 9400 +F 0 "GND_211" H 3900 9400 20 0000 C CNN +F 1 "+GND" H 3900 9330 30 0000 C CNN +F 2 "" H 3900 9400 70 0000 C CNN +F 3 "" H 3900 9400 70 0000 C CNN + 1 3900 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_212 +U 1 1 58023E63 +P 4600 9400 +F 0 "GND_212" H 4600 9400 20 0000 C CNN +F 1 "+GND" H 4600 9330 30 0000 C CNN +F 2 "" H 4600 9400 70 0000 C CNN +F 3 "" H 4600 9400 70 0000 C CNN + 1 4600 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_213 +U 1 1 58023E62 +P 5100 9400 +F 0 "GND_213" H 5100 9400 20 0000 C CNN +F 1 "+GND" H 5100 9330 30 0000 C CNN +F 2 "" H 5100 9400 70 0000 C CNN +F 3 "" H 5100 9400 70 0000 C CNN + 1 5100 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_214 +U 1 1 58023E61 +P 5600 9400 +F 0 "GND_214" H 5600 9400 20 0000 C CNN +F 1 "+GND" H 5600 9330 30 0000 C CNN +F 2 "" H 5600 9400 70 0000 C CNN +F 3 "" H 5600 9400 70 0000 C CNN + 1 5600 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_215 +U 1 1 58023E60 +P 6100 9400 +F 0 "GND_215" H 6100 9400 20 0000 C CNN +F 1 "+GND" H 6100 9330 30 0000 C CNN +F 2 "" H 6100 9400 70 0000 C CNN +F 3 "" H 6100 9400 70 0000 C CNN + 1 6100 9400 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_39 +U 1 1 58023E5F +P 600 4200 +F 0 "VCCO_3V3_39" H 600 4200 20 0000 C CNN +F 1 "+VCCO_3V3" H 600 4130 30 0000 C CNN +F 2 "" H 600 4200 70 0000 C CNN +F 3 "" H 600 4200 70 0000 C CNN + 1 600 4200 + 1 0 0 -1 +$EndComp +Wire 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2500 4400 +Connection ~ 3400 4400 +Connection ~ 3900 4400 +Connection ~ 4600 4400 +Connection ~ 5100 4400 +Connection ~ 5600 4400 +Connection ~ 3000 4400 +Connection ~ 3900 5300 +Connection ~ 4600 5300 +Connection ~ 5100 5300 +Connection ~ 5600 5300 +Connection ~ 3400 5300 +Connection ~ 3000 5300 +Connection ~ 3900 7100 +Connection ~ 4600 7100 +Connection ~ 5100 7100 +Connection ~ 5600 7100 +Connection ~ 3400 7100 +Connection ~ 3000 6200 +Connection ~ 3900 8000 +Connection ~ 4600 8000 +Connection ~ 5100 8000 +Connection ~ 5600 8000 +Connection ~ 3400 8000 +Connection ~ 3000 7100 +Connection ~ 3900 8900 +Connection ~ 4600 8900 +Connection ~ 5100 8900 +Connection ~ 5600 8900 +Connection ~ 3400 8900 +Connection ~ 3000 8000 +Connection ~ 1000 4400 +$Comp +L Cryptech_Alpha:C-EUC0402 C181 +U 1 1 58023E5E +P 4600 4600 +F 0 "C181" H 4680 4410 60 0000 L BNN + 1 4600 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C189 +U 1 1 58023E5D +P 5100 6400 +F 0 "C189" H 5180 6210 60 0000 L BNN + 1 5100 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C195 +U 1 1 58023E5C +P 5600 6400 +F 0 "C195" H 5680 6210 60 0000 L BNN + 1 5600 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C201 +U 1 1 58023E5B +P 6100 6400 +F 0 "C201" H 6180 6210 60 0000 L BNN + 1 6100 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C184 +U 1 1 58023E5A +P 4600 7300 +F 0 "C184" H 4680 7110 60 0000 L BNN + 1 4600 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C190 +U 1 1 58023E59 +P 5100 7300 +F 0 "C190" H 5180 7110 60 0000 L BNN + 1 5100 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C196 +U 1 1 58023E58 +P 5600 7300 +F 0 "C196" H 5680 7110 60 0000 L BNN + 1 5600 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C202 +U 1 1 58023E57 +P 6100 7300 +F 0 "C202" H 6180 7110 60 0000 L BNN + 1 6100 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C185 +U 1 1 58023E56 +P 4600 8200 +F 0 "C185" H 4680 8010 60 0000 L BNN + 1 4600 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C191 +U 1 1 58023E55 +P 5100 8200 +F 0 "C191" H 5180 8010 60 0000 L BNN + 1 5100 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C197 +U 1 1 58023E54 +P 5600 8200 +F 0 "C197" H 5680 8010 60 0000 L BNN + 1 5600 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C187 +U 1 1 58023E53 +P 5100 4600 +F 0 "C187" H 5180 4410 60 0000 L BNN + 1 5100 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C203 +U 1 1 58023E52 +P 6100 8200 +F 0 "C203" H 6180 8010 60 0000 L BNN + 1 6100 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C186 +U 1 1 58023E51 +P 4600 9100 +F 0 "C186" H 4680 8910 60 0000 L BNN + 1 4600 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C192 +U 1 1 58023E50 +P 5100 9100 +F 0 "C192" H 5180 8910 60 0000 L BNN + 1 5100 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C198 +U 1 1 58023E4F +P 5600 9100 +F 0 "C198" H 5680 8910 60 0000 L BNN + 1 5600 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C204 +U 1 1 58023E4E +P 6100 9100 +F 0 "C204" H 6180 8910 60 0000 L BNN + 1 6100 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C169 +U 1 1 58023E4D +P 3400 4600 +F 0 "C169" H 3480 4410 60 0000 L BNN + 1 3400 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C175 +U 1 1 58023E4C +P 3900 4600 +F 0 "C175" H 3980 4410 60 0000 L BNN + 1 3900 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C176 +U 1 1 58023E4B +P 3900 5500 +F 0 "C176" H 3980 5310 60 0000 L BNN + 1 3900 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C170 +U 1 1 58023E4A +P 3400 5500 +F 0 "C170" H 3480 5310 60 0000 L BNN + 1 3400 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C171 +U 1 1 58023E49 +P 3400 6400 +F 0 "C171" H 3480 6210 60 0000 L BNN + 1 3400 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C193 +U 1 1 58023E48 +P 5600 4600 +F 0 "C193" H 5680 4410 60 0000 L BNN + 1 5600 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C177 +U 1 1 58023E47 +P 3900 6400 +F 0 "C177" H 3980 6210 60 0000 L BNN + 1 3900 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 6210 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C178 +U 1 1 58023E46 +P 3900 7300 +F 0 "C178" H 3980 7110 60 0000 L BNN + 1 3900 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C172 +U 1 1 58023E45 +P 3400 7300 +F 0 "C172" H 3480 7110 60 0000 L BNN + 1 3400 7300 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 7110 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C173 +U 1 1 58023E44 +P 3400 8200 +F 0 "C173" H 3480 8010 60 0000 L BNN + 1 3400 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C179 +U 1 1 58023E43 +P 3900 8200 +F 0 "C179" H 3980 8010 60 0000 L BNN + 1 3900 8200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 8010 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C180 +U 1 1 58023E42 +P 3900 9100 +F 0 "C180" H 3980 8910 60 0000 L BNN + 1 3900 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3980 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0603 C174 +U 1 1 58023E41 +P 3400 9100 +F 0 "C174" H 3480 8910 60 0000 L BNN + 1 3400 9100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0805" H 3480 8910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C165 +U 1 1 58023E40 +P 1000 4600 +F 0 "C165" H 1080 4410 60 0000 L BNN + 1 1000 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1080 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C166 +U 1 1 58023E3F +P 1500 4600 +F 0 "C166" H 1580 4410 60 0000 L BNN + 1 1500 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1580 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C167 +U 1 1 58023E3E +P 2000 4600 +F 0 "C167" H 2080 4410 60 0000 L BNN + 1 2000 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 2080 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C199 +U 1 1 58023E3D +P 6100 4600 +F 0 "C199" H 6180 4410 60 0000 L BNN + 1 6100 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C168 +U 1 1 58023E3C +P 2500 4600 +F 0 "C168" H 2580 4410 60 0000 L BNN + 1 2500 4600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 2580 4410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C182 +U 1 1 58023E3B +P 4600 5500 +F 0 "C182" H 4680 5310 60 0000 L BNN + 1 4600 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C188 +U 1 1 58023E3A +P 5100 5500 +F 0 "C188" H 5180 5310 60 0000 L BNN + 1 5100 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5180 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C194 +U 1 1 58023E39 +P 5600 5500 +F 0 "C194" H 5680 5310 60 0000 L BNN + 1 5600 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 5680 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C200 +U 1 1 58023E38 +P 6100 5500 +F 0 "C200" H 6180 5310 60 0000 L BNN + 1 6100 5500 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6180 5310 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C183 +U 1 1 58023E37 +P 4600 6400 +F 0 "C183" H 4680 6210 60 0000 L BNN + 1 4600 6400 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 4680 6210 60 0001 C CNN +$EndComp +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_24.sch b/KiCAD/rev02_24.sch new file mode 100644 index 0000000..91eea7f --- /dev/null +++ b/KiCAD/rev02_24.sch @@ -0,0 +1,493 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 26 27 +Title "rev02_24" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 4300 4100 0 60 ~ 12 +*) FPGA Power Subsystem -- CORE +Text Notes 7150 5310 0 60 ~ 12 +*) VCCINT = 0.6V x (1 + 150 / 226) = 0.998V\n*) OCP_ADJ is not used (default over-current threshold)\n*) MARx are not used (output at nominal 100%)\n*) S_IN/S_OUT are not used (single regulator mode)\n*) S_DELAY is not used (single regulator mode)\n*) M/S is not used (parallel operation not needed)\n*) EA_OUT is not used (default control loop)\n*) Minimal load current is 0A, but we still place\nload of 100 Ohms just in case (gives 10 mA) +Text Notes 8520 10200 0 54 ~ 12 +FPGA CORE voltage regulators +Text Notes 2870 6680 0 60 ~ 12 +R66 +Text Notes 1860 6590 0 60 ~ 12 +C205 +Text Notes 1860 6790 0 60 ~ 12 +22~uF +Text Notes 2260 6590 0 60 ~ 12 +C206 +Text Notes 2260 6790 0 60 ~ 12 +22~uF +Text Notes 5660 6630 0 60 ~ 12 +R68 +Text Notes 5650 7260 0 60 ~ 12 +R69 +Text Notes 6330 6590 0 60 ~ 12 +C208 +Text Notes 6330 6680 0 60 ~ 12 +27pF +Text Notes 7690 7090 0 60 ~ 12 +R70 +Text Notes 5260 7280 0 60 ~ 12 +R67 +Text Notes 6660 7090 0 60 ~ 12 +C209 +Text Notes 6660 7290 0 60 ~ 12 +47uF +Text Notes 7160 7090 0 60 ~ 12 +C210 +Text Notes 7160 7290 0 60 ~ 12 +47uF +$Comp +L power:GND GND_216 +U 1 1 58023E36 +P 4200 9500 +F 0 "GND_216" H 4200 9500 20 0000 C CNN +F 1 "+GND" H 4200 9430 30 0000 C CNN +F 2 "" H 4200 9500 70 0000 C CNN +F 3 "" H 4200 9500 70 0000 C CNN + 1 4200 9500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_217 +U 1 1 58023E35 +P 4700 9500 +F 0 "GND_217" H 4700 9500 20 0000 C CNN +F 1 "+GND" H 4700 9430 30 0000 C CNN +F 2 "" H 4700 9500 70 0000 C CNN +F 3 "" H 4700 9500 70 0000 C CNN + 1 4700 9500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_218 +U 1 1 58023E34 +P 3400 9500 +F 0 "GND_218" H 3400 9500 20 0000 C CNN +F 1 "+GND" H 3400 9430 30 0000 C CNN +F 2 "" H 3400 9500 70 0000 C CNN +F 3 "" H 3400 9500 70 0000 C CNN + 1 3400 9500 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_219 +U 1 1 58023E33 +P 1800 7000 +F 0 "GND_219" H 1800 7000 20 0000 C CNN +F 1 "+GND" H 1800 6930 30 0000 C CNN +F 2 "" H 1800 7000 70 0000 C CNN +F 3 "" H 1800 7000 70 0000 C CNN + 1 1800 7000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_220 +U 1 1 58023E32 +P 2200 7000 +F 0 "GND_220" H 2200 7000 20 0000 C CNN +F 1 "+GND" H 2200 6930 30 0000 C CNN +F 2 "" H 2200 7000 70 0000 C CNN +F 3 "" H 2200 7000 70 0000 C CNN + 1 2200 7000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_221 +U 1 1 58023E31 +P 5900 7600 +F 0 "GND_221" H 5900 7600 20 0000 C CNN +F 1 "+GND" H 5900 7530 30 0000 C CNN +F 2 "" H 5900 7600 70 0000 C CNN +F 3 "" H 5900 7600 70 0000 C CNN + 1 5900 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_222 +U 1 1 58023E30 +P 6600 7600 +F 0 "GND_222" H 6600 7600 20 0000 C CNN +F 1 "+GND" H 6600 7530 30 0000 C CNN +F 2 "" H 6600 7600 70 0000 C CNN +F 3 "" H 6600 7600 70 0000 C CNN + 1 6600 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_223 +U 1 1 58023E2F +P 7100 7600 +F 0 "GND_223" H 7100 7600 20 0000 C CNN +F 1 "+GND" H 7100 7530 30 0000 C CNN +F 2 "" H 7100 7600 70 0000 C CNN +F 3 "" H 7100 7600 70 0000 C CNN + 1 7100 7600 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_224 +U 1 1 58023E2E +P 7600 7600 +F 0 "GND_224" H 7600 7600 20 0000 C CNN +F 1 "+GND" H 7600 7530 30 0000 C CNN +F 2 "" H 7600 7600 70 0000 C CNN +F 3 "" H 7600 7600 70 0000 C CNN + 1 7600 7600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_3 +U 1 1 58023E2D +P 1600 6200 +F 0 "VCC_5V0_3" H 1600 6200 20 0000 C CNN +F 1 "+VCC_5V0" H 1600 6130 30 0000 C CNN +F 2 "" H 1600 6200 70 0000 C CNN +F 3 "" H 1600 6200 70 0000 C CNN + 1 1600 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 9400 3400 9500 +Wire Wire Line + 1800 6800 1800 7000 +Wire Wire Line + 2200 6800 2200 7000 +Wire Wire Line + 5900 7500 5900 7600 +Wire Wire Line + 6600 7300 6600 7600 +Wire Wire Line + 7100 7300 7100 7600 +Wire Wire Line + 7600 7400 7600 7600 +Wire Wire Line + 8300 6400 8100 6400 +Text Label 8300 6400 0 48 ~ 0 +FPGA_VCCINT_1V0 +Wire Wire Line + 1600 6200 1600 6400 +Wire Wire Line + 3400 6400 3400 6600 +Wire Wire Line + 3600 6400 3400 6400 +Wire Wire Line + 3600 6600 3400 6600 +Wire Wire Line + 3400 6400 2800 6400 +Wire Wire Line + 2800 6400 2200 6400 +Wire Wire Line + 2200 6400 1800 6400 +Wire Wire Line + 1800 6400 1800 6500 +Wire Wire Line + 2200 6400 2200 6500 +Wire Wire Line + 2800 6400 2800 6500 +Wire Wire Line + 1800 6400 1600 6400 +Connection ~ 3400 6400 +Connection ~ 2200 6400 +Connection ~ 2800 6400 +Connection ~ 1800 6400 +Wire Wire Line + 5600 9100 5300 9100 +Text GLabel 5600 9100 2 48 Output ~ 0 +POK_VCCINT +Wire Wire Line + 3600 9100 3400 9100 +Wire Wire Line + 3600 7000 2800 7000 +Wire Wire Line + 2800 6900 2800 7000 +Wire Wire Line + 3600 6800 3200 6800 +Wire Wire Line + 3200 5900 3200 6800 +Wire Wire Line + 3200 5900 2700 5900 +Text GLabel 2700 5900 0 48 Input ~ 0 +PWR_ENA_VCCINT +Wire Wire Line + 5500 7600 5300 7600 +Wire Wire Line + 5500 7500 5500 7600 +Wire Wire Line + 5500 6400 5500 7100 +Wire Wire Line + 5500 6400 5300 6400 +Wire Wire Line + 5900 6400 5500 6400 +Wire Wire Line + 5900 6400 5900 6500 +Wire Wire Line + 6200 6400 5900 6400 +Wire Wire Line + 6200 6400 6200 6500 +Wire Wire Line + 6600 6400 6600 7000 +Wire Wire Line + 6600 6400 6200 6400 +Wire Wire Line + 7100 6400 7100 7000 +Wire Wire Line + 7100 6400 6600 6400 +Wire Wire Line + 7600 6400 7600 7000 +Wire Wire Line + 7600 6400 7100 6400 +Wire Wire Line + 7700 6400 7600 6400 +Connection ~ 5500 6400 +Connection ~ 5900 6400 +Connection ~ 6200 6400 +Connection ~ 6600 6400 +Connection ~ 7100 6400 +Connection ~ 7600 6400 +Wire Wire Line + 5900 7000 5300 7000 +Wire Wire Line + 5900 6900 5900 7000 +Wire Wire Line + 5900 7000 5900 7100 +Wire Wire Line + 6200 7000 5900 7000 +Wire Wire Line + 6200 6800 6200 7000 +Connection ~ 5900 7000 +Text Notes 3900 5400 0 72 ~ 12 +U16 +Wire Wire Line + 3600 5600 3600 5500 +Wire Wire Line + 3600 5700 3600 5600 +Wire Wire Line + 3600 5800 3600 5700 +Wire Wire Line + 3600 5900 3600 5800 +Wire Wire Line + 3600 6000 3600 5900 +Wire Wire Line + 3600 6100 3600 6000 +Wire Wire Line + 3600 6200 3600 6100 +Wire Wire Line + 3600 6300 3600 6200 +Wire Wire Line + 3600 6400 3600 6300 +Wire Wire Line + 5300 5700 5300 5600 +Wire Wire Line + 5300 5800 5300 5700 +Wire Wire Line + 5300 5900 5300 5800 +Wire Wire Line + 5300 6000 5300 5900 +Wire Wire Line + 5300 6100 5300 6000 +Wire Wire Line + 5300 6200 5300 6100 +Wire Wire Line + 5300 6300 5300 6200 +Wire Wire Line + 5300 6400 5300 6300 +Text Notes 3110 9170 0 60 ~ 12 +C116 +Text Notes 2800 9370 0 60 ~ 12 +0.047~uF +Connection ~ 3600 6400 +Connection ~ 3600 6300 +Connection ~ 3600 6200 +Connection ~ 3600 6100 +Connection ~ 3600 6000 +Connection ~ 3600 5900 +Connection ~ 3600 5800 +Connection ~ 3600 5700 +Connection ~ 3600 5600 +Connection ~ 5300 6400 +Connection ~ 5300 6300 +Connection ~ 5300 6200 +Connection ~ 5300 6100 +Connection ~ 5300 6000 +Connection ~ 5300 5900 +Connection ~ 5300 5800 +Connection ~ 5300 5700 +$Comp +L Cryptech_Alpha:R-EU_R0402 R66 +U 1 1 58023E2C +P 2800 6700 +F 0 "R66" V 2710 6655 60 0000 R TNN +F 1 "4.7k" V 2730 6630 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 2730 6630 60 0001 C CNN +F 3 "" H 2730 6630 60 0000 C CNN + 1 2800 6700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C209 +U 1 1 58023E2B +P 6600 7100 +F 0 "C209" H 6680 6910 60 0000 L BNN + 1 6600 7100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 6680 6910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C210 +U 1 1 58023E2A +P 7100 7100 +F 0 "C210" H 7180 6910 60 0000 L BNN + 1 7100 7100 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 7180 6910 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:EN5364QI U16 +U 1 1 58023E29 +P 4400 7700 +F 0 "U16" H 3950 10020 60 0000 L BNN +F 1 "EN5364QI" H 4510 10030 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:QFN68" H 4510 10030 60 0001 C CNN +F 3 "" H 4510 10030 60 0000 C CNN + 1 4400 7700 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C207 +U 1 1 58023E28 +P 3400 9200 +F 0 "C207" H 2800 9150 60 0000 L BNN + 1 3400 9200 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2800 9150 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C205 +U 1 1 58023E27 +P 1800 6600 +F 0 "C205" H 1880 6410 60 0000 L BNN + 1 1800 6600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 1880 6410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:C-EUC1210 C206 +U 1 1 58023E26 +P 2200 6600 +F 0 "C206" H 2280 6410 60 0000 L BNN + 1 2200 6600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_1210" H 2280 6410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R68 +U 1 1 58023E25 +P 5900 6700 +F 0 "R68" V 5810 6655 60 0000 R TNN +F 1 "150k" V 5870 6950 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5870 6950 60 0001 C CNN +F 3 "" H 5870 6950 60 0000 C CNN + 1 5900 6700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R69 +U 1 1 58023E24 +P 5900 7300 +F 0 "R69" V 5810 7255 60 0000 R TNN +F 1 "226k" V 5850 7550 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5850 7550 60 0001 C CNN +F 3 "" H 5850 7550 60 0000 C CNN + 1 5900 7300 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C208 +U 1 1 58023E23 +P 6200 6600 +F 0 "C208" H 6280 6410 60 0000 L BNN + 1 6200 6600 + 1 0 0 -1 +F 2 "Cryptech_Alpha_Footprints:C_0402" H 6280 6410 60 0001 C CNN +$EndComp +$Comp +L Cryptech_Alpha:BLM31PG330SN1_1206 FB7 +U 1 1 58023E22 +P 7900 6500 +F 0 "FB7" H 7750 6700 60 0000 L BNN +F 1 "BLM31PG330SN1" H 7750 6400 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:L_1206" H 7750 6400 60 0001 C CNN +F 3 "" H 7750 6400 60 0000 C CNN + 1 7900 6500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R70 +U 1 1 58023E21 +P 7600 7200 +F 0 "R70" V 7510 7155 60 0000 R TNN +F 1 "100" V 7610 7100 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 7610 7100 60 0001 C CNN +F 3 "" H 7610 7100 60 0000 C CNN + 1 7600 7200 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R67 +U 1 1 58023E20 +P 5500 7300 +F 0 "R67" V 5410 7255 60 0000 R TNN +F 1 "0" V 5440 7540 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5440 7540 60 0001 C CNN +F 3 "" H 5440 7540 60 0000 C CNN + 1 5500 7300 + 0 -1 -1 0 +$EndComp +NoConn ~ 5300 8100 +NoConn ~ 5300 8300 +NoConn ~ 3600 7400 +NoConn ~ 3600 7600 +NoConn ~ 3600 7800 +NoConn ~ 3600 8000 +NoConn ~ 3600 8200 +NoConn ~ 3600 8700 +NoConn ~ 5300 8700 +Wire Wire Line + 8300 6400 8300 6200 +$Comp +L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR? +U 1 1 5AF3F25C +P 8300 6200 +F 0 "#PWR?" H 8300 6050 50 0001 C CNN +F 1 "FPGA_VCCINT_1V0" H 8315 6373 50 0000 C CNN +F 2 "" H 8300 6200 60 0000 C CNN +F 3 "" H 8300 6200 60 0000 C CNN + 1 8300 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA77EC +P 8150 6400 +F 0 "#FLG?" H 8150 6475 50 0001 C CNN +F 1 "PWR_FLAG" H 8150 6574 50 0000 C CNN +F 2 "" H 8150 6400 50 0001 C CNN +F 3 "~" H 8150 6400 50 0001 C CNN + 1 8150 6400 + 1 0 0 -1 +$EndComp +Connection ~ 8150 6400 +$EndSCHEMATC \ No newline at end of file diff --git a/KiCAD/rev02_25.sch b/KiCAD/rev02_25.sch new file mode 100644 index 0000000..f6bf4c1 --- /dev/null +++ b/KiCAD/rev02_25.sch @@ -0,0 +1,447 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 27 27 +Title "rev02_25" +Date "15 10 2016" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 8100 5000 0 60 ~ 12 +*) Recommended power-up sequence:\n1) VCCINT\n2) VCCAUX\n3) VCCO\nRC network values are preliminary,\nshould be tweaked after experiments +Text Notes 4100 5300 0 60 ~ 12 +---> +Text Notes 8800 5300 0 60 ~ 12 +---> +Text Notes 600 8700 0 60 ~ 12 +---> +Text Notes 5100 8700 0 60 ~ 12 +---> +Text Notes 6500 9400 0 60 ~ 12 +*) "Power OK" LED, should be of green color +Text Notes 8700 10220 0 66 ~ 12 +FPGA power sequencing +Text Notes 1950 5250 0 60 ~ 12 +R72 +Text Notes 1940 4820 0 60 ~ 12 +D2 +Text Notes 2190 5070 0 60 ~ 12 +BAT54 +Text Notes 5740 5050 1 60 ~ 12 +R75 +Text Notes 6450 5250 0 60 ~ 12 +R76 +Text Notes 6600 4820 0 60 ~ 12 +D4 +Text Notes 6690 5040 0 60 ~ 12 +BAT54 +Text Notes 2140 8450 1 60 ~ 12 +R73 +Text Notes 2850 8650 0 60 ~ 12 +R74 +Text Notes 2890 8220 0 60 ~ 12 +D3 +Text Notes 3120 8470 0 60 ~ 12 +BAT54 +Text Notes 6740 8050 1 60 ~ 12 +R77 +Text Notes 7150 8600 0 60 ~ 12 +2N7002 +Text Notes 6990 8540 0 60 ~ 12 +Q6 +Text Notes 8220 8130 0 60 ~ 12 +LED18 +Text Notes 8090 7690 0 60 ~ 12 +R78 +Text Notes 2560 5590 0 60 ~ 12 +C211 +Text Notes 2560 5790 0 60 ~ 12 +0.1~uF +Text Notes 3460 8990 0 60 ~ 12 +C212 +Text Notes 3460 9190 0 60 ~ 12 +0.1~uF +Text Notes 7060 5590 0 60 ~ 12 +C213 +Text Notes 7060 5790 0 60 ~ 12 +0.1~uF +$Comp +L power:GND GND_225 +U 1 1 58023E1F +P 2500 6000 +F 0 "GND_225" H 2500 6000 20 0000 C CNN +F 1 "+GND" H 2500 5930 30 0000 C CNN +F 2 "" H 2500 6000 70 0000 C CNN +F 3 "" H 2500 6000 70 0000 C CNN + 1 2500 6000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_226 +U 1 1 58023E1E +P 7000 6000 +F 0 "GND_226" H 7000 6000 20 0000 C CNN +F 1 "+GND" H 7000 5930 30 0000 C CNN +F 2 "" H 7000 6000 70 0000 C CNN +F 3 "" H 7000 6000 70 0000 C CNN + 1 7000 6000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_227 +U 1 1 58023E1D +P 3400 9400 +F 0 "GND_227" H 3400 9400 20 0000 C CNN +F 1 "+GND" H 3400 9330 30 0000 C CNN +F 2 "" H 3400 9400 70 0000 C CNN +F 3 "" H 3400 9400 70 0000 C CNN + 1 3400 9400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND GND_228 +U 1 1 58023E1C +P 8000 8900 +F 0 "GND_228" H 8000 8900 20 0000 C CNN +F 1 "+GND" H 8000 8830 30 0000 C CNN +F 2 "" H 8000 8900 70 0000 C CNN +F 3 "" H 8000 8900 70 0000 C CNN + 1 8000 8900 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_4 +U 1 1 58023E1B +P 900 4500 +F 0 "VCC_5V0_4" H 900 4500 20 0000 C CNN +F 1 "+VCC_5V0" H 900 4430 30 0000 C CNN +F 2 "" H 900 4500 70 0000 C CNN +F 3 "" H 900 4500 70 0000 C CNN + 1 900 4500 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_5 +U 1 1 58023E1A +P 2200 7800 +F 0 "VCC_5V0_5" H 2200 7800 20 0000 C CNN +F 1 "+VCC_5V0" H 2200 7730 30 0000 C CNN +F 2 "" H 2200 7800 70 0000 C CNN +F 3 "" H 2200 7800 70 0000 C CNN + 1 2200 7800 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_6 +U 1 1 58023E19 +P 6800 7200 +F 0 "VCC_5V0_6" H 6800 7200 20 0000 C CNN +F 1 "+VCC_5V0" H 6800 7130 30 0000 C CNN +F 2 "" H 6800 7200 70 0000 C CNN +F 3 "" H 6800 7200 70 0000 C CNN + 1 6800 7200 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:VCC_5V0 VCC_5V0_7 +U 1 1 58023E18 +P 5800 4500 +F 0 "VCC_5V0_7" H 5800 4500 20 0000 C CNN +F 1 "+VCC_5V0" H 5800 4430 30 0000 C CNN +F 2 "" H 5800 4500 70 0000 C CNN +F 3 "" H 5800 4500 70 0000 C CNN + 1 5800 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 5800 2500 6000 +Wire Wire Line + 7000 5800 7000 6000 +Wire Wire Line + 3400 9200 3400 9400 +Wire Wire Line + 8000 8700 7800 8700 +Wire Wire Line + 8000 8700 8000 8900 +Wire Wire Line + 900 4500 900 5300 +Wire Wire Line + 1900 5300 1700 5300 +Wire Wire Line + 1700 4900 1700 5300 +Wire Wire Line + 2000 4900 1700 4900 +Wire Wire Line + 1700 5300 900 5300 +Connection ~ 1700 5300 +Wire Wire Line + 2200 7800 2200 8100 +Wire Wire Line + 6800 7200 6800 7500 +Wire Wire Line + 6800 7500 6800 7700 +Wire Wire Line + 8000 7500 8000 7600 +Wire Wire Line + 8000 7500 6800 7500 +Connection ~ 6800 7500 +Wire Wire Line + 5800 4500 5800 4700 +Wire Wire Line + 7000 5300 6800 5300 +Wire Wire Line + 7900 5300 7000 5300 +Wire Wire Line + 7000 5300 7000 5500 +Wire Wire Line + 7000 4900 6700 4900 +Wire Wire Line + 7000 4900 7000 5300 +Text GLabel 7900 5300 2 48 Output ~ 0 +PWR_ENA_VCCAUX +Connection ~ 7000 5300 +Wire Wire Line + 5800 5300 5000 5300 +Wire Wire Line + 5800 5100 5800 5300 +Wire Wire Line + 6400 5300 6200 5300 +Wire Wire Line + 6200 4900 6200 5300 +Wire Wire Line + 6500 4900 6200 4900 +Wire Wire Line + 6200 5300 5800 5300 +Text GLabel 5000 5300 0 48 Input ~ 0 +POK_VCCINT +Connection ~ 5800 5300 +Connection ~ 6200 5300 +Wire Wire Line + 4350 8700 3400 8700 +Wire Wire Line + 3400 8300 3100 8300 +Wire Wire Line + 3400 8300 3400 8700 +Wire Wire Line + 3400 8700 3200 8700 +Wire Wire Line + 3400 8700 3400 8900 +Text GLabel 4350 8700 2 48 Output ~ 0 +PWR_ENA_VCCO +Connection ~ 3400 8700 +Wire Wire Line + 2500 4900 2200 4900 +Wire Wire Line + 2500 4900 2500 5300 +Wire Wire Line + 2500 5300 2300 5300 +Wire Wire Line + 2500 5300 2500 5500 +Wire Wire Line + 3400 5300 2500 5300 +Text GLabel 3400 5300 2 48 Output ~ 0 +PWR_ENA_VCCINT +Connection ~ 2500 5300 +Wire Wire Line + 2200 8700 1450 8700 +Wire Wire Line + 2200 8500 2200 8700 +Wire Wire Line + 2800 8700 2600 8700 +Wire Wire Line + 2600 8300 2600 8700 +Wire Wire Line + 2900 8300 2600 8300 +Wire Wire Line + 2600 8700 2200 8700 +Text GLabel 1450 8700 0 48 Input ~ 0 +POK_VCCAUX +Connection ~ 2200 8700 +Connection ~ 2600 8700 +Wire Wire Line + 6800 8700 6050 8700 +Wire Wire Line + 6800 8100 6800 8700 +Wire Wire Line + 7400 8700 6800 8700 +Text GLabel 6050 8700 0 48 Input ~ 0 +POK_VCCO +Connection ~ 6800 8700 +Wire Wire Line + 8000 8500 7800 8500 +Wire Wire Line + 8000 8400 8000 8500 +Wire Wire Line + 8000 8000 8000 8100 +$Comp +L Cryptech_Alpha:R-EU_R0402 R72 +U 1 1 58023E17 +P 2100 5300 +F 0 "R72" H 1990 5155 60 0000 L BNN +F 1 "100k" H 1940 5150 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 1940 5150 60 0001 C CNN +F 3 "" H 1940 5150 60 0000 C CNN + 1 2100 5300 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:2N7002 Q6 +U 1 1 58023E16 +P 7600 8600 +F 0 "Q6" H 7490 8345 60 0000 L BNN +F 1 "2N7002P,235" H 6980 8530 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 6980 8530 60 0001 C CNN +F 3 "" H 6980 8530 60 0000 C CNN + 1 7600 8600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:LEDCHIP-LED0603 LED18 +U 1 1 58023E15 +P 8000 8200 +F 0 "LED18" H 7855 8110 60 0000 R BNN +F 1 "LTST-C191KGKT" H 7855 8010 60 0000 R BNN +F 2 "Cryptech_Alpha_Footprints:VD_0603" H 7855 8010 60 0001 C CNN +F 3 "" H 7855 8010 60 0000 C CNN + 1 8000 8200 + -1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R78 +U 1 1 58023E14 +P 8000 7800 +F 0 "R78" V 8090 7755 60 0000 L TNN +F 1 "330" V 7930 7710 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 7930 7710 60 0001 C CNN +F 3 "" H 7930 7710 60 0000 C CNN + 1 8000 7800 + 0 -1 1 0 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C211 +U 1 1 58023E13 +P 2500 5600 +F 0 "C211" H 2580 5410 60 0000 L BNN +F 1 "0.1uF" H 2840 5620 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 2840 5620 60 0001 C CNN +F 3 "" H 2840 5620 60 0000 C CNN + 1 2500 5600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C212 +U 1 1 58023E12 +P 3400 9000 +F 0 "C212" H 3480 8810 60 0000 L BNN +F 1 "0.1uF" H 3730 9020 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 3730 9020 60 0001 C CNN +F 3 "" H 3730 9020 60 0000 C CNN + 1 3400 9000 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:C-EUC0402 C213 +U 1 1 58023E11 +P 7000 5600 +F 0 "C213" H 7080 5410 60 0000 L BNN +F 1 "0.1uF" H 7330 5620 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:C_0402" H 7330 5620 60 0001 C CNN +F 3 "" H 7330 5620 60 0000 C CNN + 1 7000 5600 + 1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:BAT54 D2 +U 1 1 58023E10 +P 2100 4900 +F 0 "D2" H 2185 4740 60 0000 R BNN +F 1 "BAT54LT1G" H 2090 4980 60 0000 R BNN +F 2 "Cryptech_Alpha_Footprints:SOT-23" H 2090 4980 60 0001 C CNN +F 3 "" H 2090 4980 60 0000 C CNN + 1 2100 4900 + -1 0 0 -1 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R75 +U 1 1 58023E0F +P 5800 4900 +F 0 "R75" V 5710 4855 60 0000 R TNN +F 1 "4.7k" H 5640 4740 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 5640 4740 60 0001 C CNN +F 3 "" H 5640 4740 60 0000 C CNN + 1 5800 4900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:R-EU_R0402 R76 +U 1 1 58023E0E +P 6600 5300 +F 0 "R76" H 6490 5155 60 0000 L BNN +F 1 "100k" H 6450 5150 60 0000 L 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