From 59237fb52930aa5495fe25526d5269f05239282e Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Wed, 23 Sep 2020 15:14:24 +0300 Subject: Entirely routed the design. Not useable right now, so far just reports zero unrouted nets. Will cleanup next. --- KiCAD/rev02_17.sch-bak | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'KiCAD/rev02_17.sch-bak') diff --git a/KiCAD/rev02_17.sch-bak b/KiCAD/rev02_17.sch-bak index 7612c65..f1e151e 100644 --- a/KiCAD/rev02_17.sch-bak +++ b/KiCAD/rev02_17.sch-bak @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr B 17000 11000 encoding utf-8 -Sheet 19 27 +Sheet 18 27 Title "rev02_17" Date "15 10 2016" Rev "" @@ -308,13 +308,13 @@ Wire Wire Line Wire Wire Line 2950 8400 1800 8400 Text GLabel 2950 5900 2 48 Output ~ 0 -MKM_FPGA_CS_N +ICE40_FPGA_CS_N Text GLabel 2950 6400 2 48 Output ~ 0 -MKM_FPGA_SCK +ICE40_FPGA_SCK Text GLabel 2950 6100 2 48 Output ~ 0 -MKM_FPGA_MOSI +ICE40_FPGA_MOSI Text GLabel 2950 6200 2 48 Input ~ 0 -MKM_FPGA_MISO +ICE40_FPGA_MISO Text GLabel 2950 6300 2 48 Output ~ 0 FPGA_GPIO_LED_0 Text GLabel 2950 5300 2 48 Output ~ 0 -- cgit v1.2.3