From 1dee9e20eccc1cf3a6396d88c765b44faebacdd2 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Wed, 23 Sep 2020 15:11:11 +0300 Subject: Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA along with it's power subsystem and programming circuitry. --- KiCAD/rev02_05.sch-bak | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) (limited to 'KiCAD/rev02_05.sch-bak') diff --git a/KiCAD/rev02_05.sch-bak b/KiCAD/rev02_05.sch-bak index b877484..ecd3422 100644 --- a/KiCAD/rev02_05.sch-bak +++ b/KiCAD/rev02_05.sch-bak @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr B 17000 11000 encoding utf-8 -Sheet 7 27 +Sheet 19 27 Title "rev02_05" Date "15 10 2016" Rev "" @@ -573,12 +573,8 @@ Text GLabel 2250 7200 0 48 BiDi ~ 0 AVR_GPIO_ARM_3 Wire Bus Line 14900 3200 13500 3200 -Wire Bus Line - 13500 3200 13500 6500 Text Label 13500 3200 0 60 ~ 0 FMC_D[0..31]FMC_A[0..25] -Wire Bus Line - 9990 3200 9990 5900 Wire Bus Line 9990 3200 8590 3200 Text Label 8590 3200 0 60 ~ 0 @@ -630,11 +626,7 @@ F 3 "" H 4700 5600 50 0001 C CNN 1 0 0 -1 $EndComp NoConn ~ 3100 5300 -NoConn ~ 3100 5400 NoConn ~ 3100 5500 -NoConn ~ 3100 5600 -NoConn ~ 3100 5700 -NoConn ~ 3100 5800 NoConn ~ 3100 6900 NoConn ~ 3100 7000 NoConn ~ 3100 7100 @@ -675,4 +667,24 @@ NoConn ~ 6200 3100 NoConn ~ 6200 3000 NoConn ~ 6200 2900 NoConn ~ 6200 2800 +Wire Wire Line + 3100 5700 2250 5700 +Wire Wire Line + 3100 5600 2250 5600 +Wire Wire Line + 3100 5400 2250 5400 +Wire Wire Line + 3100 5800 2250 5800 +Text GLabel 2250 5700 0 50 Output ~ 0 +ARM_SPI3_SCK +Text GLabel 2250 5600 0 50 Output ~ 0 +ARM_SPI3_CS_N +Text GLabel 2250 5400 0 50 Output ~ 0 +ARM_SPI3_MOSI +Text GLabel 2250 5800 0 50 Input ~ 0 +ARM_SPI3_MISO +Wire Bus Line + 9990 3200 9990 5900 +Wire Bus Line + 13500 3200 13500 6500 $EndSCHEMATC -- cgit v1.2.3