From a0a00256b970d0c60171ca9a97dbfbd95e4e0c7d Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Wed, 23 Sep 2020 15:21:46 +0300 Subject: Renamed schematics sheets for consistency. --- KiCAD/Cryptech Alpha.sch | 52 ++++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'KiCAD/Cryptech Alpha.sch') diff --git a/KiCAD/Cryptech Alpha.sch b/KiCAD/Cryptech Alpha.sch index 2a49ce3..7d80b8f 100644 --- a/KiCAD/Cryptech Alpha.sch +++ b/KiCAD/Cryptech Alpha.sch @@ -17,157 +17,157 @@ $Sheet S 7100 6650 500 300 U 57D8469B F0 "Introduction" 60 -F1 "rev02_00.sch" 60 +F1 "rev04_00.sch" 60 $EndSheet $Sheet S 9900 850 750 400 U 57D84708 F0 "Power" 60 -F1 "rev02_01.sch" 60 +F1 "rev04_01.sch" 60 $EndSheet $Sheet S 750 5200 750 400 U 57D8488D F0 "Entropy source" 60 -F1 "rev02_02.sch" 60 +F1 "rev04_02.sch" 60 $EndSheet $Sheet S 6950 3100 750 400 U 57D84936 F0 "STM32 configuration" 60 -F1 "rev02_03.sch" 60 +F1 "rev04_03.sch" 60 $EndSheet $Sheet S 6950 2400 750 400 U 57D849FD F0 "STM32 power" 60 -F1 "rev02_04.sch" 60 +F1 "rev04_04.sch" 60 $EndSheet $Sheet S 8700 2400 750 400 U 57D84B22 F0 "SDRAM" 60 -F1 "rev02_06.sch" 60 +F1 "rev04_06.sch" 60 $EndSheet $Sheet S 8700 3100 750 400 U 57D84C13 F0 "Keystore memory" 60 -F1 "rev02_07.sch" 60 +F1 "rev04_07.sch" 60 $EndSheet $Sheet S 8700 3800 750 400 U 57D84C55 F0 "Real Time Clock" 60 -F1 "rev02_08.sch" 60 +F1 "rev04_08.sch" 60 $EndSheet $Sheet S 7550 1200 750 400 U 57D84CB3 F0 "User USB UART" 60 -F1 "rev02_09.sch" 60 +F1 "rev04_09.sch" 60 $EndSheet $Sheet S 6350 1200 750 400 U 57D84E30 F0 "MGMT USB UART" 60 -F1 "rev02_10.sch" 60 +F1 "rev04_10.sch" 60 $EndSheet $Sheet S 5350 5250 750 450 U 57D84FAD F0 "Tamper Circuitry" 60 -F1 "rev02_11.sch" 60 +F1 "rev04_11.sch" 60 $EndSheet $Sheet S 5350 6100 750 400 U 57D8509E F0 "Master Key Memory" 60 -F1 "rev02_12.sch" 60 +F1 "rev04_12.sch" 60 $EndSheet $Sheet S 2100 2100 750 400 U 57D85134 F0 "Config interface" 60 -F1 "rev02_13.sch" 60 +F1 "rev04_13.sch" 60 $EndSheet $Sheet S 2100 2700 750 400 U 57D85217 F0 "Unused" 60 -F1 "rev02_14.sch" 60 +F1 "rev04_14.sch" 60 $EndSheet $Sheet S 650 1300 750 400 U 57D85260 F0 "Config memory" 60 -F1 "rev02_15.sch" 60 +F1 "rev04_15.sch" 60 $EndSheet $Sheet S 2100 3350 750 400 U 57D85319 F0 "Unused banks" 60 -F1 "rev02_16.sch" 60 +F1 "rev04_16.sch" 60 $EndSheet $Sheet S 4900 3350 750 400 U 57D85338 F0 "FMC interface" 60 -F1 "rev02_17.sch" 60 +F1 "rev04_17.sch" 60 $EndSheet $Sheet S 6950 3800 750 400 U 57D85391 F0 "STM32 IO" 60 -F1 "rev02_05.sch" 60 +F1 "rev04_05.sch" 60 $EndSheet $Sheet S 9900 2100 750 400 U 57D853B0 F0 "Power: 1V8 3V3" 60 -F1 "rev02_18.sch" 60 +F1 "rev04_18.sch" 60 $EndSheet $Sheet S 2100 4050 750 400 U 57D854CB F0 "GPIO" 60 -F1 "rev02_19.sch" 60 +F1 "rev04_19.sch" 60 $EndSheet $Sheet S 4900 4050 750 400 U 57D8556F F0 "MKM interface" 60 -F1 "rev02_20.sch" 60 +F1 "rev04_20.sch" 60 $EndSheet $Sheet S 3500 4050 750 400 U 57D8559C F0 "PWR and GND" 60 -F1 "rev02_21.sch" 60 +F1 "rev04_21.sch" 60 $EndSheet $Sheet S 3500 2700 750 400 U 57D855DE F0 "Core and AUX bypass" 60 -F1 "rev02_22.sch" 60 +F1 "rev04_22.sch" 60 $EndSheet $Sheet S 3500 3350 750 400 U 57D8583B F0 "VCCO bypass" 60 -F1 "rev02_23.sch" 60 +F1 "rev04_23.sch" 60 $EndSheet $Sheet S 9900 1500 750 400 U 57D85A75 F0 "Power: 1V0" 60 -F1 "rev02_24.sch" 60 +F1 "rev04_24.sch" 60 $EndSheet $Sheet S 3500 2100 750 400 U 57D85B19 F0 "Power sequencing" 60 -F1 "rev02_25.sch" 60 +F1 "rev04_25.sch" 60 $EndSheet Wire Notes Line 6400 2200 6400 4400 -- cgit v1.2.3