From 1dee9e20eccc1cf3a6396d88c765b44faebacdd2 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Wed, 23 Sep 2020 15:11:11 +0300
Subject: Almost finished doing edits to schematics. Added Lattice iCE40
 UltraPlus FPGA along with it's power subsystem and programming circuitry.

---
 KiCAD/Cryptech Alpha-cache.lib | 96 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

(limited to 'KiCAD/Cryptech Alpha-cache.lib')

diff --git a/KiCAD/Cryptech Alpha-cache.lib b/KiCAD/Cryptech Alpha-cache.lib
index fe3cd8c..dcefdff 100644
--- a/KiCAD/Cryptech Alpha-cache.lib	
+++ b/KiCAD/Cryptech Alpha-cache.lib	
@@ -1,6 +1,37 @@
 EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
+# Connector_Generic_Conn_01x08
+#
+DEF Connector_Generic_Conn_01x08 J 0 40 Y N 1 F N
+F0 "J" 0 400 50 H V C CNN
+F1 "Connector_Generic_Conn_01x08" 0 -500 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -395 0 -405 1 1 6 N
+S -50 -295 0 -305 1 1 6 N
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 305 0 295 1 1 6 N
+S -50 350 50 -450 1 1 10 f
+X Pin_1 1 -200 300 150 R 50 50 1 1 P
+X Pin_2 2 -200 200 150 R 50 50 1 1 P
+X Pin_3 3 -200 100 150 R 50 50 1 1 P
+X Pin_4 4 -200 0 150 R 50 50 1 1 P
+X Pin_5 5 -200 -100 150 R 50 50 1 1 P
+X Pin_6 6 -200 -200 150 R 50 50 1 1 P
+X Pin_7 7 -200 -300 150 R 50 50 1 1 P
+X Pin_8 8 -200 -400 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # Cryptech_Alpha_15V_STABLE
 #
 DEF Cryptech_Alpha_15V_STABLE #PWR 0 0 Y Y 1 F P
@@ -95,6 +126,54 @@ X VCC 20 0 300 200 D 70 1 3 1 W
 ENDDRAW
 ENDDEF
 #
+# Cryptech_Alpha_ADP121-AUJZ12R7
+#
+DEF Cryptech_Alpha_ADP121-AUJZ12R7 U 0 40 Y Y 1 L N
+F0 "U" -193 477 50 H V L BNN
+F1 "Cryptech_Alpha_ADP121-AUJZ12R7" -265 -716 50 H V L BNN
+F2 "SOT95P280X100-5N" 0 0 50 H I L BNN
+F3 "2074869" 0 0 50 H I L BNN
+F4 "Analog Devices" 0 0 50 H I L BNN
+F5 "TSOT-5" 0 0 50 H I L BNN
+F6 "10R7024" 0 0 50 H I L BNN
+F7 "ADP121-AUJZ12R7" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 16 -500 -600 500 -600 N
+P 2 0 0 16 -500 400 -500 -600 N
+P 2 0 0 16 500 -600 500 400 N
+P 2 0 0 16 500 400 -500 400 N
+X VIN 1 -700 200 200 R 40 40 0 0 I
+X GND 2 -700 -400 200 R 40 40 0 0 P
+X EN 3 -700 0 200 R 40 40 0 0 I
+X NC 4 -700 -200 200 R 40 40 0 0 N
+X VOUT 5 700 200 200 L 40 40 0 0 O
+ENDDRAW
+ENDDEF
+#
+# Cryptech_Alpha_ADP121-AUJZ25R7
+#
+DEF Cryptech_Alpha_ADP121-AUJZ25R7 U 0 40 Y Y 1 L N
+F0 "U" -193 477 50 H V L BNN
+F1 "Cryptech_Alpha_ADP121-AUJZ25R7" -265 -716 50 H V L BNN
+F2 "SOT95P280X100-5N" 0 0 50 H I L BNN
+F3 "2074869" 0 0 50 H I L BNN
+F4 "Analog Devices" 0 0 50 H I L BNN
+F5 "TSOT-5" 0 0 50 H I L BNN
+F6 "10R7024" 0 0 50 H I L BNN
+F7 "ADP121-AUJZ25R7" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 16 -500 -600 500 -600 N
+P 2 0 0 16 -500 400 -500 -600 N
+P 2 0 0 16 500 -600 500 400 N
+P 2 0 0 16 500 400 -500 400 N
+X VIN 1 -700 200 200 R 40 40 0 0 I
+X GND 2 -700 -400 200 R 40 40 0 0 P
+X EN 3 -700 0 200 R 40 40 0 0 I
+X NC 4 -700 -200 200 R 40 40 0 0 N
+X VOUT 5 700 200 200 L 40 40 0 0 O
+ENDDRAW
+ENDDEF
+#
 # Cryptech_Alpha_ASF*
 #
 DEF Cryptech_Alpha_ASF* Q 0 40 Y Y 1 F N
@@ -2204,6 +2283,23 @@ X G1 4 -200 -300 200 R 1 1 0 1 W
 ENDDRAW
 ENDDEF
 #
+# Device_R
+#
+DEF Device_R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device_R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # FPGA_Lattice_ICE40UP5K-SG48ITR
 #
 DEF FPGA_Lattice_ICE40UP5K-SG48ITR U 0 20 Y Y 4 L N
-- 
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