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2020-09-23Finished cleanup, fixed all pcbnew DRC errors reported. First attempt atPavel V. Shatov (Meister)
generating Gerbers. The result is somewhat surprising, since each Gerber is huge (10MB+). This turned out to be related to the way KiCAD fills copper polygons. Version 5.1.x that I use has support for some better pouring algorithm, while the 4.x version Fredrik used at the time of conversion had some different and obviously inferior pouring algorithm. I updated all the shapes to use the newer fill algorithm and this helped a bit, but didn't entirely solve the problem. Internal layers with large planes still produce very large Gerbers (~1MB), but they're more or less manageable now. Further research indicates there currently seems to be no way of further reducing Gerbers, see eg.: https://forum.kicad.info/t/gerber-files-are-too-large-due-to-thousands-of-drawn-features/17750
2020-09-23Did some cleanup, also had to re-route VCC_PLL for iCE40.Pavel V. Shatov (Meister)
2020-09-23Entirely routed the design. Not useable right now, so far just reports zeroPavel V. Shatov (Meister)
unrouted nets. Will cleanup next.
2020-09-23Intermediate step, re-routing the design according to the changes in schematics.Pavel V. Shatov (Meister)
2020-09-23Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGAPavel V. Shatov (Meister)
along with it's power subsystem and programming circuitry.
2020-09-23Continued doing edits. Removed AVR tiny tamper detection processor.Pavel V. Shatov (Meister)
2020-09-23Started editing the design. So far removed the old MKM component.Pavel V. Shatov (Meister)
2020-09-23Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah!Pavel V. Shatov (Meister)
2020-09-23Turns out multi-part components were not fully converted and were notPavel V. Shatov (Meister)
recognized properly during forward annotation. Had to do a couple of experiments to figure out how KiCAD handles this and then write some quick and dirty scripts to repair the multi-part symbols (STM32, Artix-7 and the 74_244 logic buffer were affected).
2020-09-23Fixed PCB footprint references. Basically had to just replace dashes withPavel V. Shatov (Meister)
underscores.
2020-09-23Initial project cleanupPavel V. Shatov (Meister)
2020-05-25Internal ground layers OK.Pavel V. Shatov (Meister)
2020-05-25Bottom Layer OKPavel V. Shatov (Meister)
2020-05-25Internal signal layer #2 cleaned up.Pavel V. Shatov (Meister)
2020-05-25Internal signal layer #1 cleaned up.Pavel V. Shatov (Meister)
2020-05-11Top (aka "Front") Layer OKPavel V. Shatov (Meister)
2020-04-23Copy of rev.04 project as-is after Fredrik's conversion script.Pavel V. Shatov (Meister)