| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-09-23 | Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA | Pavel V. Shatov (Meister) | |
| along with it's power subsystem and programming circuitry. | |||
| 2020-09-23 | Continued doing edits. Removed AVR tiny tamper detection processor. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Started editing the design. So far removed the old MKM component. | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah! | Pavel V. Shatov (Meister) | |
| 2020-09-23 | Turns out multi-part components were not fully converted and were not | Pavel V. Shatov (Meister) | |
| recognized properly during forward annotation. Had to do a couple of experiments to figure out how KiCAD handles this and then write some quick and dirty scripts to repair the multi-part symbols (STM32, Artix-7 and the 74_244 logic buffer were affected). | |||
| 2020-09-23 | Fixed PCB footprint references. Basically had to just replace dashes with | Pavel V. Shatov (Meister) | |
| underscores. | |||
| 2020-09-23 | Initial project cleanup | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal ground layers OK. | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Bottom Layer OK | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal signal layer #2 cleaned up. | Pavel V. Shatov (Meister) | |
| 2020-05-25 | Internal signal layer #1 cleaned up. | Pavel V. Shatov (Meister) | |
| 2020-05-11 | Top (aka "Front") Layer OK | Pavel V. Shatov (Meister) | |
| 2020-04-23 | Copy of rev.04 project as-is after Fredrik's conversion script. | Pavel V. Shatov (Meister) | |
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index : user/shatov/alpha_rev04 | |
| Unnamed repository; edit this file 'description' to name the repository. | git repositories |
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