diff options
Diffstat (limited to 'KiCAD/rev02_19.sch-bak')
| -rw-r--r-- | KiCAD/rev02_19.sch-bak | 176 |
1 files changed, 91 insertions, 85 deletions
diff --git a/KiCAD/rev02_19.sch-bak b/KiCAD/rev02_19.sch-bak index 9f12bd2..de36c88 100644 --- a/KiCAD/rev02_19.sch-bak +++ b/KiCAD/rev02_19.sch-bak @@ -1,5 +1,5 @@ EESchema Schematic File Version 4 -EELAYER 26 0 +EELAYER 30 0 EELAYER END $Descr B 17000 11000 encoding utf-8 @@ -23,7 +23,7 @@ Text Notes 6930 3910 0 60 ~ 12 *) Signals, that are allowed to be swapped, can be be swapped\nwith each other and/or moved to different pins within their bank. Text Notes 3300 6500 0 60 ~ 12 NOTE: One of the FPGA_GPIO_* pins\nshould be connected to one of the\nMRCC pins.\nThe non-MRCC GPIO signals should be\nlength matched to within 500 ps of\nthe MRCC signal. -Text Notes 8840 10230 0 84 ~ 12 +Text Notes 8840 10230 0 84 ~ 17 FPGA GPIO Text Notes 8950 4500 2 60 ~ 12 MA08-2 @@ -42,10 +42,10 @@ C122 Text Notes 7260 7190 0 60 ~ 12 0.1~uF $Comp -L power:GND GND_125 +L power:GND #GND_0125 U 1 1 58023F03 P 7200 5600 -F 0 "GND_125" H 7200 5600 20 0000 C CNN +F 0 "#GND_0125" H 7200 5600 20 0000 C CNN F 1 "+GND" H 7200 5530 30 0000 C CNN F 2 "" H 7200 5600 70 0000 C CNN F 3 "" H 7200 5600 70 0000 C CNN @@ -53,10 +53,10 @@ F 3 "" H 7200 5600 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_126 +L power:GND #GND_0126 U 1 1 58023F02 P 8400 5600 -F 0 "GND_126" H 8400 5600 20 0000 C CNN +F 0 "#GND_0126" H 8400 5600 20 0000 C CNN F 1 "+GND" H 8400 5530 30 0000 C CNN F 2 "" H 8400 5600 70 0000 C CNN F 3 "" H 8400 5600 70 0000 C CNN @@ -64,10 +64,10 @@ F 3 "" H 8400 5600 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_127 +L power:GND #GND_0127 U 1 1 58023F01 P 9200 5600 -F 0 "GND_127" H 9200 5600 20 0000 C CNN +F 0 "#GND_0127" H 9200 5600 20 0000 C CNN F 1 "+GND" H 9200 5530 30 0000 C CNN F 2 "" H 9200 5600 70 0000 C CNN F 3 "" H 9200 5600 70 0000 C CNN @@ -75,10 +75,10 @@ F 3 "" H 9200 5600 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_128 +L power:GND #GND_0128 U 1 1 58023F00 P 7200 7500 -F 0 "GND_128" H 7200 7500 20 0000 C CNN +F 0 "#GND_0128" H 7200 7500 20 0000 C CNN F 1 "+GND" H 7200 7430 30 0000 C CNN F 2 "" H 7200 7500 70 0000 C CNN F 3 "" H 7200 7500 70 0000 C CNN @@ -86,10 +86,10 @@ F 3 "" H 7200 7500 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_129 +L power:GND #GND_0129 U 1 1 58023EFF P 8400 7500 -F 0 "GND_129" H 8400 7500 20 0000 C CNN +F 0 "#GND_0129" H 8400 7500 20 0000 C CNN F 1 "+GND" H 8400 7430 30 0000 C CNN F 2 "" H 8400 7500 70 0000 C CNN F 3 "" H 8400 7500 70 0000 C CNN @@ -97,10 +97,10 @@ F 3 "" H 8400 7500 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_130 +L power:GND #GND_0130 U 1 1 58023EFE P 9200 7500 -F 0 "GND_130" H 9200 7500 20 0000 C CNN +F 0 "#GND_0130" H 9200 7500 20 0000 C CNN F 1 "+GND" H 9200 7430 30 0000 C CNN F 2 "" H 9200 7500 70 0000 C CNN F 3 "" H 9200 7500 70 0000 C CNN @@ -108,10 +108,10 @@ F 3 "" H 9200 7500 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_35 +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_035 U 1 1 58023EFD P 2100 4200 -F 0 "VCCO_3V3_35" H 2100 4200 20 0000 C CNN +F 0 "#VCCO_3V3_035" H 2100 4200 20 0000 C CNN F 1 "+VCCO_3V3" H 2100 4130 30 0000 C CNN F 2 "" H 2100 4200 70 0000 C CNN F 3 "" H 2100 4200 70 0000 C CNN @@ -119,10 +119,10 @@ F 3 "" H 2100 4200 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_36 +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_036 U 1 1 58023EFC P 7200 4300 -F 0 "VCCO_3V3_36" H 7200 4300 20 0000 C CNN +F 0 "#VCCO_3V3_036" H 7200 4300 20 0000 C CNN F 1 "+VCCO_3V3" H 7200 4230 30 0000 C CNN F 2 "" H 7200 4300 70 0000 C CNN F 3 "" H 7200 4300 70 0000 C CNN @@ -130,10 +130,10 @@ F 3 "" H 7200 4300 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_37 +L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_037 U 1 1 58023EFB P 7200 6200 -F 0 "VCCO_3V3_37" H 7200 6200 20 0000 C CNN +F 0 "#VCCO_3V3_037" H 7200 6200 20 0000 C CNN F 1 "+VCCO_3V3" H 7200 6130 30 0000 C CNN F 2 "" H 7200 6200 70 0000 C CNN F 3 "" H 7200 6200 70 0000 C CNN @@ -141,10 +141,10 @@ F 3 "" H 7200 6200 70 0000 C CNN 1 0 0 -1 $EndComp $Comp -L power:GND GND_131 +L power:GND #GND_0131 U 1 1 58023EFA P 9300 9100 -F 0 "GND_131" H 9300 9100 20 0000 C CNN +F 0 "#GND_0131" H 9300 9100 20 0000 C CNN F 1 "+GND" H 9300 9030 30 0000 C CNN F 2 "" H 9300 9100 70 0000 C CNN F 3 "" H 9300 9100 70 0000 C CNN @@ -277,167 +277,167 @@ Wire Wire Line 8500 6600 8400 6600 Wire Wire Line 3100 8100 1900 8100 -Text GLabel 3100 8100 2 48 UnSpc ~ 0 +Text GLabel 3100 8100 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_0 Wire Wire Line 3100 8200 1900 8200 -Text GLabel 3100 8200 2 48 UnSpc ~ 0 +Text GLabel 3100 8200 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_1 Wire Wire Line 3100 5200 1900 5200 -Text GLabel 3100 5200 2 48 UnSpc ~ 0 +Text GLabel 3100 5200 2 48 UnSpc ~ 0 FPGA_IRQ_N_0 Wire Wire Line 3100 5300 1900 5300 -Text GLabel 3100 5300 2 48 UnSpc ~ 0 +Text GLabel 3100 5300 2 48 UnSpc ~ 0 FPGA_IRQ_N_1 Wire Wire Line 3100 5400 1900 5400 -Text GLabel 3100 5400 2 48 UnSpc ~ 0 +Text GLabel 3100 5400 2 48 UnSpc ~ 0 FPGA_IRQ_N_2 Wire Wire Line 3100 5500 1900 5500 -Text GLabel 3100 5500 2 48 UnSpc ~ 0 +Text GLabel 3100 5500 2 48 UnSpc ~ 0 FPGA_IRQ_N_3 Wire Wire Line 3100 5600 1900 5600 -Text GLabel 3100 5800 2 48 BiDi ~ 0 +Text GLabel 3100 5800 2 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 8500 5000 7600 5000 -Text GLabel 7600 5000 0 48 BiDi ~ 0 +Text GLabel 7600 5000 0 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 3100 5700 1900 5700 -Text GLabel 3100 5700 2 48 BiDi ~ 0 +Text GLabel 3100 5700 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 10000 5000 9100 5000 -Text GLabel 10000 5000 2 48 BiDi ~ 0 +Text GLabel 10000 5000 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 3100 5800 1900 5800 -Text GLabel 3100 6900 2 48 BiDi ~ 0 +Text GLabel 3100 6900 2 48 BiDi ~ 0 FPGA_GPIO_A_2 Wire Wire Line 8500 5100 7600 5100 -Text GLabel 7600 5100 0 48 BiDi ~ 0 +Text GLabel 7600 5100 0 48 BiDi ~ 0 FPGA_GPIO_A_2 -Text GLabel 3100 7000 2 48 BiDi ~ 0 +Text GLabel 3100 7000 2 48 BiDi ~ 0 FPGA_GPIO_A_3 Wire Wire Line 10000 5100 9100 5100 -Text GLabel 10000 5100 2 48 BiDi ~ 0 +Text GLabel 10000 5100 2 48 BiDi ~ 0 FPGA_GPIO_A_3 -Text GLabel 3100 6500 2 48 BiDi ~ 0 +Text GLabel 3100 6500 2 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 8500 5300 7600 5300 -Text GLabel 7600 5300 0 48 BiDi ~ 0 +Text GLabel 7600 5300 0 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 3100 6100 1900 6100 -Text GLabel 3100 6600 2 48 BiDi ~ 0 +Text GLabel 3100 6600 2 48 BiDi ~ 0 FPGA_GPIO_A_5 Wire Wire Line 10000 5300 9100 5300 -Text GLabel 10000 5300 2 48 BiDi ~ 0 +Text GLabel 10000 5300 2 48 BiDi ~ 0 FPGA_GPIO_A_5 -Text GLabel 3100 6700 2 48 BiDi ~ 0 +Text GLabel 3100 6700 2 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 8500 5400 7600 5400 -Text GLabel 7600 5400 0 48 BiDi ~ 0 +Text GLabel 7600 5400 0 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 3100 6300 1900 6300 -Text GLabel 3100 6300 2 48 BiDi ~ 0 +Text GLabel 3100 6300 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 10000 5400 9100 5400 -Text GLabel 10000 5400 2 48 BiDi ~ 0 +Text GLabel 10000 5400 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 3100 6400 1900 6400 -Text GLabel 3100 6800 2 48 BiDi ~ 0 +Text GLabel 3100 6800 2 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 8500 6900 7600 6900 -Text GLabel 7600 6900 0 48 BiDi ~ 0 +Text GLabel 7600 6900 0 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 3100 6500 1900 6500 -Text GLabel 3100 5600 2 48 BiDi ~ 0 +Text GLabel 3100 5600 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 10000 6900 9100 6900 -Text GLabel 10000 6900 2 48 BiDi ~ 0 +Text GLabel 10000 6900 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 3100 6600 1900 6600 -Text GLabel 3100 6400 2 48 BiDi ~ 0 +Text GLabel 3100 6400 2 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 8500 7000 7600 7000 -Text GLabel 7600 7000 0 48 BiDi ~ 0 +Text GLabel 7600 7000 0 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 3100 6700 1900 6700 -Text GLabel 3100 6100 2 48 BiDi ~ 0 +Text GLabel 3100 6100 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 10000 7000 9100 7000 -Text GLabel 10000 7000 2 48 BiDi ~ 0 +Text GLabel 10000 7000 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 3100 6800 1900 6800 -Text GLabel 3100 7500 2 48 BiDi ~ 0 +Text GLabel 3100 7500 2 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 8500 7200 7600 7200 -Text GLabel 7600 7200 0 48 BiDi ~ 0 +Text GLabel 7600 7200 0 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 3100 6900 1900 6900 -Text GLabel 3100 9200 2 48 BiDi ~ 0 +Text GLabel 3100 9200 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 10000 7200 9100 7200 -Text GLabel 10000 7200 2 48 BiDi ~ 0 +Text GLabel 10000 7200 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 3100 7000 1900 7000 -Text GLabel 3100 8800 2 48 BiDi ~ 0 +Text GLabel 3100 8800 2 48 BiDi ~ 0 FPGA_GPIO_B_6 Wire Wire Line 8500 7300 7600 7300 -Text GLabel 7600 7300 0 48 BiDi ~ 0 +Text GLabel 7600 7300 0 48 BiDi ~ 0 FPGA_GPIO_B_6 -Text GLabel 3100 8900 2 48 BiDi ~ 0 +Text GLabel 3100 8900 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 10000 7300 9100 7300 -Text GLabel 10000 7300 2 48 BiDi ~ 0 +Text GLabel 10000 7300 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 3100 7300 1900 7300 -Text GLabel 3100 7300 2 48 UnSpc ~ 0 +Text GLabel 3100 7300 2 48 UnSpc ~ 0 FPGA_GCLK Wire Wire Line 7890 8700 7300 8700 -Text GLabel 7300 8700 0 48 Input ~ 0 +Text GLabel 7300 8700 0 48 Input ~ 0 FPGA_GPIO_LED_2 Wire Wire Line 8200 8600 7300 8600 -Text GLabel 7300 8600 0 48 Input ~ 0 +Text GLabel 7300 8600 0 48 Input ~ 0 FPGA_GPIO_LED_3 Wire Wire Line 7890 8900 7300 8900 -Text GLabel 7300 8900 0 48 Input ~ 0 +Text GLabel 7300 8900 0 48 Input ~ 0 FPGA_GPIO_LED_0 Wire Wire Line 8200 8800 7300 8800 -Text GLabel 7300 8800 0 48 Input ~ 0 +Text GLabel 7300 8800 0 48 Input ~ 0 FPGA_GPIO_LED_1 Wire Wire Line 8900 8900 8290 8900 @@ -449,15 +449,15 @@ Wire Wire Line 8700 8600 8600 8600 Wire Wire Line 3100 7200 1900 7200 -Text GLabel 3100 7200 2 48 Output ~ 0 +Text GLabel 3100 7200 2 48 Output ~ 0 FPGA_ENTROPY_DISABLE Wire Wire Line 3100 8300 1900 8300 -Text GLabel 3100 8300 2 48 UnSpc ~ 0 +Text GLabel 3100 8300 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_2 Wire Wire Line 3100 8400 1900 8400 -Text GLabel 3100 8400 2 48 UnSpc ~ 0 +Text GLabel 3100 8400 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_3 Wire Wire Line 3100 7500 1900 7500 @@ -472,9 +472,11 @@ L Cryptech_Alpha:MA08-2 SV2 U 1 1 58023EF9 P 8800 5000 F 0 "SV2" H 8980 5630 60 0000 R TNN - 1 8800 5000 - -1 0 0 1 +F 1 "~" H 8800 5000 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:PLD-16" H 8980 5630 60 0001 C CNN +F 3 "" H 8800 5000 50 0001 C CNN + 1 8800 5000 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R99 @@ -485,7 +487,7 @@ F 1 "330" H 8500 8510 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 8500 8510 60 0001 C CNN F 3 "" H 8500 8510 60 0000 C CNN 1 8400 8600 - -1 0 0 1 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R98 @@ -496,7 +498,7 @@ F 1 "330" H 8230 8510 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 8230 8510 60 0001 C CNN F 3 "" H 8230 8510 60 0000 C CNN 1 8090 8700 - -1 0 0 1 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R64 @@ -507,7 +509,7 @@ F 1 "330" H 8090 8500 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 8090 8500 60 0001 C CNN F 3 "" H 8090 8500 60 0000 C CNN 1 8400 8800 - -1 0 0 1 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R100 @@ -518,16 +520,18 @@ F 1 "330" H 8190 9160 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:R_0402" H 8190 9160 60 0001 C CNN F 3 "" H 8190 9160 60 0000 C CNN 1 8090 8900 - -1 0 0 1 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:MA08-2 SV3 U 1 1 58023EF4 P 8800 6900 F 0 "SV3" H 8980 7530 60 0000 R TNN - 1 8800 6900 - -1 0 0 1 +F 1 "~" H 8800 6900 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:PLD-16" H 8980 7530 60 0001 C CNN +F 3 "" H 8800 6900 50 0001 C CNN + 1 8800 6900 + -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:C-EUC0402 C121 @@ -538,7 +542,7 @@ F 1 "0.1uF" H 7320 5010 60 0000 L BNN F 2 "Cryptech_Alpha_Footprints:C_0402" H 7320 5010 60 0001 C CNN F 3 "" H 7320 5010 60 0000 C CNN 1 7200 5100 - 1 0 0 -1 + 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:C-EUC0402 C122 @@ -549,7 +553,7 @@ F 1 "0.1uF" H 7330 6910 60 0000 L BNN F 2 "Cryptech_Alpha_Footprints:C_0402" H 7330 6910 60 0001 C CNN F 3 "" H 7330 6910 60 0000 C CNN 1 7200 7000 - 1 0 0 -1 + 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED17 @@ -560,7 +564,7 @@ F 1 "LTST-C193TBKT-5A" V 8960 8220 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8960 8220 60 0001 C CNN F 3 "" H 8960 8220 60 0000 C CNN 1 9000 8900 - 0 -1 -1 0 + 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED15 @@ -571,7 +575,7 @@ F 1 "LTST-C191KGKT" V 8760 7920 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8760 7920 60 0001 C CNN F 3 "" H 8760 7920 60 0000 C CNN 1 8800 8800 - 0 -1 -1 0 + 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED16 @@ -582,7 +586,7 @@ F 1 "LTST-C191KSKT" V 8960 8030 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8960 8030 60 0001 C CNN F 3 "" H 8960 8030 60 0000 C CNN 1 9000 8700 - 0 -1 -1 0 + 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:LEDCHIP-LED0603 LED14 @@ -593,16 +597,18 @@ F 1 "LTST-C191KRKT" V 8760 7720 60 0000 R TNN F 2 "Cryptech_Alpha_Footprints:VD_0603" H 8760 7720 60 0001 C CNN F 3 "" H 8760 7720 60 0000 C CNN 1 8800 8600 - 0 -1 -1 0 + 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:XC7A200TFBG484_5 U13_11 U 1 1 58023EED P 1700 7100 F 0 "U13_11" H 1290 4090 60 0000 L BNN - 1 1700 7100 - 1 0 0 -1 +F 1 "~" H 1700 7100 50 0001 C CNN F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1290 4090 60 0001 C CNN +F 3 "" H 1700 7100 50 0001 C CNN + 1 1700 7100 + 1 0 0 -1 $EndComp NoConn ~ 1900 5000 NoConn ~ 1900 5100 @@ -628,4 +634,4 @@ NoConn ~ 1900 9700 NoConn ~ 1900 9800 NoConn ~ 1900 9900 NoConn ~ 1900 6200 -$EndSCHEMATC
\ No newline at end of file +$EndSCHEMATC |