diff options
Diffstat (limited to 'KiCAD/rev02_15.sch')
| -rw-r--r-- | KiCAD/rev02_15.sch | 614 |
1 files changed, 314 insertions, 300 deletions
diff --git a/KiCAD/rev02_15.sch b/KiCAD/rev02_15.sch index 61b86e8..2301053 100644 --- a/KiCAD/rev02_15.sch +++ b/KiCAD/rev02_15.sch @@ -4,7 +4,7 @@ EELAYER END $Descr B 17000 11000 encoding utf-8 Sheet 16 27 -Title "rev02_15" +Title "rev04_15" Date "15 10 2016" Rev "" Comp "" @@ -13,575 +13,589 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text Notes 7100 4900 0 60 ~ 12 +Text Notes 9150 2900 0 60 ~ 12 *) HOLD feature not used\n*) PROM is write-protected by default, to disable\nwrite protection (such as during firmware update),\njumper must be inserted -Text Notes 4800 8600 0 84 ~ 17 +Text Notes 6850 6600 0 84 ~ 17 FPGA clock -Text Notes 7100 4200 0 84 ~ 17 +Text Notes 9150 2200 0 84 ~ 17 FPGA config memory, 128 Mbit -Text Notes 1260 3930 0 84 ~ 17 +Text Notes 3310 1930 0 84 ~ 17 SPI mux to let ARM override access to\nFPGA config memory (to reprogram FPGA) -Text Notes 420 6220 0 42 ~ 8 +Text Notes 2470 4220 0 42 ~ 8 Install this jumper to allow\nARM to configure the FPGA -Text Notes 3490 4850 0 42 ~ 8 +Text Notes 5540 2850 0 42 ~ 8 ARM access default\ndisabled through pull-up -Text Notes 3190 7830 0 42 ~ 8 +Text Notes 5240 5830 0 42 ~ 8 FPGA access default\nenabled through pull-down -Text Notes 430 6540 0 42 ~ 8 +Text Notes 2480 4540 0 42 ~ 8 Install this jumper to allow\nARM to configure the FPGA -Text Notes 8520 10210 0 60 ~ 12 +Text Notes 10570 8210 0 60 ~ 12 FPGA supporting components -Text Notes 7900 6180 0 60 ~ 12 +Text Notes 9950 4180 0 60 ~ 12 IC3 -Text Notes 8460 6180 0 60 ~ 12 +Text Notes 10510 4180 0 60 ~ 12 N25Q128A13ES -Text Notes 7700 5900 0 60 ~ 12 +Text Notes 9750 3900 0 60 ~ 12 R51 -Text Notes 6800 6900 0 60 ~ 12 +Text Notes 8850 4900 0 60 ~ 12 R50 -Text Notes 4460 9590 0 60 ~ 12 +Text Notes 6510 7590 0 60 ~ 12 C111 -Text Notes 4460 9790 0 60 ~ 12 +Text Notes 6510 7790 0 60 ~ 12 0.01uF -Text Notes 5650 8770 2 60 ~ 12 +Text Notes 7700 6770 2 60 ~ 12 R49 -Text Notes 3470 4640 0 60 ~ 12 +Text Notes 5520 2640 0 60 ~ 12 R46 -Text Notes 3210 7520 2 60 ~ 12 +Text Notes 5260 5520 2 60 ~ 12 R47 -Text Notes 6450 9560 2 60 ~ 12 +Text Notes 8500 7560 2 60 ~ 12 R4 -Text Notes 3860 5510 0 60 ~ 12 +Text Notes 5910 3510 0 60 ~ 12 IC2 -Text Notes 3860 6330 0 60 ~ 12 +Text Notes 5910 4330 0 60 ~ 12 74*244DW $Comp L power:GND #GND_0102 U 1 1 58023F4D -P 7600 7300 -F 0 "#GND_0102" H 7600 7300 20 0000 C CNN -F 1 "+GND" H 7600 7230 30 0000 C CNN -F 2 "" H 7600 7300 70 0000 C CNN -F 3 "" H 7600 7300 70 0000 C CNN - 1 7600 7300 +P 9650 5300 +F 0 "#GND_0102" H 9650 5300 20 0000 C CNN +F 1 "+GND" H 9650 5230 30 0000 C CNN +F 2 "" H 9650 5300 70 0000 C CNN +F 3 "" H 9650 5300 70 0000 C CNN + 1 9650 5300 1 0 0 -1 $EndComp $Comp L power:GND #GND_0103 U 1 1 58023F4C -P 6700 7300 -F 0 "#GND_0103" H 6700 7300 20 0000 C CNN -F 1 "+GND" H 6700 7230 30 0000 C CNN -F 2 "" H 6700 7300 70 0000 C CNN -F 3 "" H 6700 7300 70 0000 C CNN - 1 6700 7300 +P 8750 5300 +F 0 "#GND_0103" H 8750 5300 20 0000 C CNN +F 1 "+GND" H 8750 5230 30 0000 C CNN +F 2 "" H 8750 5300 70 0000 C CNN +F 3 "" H 8750 5300 70 0000 C CNN + 1 8750 5300 1 0 0 -1 $EndComp $Comp L power:GND #GND_0104 U 1 1 58023F4B -P 10000 7300 -F 0 "#GND_0104" H 10000 7300 20 0000 C CNN -F 1 "+GND" H 10000 7230 30 0000 C CNN -F 2 "" H 10000 7300 70 0000 C CNN -F 3 "" H 10000 7300 70 0000 C CNN - 1 10000 7300 +P 12050 5300 +F 0 "#GND_0104" H 12050 5300 20 0000 C CNN +F 1 "+GND" H 12050 5230 30 0000 C CNN +F 2 "" H 12050 5300 70 0000 C CNN +F 3 "" H 12050 5300 70 0000 C CNN + 1 12050 5300 1 0 0 -1 $EndComp $Comp L power:GND #GND_0105 U 1 1 58023F4A -P 5000 10000 -F 0 "#GND_0105" H 5000 10000 20 0000 C CNN -F 1 "+GND" H 5000 9930 30 0000 C CNN -F 2 "" H 5000 10000 70 0000 C CNN -F 3 "" H 5000 10000 70 0000 C CNN - 1 5000 10000 +P 7050 8000 +F 0 "#GND_0105" H 7050 8000 20 0000 C CNN +F 1 "+GND" H 7050 7930 30 0000 C CNN +F 2 "" H 7050 8000 70 0000 C CNN +F 3 "" H 7050 8000 70 0000 C CNN + 1 7050 8000 1 0 0 -1 $EndComp $Comp L power:GND #GND_0106 U 1 1 58023F49 -P 4400 10000 -F 0 "#GND_0106" H 4400 10000 20 0000 C CNN -F 1 "+GND" H 4400 9930 30 0000 C CNN -F 2 "" H 4400 10000 70 0000 C CNN -F 3 "" H 4400 10000 70 0000 C CNN - 1 4400 10000 +P 6450 8000 +F 0 "#GND_0106" H 6450 8000 20 0000 C CNN +F 1 "+GND" H 6450 7930 30 0000 C CNN +F 2 "" H 6450 8000 70 0000 C CNN +F 3 "" H 6450 8000 70 0000 C CNN + 1 6450 8000 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_027 U 1 1 58023F48 -P 6700 5200 -F 0 "#VCCO_3V3_027" H 6700 5200 20 0000 C CNN -F 1 "+VCCO_3V3" H 6700 5130 30 0000 C CNN -F 2 "" H 6700 5200 70 0000 C CNN -F 3 "" H 6700 5200 70 0000 C CNN - 1 6700 5200 +P 8750 3200 +F 0 "#VCCO_3V3_027" H 8750 3200 20 0000 C CNN +F 1 "+VCCO_3V3" H 8750 3130 30 0000 C CNN +F 2 "" H 8750 3200 70 0000 C CNN +F 3 "" H 8750 3200 70 0000 C CNN + 1 8750 3200 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_028 U 1 1 58023F47 -P 4400 8900 -F 0 "#VCCO_3V3_028" H 4400 8900 20 0000 C CNN -F 1 "+VCCO_3V3" H 4400 8830 30 0000 C CNN -F 2 "" H 4400 8900 70 0000 C CNN -F 3 "" H 4400 8900 70 0000 C CNN - 1 4400 8900 +P 6450 6900 +F 0 "#VCCO_3V3_028" H 6450 6900 20 0000 C CNN +F 1 "+VCCO_3V3" H 6450 6830 30 0000 C CNN +F 2 "" H 6450 6900 70 0000 C CNN +F 3 "" H 6450 6900 70 0000 C CNN + 1 6450 6900 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_029 U 1 1 58023F46 -P 1660 4630 -F 0 "#VCCO_3V3_029" H 1660 4630 20 0000 C CNN -F 1 "+VCCO_3V3" H 1660 4560 30 0000 C CNN -F 2 "" H 1660 4630 70 0000 C CNN -F 3 "" H 1660 4630 70 0000 C CNN - 1 1660 4630 +P 3710 2630 +F 0 "#VCCO_3V3_029" H 3710 2630 20 0000 C CNN +F 1 "+VCCO_3V3" H 3710 2560 30 0000 C CNN +F 2 "" H 3710 2630 70 0000 C CNN +F 3 "" H 3710 2630 70 0000 C CNN + 1 3710 2630 1 0 0 -1 $EndComp $Comp L power:GND #GND_0107 U 1 1 58023F45 -P 1660 5630 -F 0 "#GND_0107" H 1660 5630 20 0000 C CNN -F 1 "+GND" H 1660 5560 30 0000 C CNN -F 2 "" H 1660 5630 70 0000 C CNN -F 3 "" H 1660 5630 70 0000 C CNN - 1 1660 5630 +P 3710 3630 +F 0 "#GND_0107" H 3710 3630 20 0000 C CNN +F 1 "+GND" H 3710 3560 30 0000 C CNN +F 2 "" H 3710 3630 70 0000 C CNN +F 3 "" H 3710 3630 70 0000 C CNN + 1 3710 3630 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_030 U 1 1 58023F44 -P 3360 4300 -F 0 "#VCCO_3V3_030" H 3360 4300 20 0000 C CNN -F 1 "+VCCO_3V3" H 3360 4230 30 0000 C CNN -F 2 "" H 3360 4300 70 0000 C CNN -F 3 "" H 3360 4300 70 0000 C CNN - 1 3360 4300 +P 5410 2300 +F 0 "#VCCO_3V3_030" H 5410 2300 20 0000 C CNN +F 1 "+VCCO_3V3" H 5410 2230 30 0000 C CNN +F 2 "" H 5410 2300 70 0000 C CNN +F 3 "" H 5410 2300 70 0000 C CNN + 1 5410 2300 1 0 0 -1 $EndComp $Comp L power:GND #GND_0108 U 1 1 58023F43 -P 2960 7930 -F 0 "#GND_0108" H 2960 7930 20 0000 C CNN -F 1 "+GND" H 2960 7860 30 0000 C CNN -F 2 "" H 2960 7930 70 0000 C CNN -F 3 "" H 2960 7930 70 0000 C CNN - 1 2960 7930 +P 5010 5930 +F 0 "#GND_0108" H 5010 5930 20 0000 C CNN +F 1 "+GND" H 5010 5860 30 0000 C CNN +F 2 "" H 5010 5930 70 0000 C CNN +F 3 "" H 5010 5930 70 0000 C CNN + 1 5010 5930 1 0 0 -1 $EndComp Wire Wire Line - 7600 6600 7600 7300 + 9650 4600 9650 5300 Wire Wire Line - 7700 6600 7600 6600 + 9750 4600 9650 4600 Wire Wire Line - 6700 7100 6700 7300 + 8750 5100 8750 5300 Wire Wire Line - 10000 7000 10000 7300 + 12050 5000 12050 5300 Wire Wire Line - 5000 9700 5000 10000 + 7050 7700 7050 8000 Wire Wire Line - 5100 9700 5000 9700 + 7150 7700 7050 7700 Wire Wire Line - 4400 9800 4400 10000 + 6450 7800 6450 8000 Wire Wire Line - 1660 5530 1660 5630 + 3710 3530 3710 3630 Wire Wire Line - 1660 5430 1660 5530 + 3710 3430 3710 3530 Wire Wire Line - 1260 5330 1260 5530 + 3310 3330 3310 3530 Wire Wire Line - 1660 5530 1260 5530 + 3710 3530 3310 3530 Wire Wire Line - 2960 7830 2960 7930 + 5010 5830 5010 5930 Wire Wire Line - 7600 5500 7600 5700 + 9650 3500 9650 3700 Wire Wire Line - 7600 5500 6700 5500 + 9650 3500 8750 3500 Wire Wire Line - 6700 5200 6700 5500 + 8750 3200 8750 3500 Wire Wire Line - 9400 6300 9150 6300 + 11450 4300 11200 4300 Wire Wire Line - 9400 5500 9400 6300 + 11450 3500 11450 4300 Wire Wire Line - 9400 5500 7600 5500 + 11450 3500 9650 3500 Wire Wire Line - 9400 6400 9150 6400 + 11450 4400 11200 4400 Wire Wire Line - 9400 6300 9400 6400 + 11450 4300 11450 4400 Wire Wire Line - 10000 6400 10000 6700 + 12050 4400 12050 4700 Wire Wire Line - 10000 6400 9400 6400 + 12050 4400 11450 4400 Wire Wire Line - 4400 9300 4400 9500 + 6450 7300 6450 7500 Wire Wire Line - 5000 9300 4400 9300 + 7050 7300 6450 7300 Wire Wire Line - 5100 9300 5000 9300 + 7150 7300 7050 7300 Wire Wire Line - 4400 8900 4400 9300 + 6450 6900 6450 7300 Wire Wire Line - 5400 8900 5000 8900 + 7450 6900 7050 6900 Wire Wire Line - 5000 8900 5000 9300 + 7050 6900 7050 7300 Wire Wire Line - 1660 4730 1660 4830 + 3710 2730 3710 2830 Wire Wire Line - 1660 4630 1660 4730 + 3710 2630 3710 2730 Wire Wire Line - 1260 4730 1260 5030 + 3310 2730 3310 3030 Wire Wire Line - 1660 4730 1260 4730 + 3710 2730 3310 2730 Wire Wire Line - 3360 4420 3360 4500 + 5410 2420 5410 2500 Wire Wire Line - 3360 4300 3360 4420 + 5410 2300 5410 2420 Wire Wire Line - 9770 6500 9150 6500 -Text Label 9150 6500 0 48 ~ 0 + 11820 4500 11200 4500 +Text Label 11200 4500 0 48 ~ 0 FPGA_PROM_SCLK Wire Wire Line - 4860 5730 4660 5730 + 6910 3730 6710 3730 Wire Wire Line - 4860 5730 4860 6830 + 6910 3730 6910 4830 Wire Wire Line - 4860 6830 4660 6830 + 6910 4830 6710 4830 Wire Wire Line - 5160 5730 4860 5730 -Text Label 5160 5730 0 48 ~ 0 + 7210 3730 6910 3730 +Text Label 7210 3730 0 48 ~ 0 FPGA_PROM_SCLK Wire Wire Line - 9770 6600 9150 6600 -Text Label 9150 6600 0 48 ~ 0 + 11820 4600 11200 4600 +Text Label 11200 4600 0 48 ~ 0 FPGA_PROM_MOSI Wire Wire Line - 4960 6930 4660 6930 + 7010 4930 6710 4930 Wire Wire Line - 4960 5830 4960 6930 + 7010 3830 7010 4930 Wire Wire Line - 4960 5830 4660 5830 + 7010 3830 6710 3830 Wire Wire Line - 5160 5830 4960 5830 -Text Label 5160 5830 0 48 ~ 0 + 7210 3830 7010 3830 +Text Label 7210 3830 0 48 ~ 0 FPGA_PROM_MOSI Wire Wire Line - 7700 6300 7600 6300 + 9750 4300 9650 4300 Wire Wire Line - 7600 6100 7600 6300 + 9650 4100 9650 4300 Wire Wire Line - 7600 6300 6900 6300 -Text Label 6900 6300 0 48 ~ 0 + 9650 4300 8950 4300 +Text Label 8950 4300 0 48 ~ 0 FPGA_PROM_CS_N Wire Wire Line - 4760 6730 4660 6730 + 6810 4730 6710 4730 Wire Wire Line - 4760 5630 4760 6730 + 6810 3630 6810 4730 Wire Wire Line - 4760 5630 4660 5630 + 6810 3630 6710 3630 Wire Wire Line - 5160 5630 4760 5630 -Text Label 5160 5630 0 48 ~ 0 + 7210 3630 6810 3630 +Text Label 7210 3630 0 48 ~ 0 FPGA_PROM_CS_N Wire Wire Line - 7700 6400 6900 6400 -Text Label 6900 6400 0 48 ~ 0 + 9750 4400 8950 4400 +Text Label 8950 4400 0 48 ~ 0 FPGA_PROM_MISO Wire Wire Line - 3660 5930 3560 5930 + 5710 3930 5610 3930 Wire Wire Line - 3560 5930 2980 5930 + 5610 3930 5030 3930 Wire Wire Line - 3660 7030 3560 7030 + 5710 5030 5610 5030 Wire Wire Line - 3560 5930 3560 7030 -Text Label 2980 5930 0 48 ~ 0 + 5610 3930 5610 5030 +Text Label 5030 3930 0 48 ~ 0 FPGA_PROM_MISO Wire Wire Line - 7700 6500 6700 6500 + 9750 4500 8750 4500 Wire Wire Line - 6700 6500 6700 6700 -Text Label 6900 6500 0 48 ~ 0 + 8750 4500 8750 4700 +Text Label 8950 4500 0 48 ~ 0 FPGA_PROM_W_N Wire Wire Line - 7000 9500 6700 9500 -Text GLabel 6700 9500 0 48 Input ~ 0 + 9050 7500 8750 7500 +Text GLabel 8750 7500 0 48 Input ~ 0 FPGA_GCLK Wire Wire Line - 6200 9300 6100 9300 + 8250 7300 8150 7300 Wire Wire Line - 6200 8900 6200 9300 + 8250 6900 8250 7300 Wire Wire Line - 6200 8900 5800 8900 + 8250 6900 7850 6900 Wire Wire Line - 3660 6830 3090 6830 -Text GLabel 3090 6830 0 48 Input ~ 0 + 5710 4830 5140 4830 +Text GLabel 5140 4830 0 48 Input ~ 0 FPGA_CFG_SCLK Wire Wire Line - 3660 6930 3090 6930 -Text GLabel 3090 6930 0 48 Input ~ 0 + 5710 4930 5140 4930 +Text GLabel 5140 4930 0 48 Input ~ 0 FPGA_CFG_MOSI Wire Wire Line - 3660 6730 3090 6730 -Text GLabel 3090 6730 0 48 Input ~ 0 + 5710 4730 5140 4730 +Text GLabel 5140 4730 0 48 Input ~ 0 FPGA_CFG_CS_N Wire Wire Line - 5160 7030 4660 7030 -Text GLabel 5160 7030 2 48 Output ~ 0 + 7210 5030 6710 5030 +Text GLabel 7210 5030 2 48 Output ~ 0 FPGA_CFG_MISO Wire Wire Line - 3660 5630 2980 5630 -Text GLabel 2980 5630 0 48 Input ~ 0 + 5710 3630 5030 3630 +Text GLabel 5030 3630 0 48 Input ~ 0 ARM_FPGA_CFG_CS_N Wire Wire Line - 3660 5830 2980 5830 -Text GLabel 2980 5830 0 48 Input ~ 0 + 5710 3830 5030 3830 +Text GLabel 5030 3830 0 48 Input ~ 0 ARM_FPGA_CFG_MOSI Wire Wire Line - 5160 5930 4660 5930 -Text GLabel 5160 5930 2 48 Output ~ 0 + 7210 3930 6710 3930 +Text GLabel 7210 3930 2 48 Output ~ 0 ARM_FPGA_CFG_MISO Wire Wire Line - 3660 5730 2980 5730 -Text GLabel 2980 5730 0 48 Input ~ 0 + 5710 3730 5030 3730 +Text GLabel 5030 3730 0 48 Input ~ 0 ARM_FPGA_CFG_SCLK -Text Label 3360 5510 1 48 ~ 0 +Text Label 5410 3510 1 48 ~ 0 SPI_A_TRISTATE -Text Label 3060 7230 0 48 ~ 0 +Text Label 5110 5230 0 48 ~ 0 SPI_B_TRISTATE -Text GLabel 430 6430 0 48 Input ~ 0 +Text GLabel 2480 4430 0 48 Input ~ 0 FPGA_CFG_CTRL_FPGA_DIS Wire Wire Line - 6300 9500 6100 9500 -Text Notes 5320 9730 0 54 ~ 11 + 8350 7500 8150 7500 +Text Notes 7370 7730 0 54 ~ 11 GND -Text Notes 5320 9330 0 54 ~ 11 +Text Notes 7370 7330 0 54 ~ 11 VCC -Text Notes 5760 9660 0 54 ~ 11 +Text Notes 7810 7660 0 54 ~ 11 FO -Text Notes 5750 9300 0 54 ~ 11 +Text Notes 7800 7300 0 54 ~ 11 OE -Text Notes 1890 6120 0 60 ~ 12 +Text Notes 3940 4120 0 60 ~ 12 1 -Text Notes 2190 6120 0 60 ~ 12 +Text Notes 4240 4120 0 60 ~ 12 2 -Text Notes 1890 6220 0 60 ~ 12 +Text Notes 3940 4220 0 60 ~ 12 3 -Text Notes 2190 6220 0 60 ~ 12 +Text Notes 4240 4220 0 60 ~ 12 4 -Text Notes 1890 6320 0 60 ~ 12 +Text Notes 3940 4320 0 60 ~ 12 5 -Text Notes 2190 6320 0 60 ~ 12 +Text Notes 4240 4320 0 60 ~ 12 6 Wire Wire Line - 3360 4900 3360 6130 + 5410 2900 5410 4130 Wire Wire Line - 2960 7230 2960 7430 + 5010 5230 5010 5430 Wire Wire Line - 3660 7230 2960 7230 + 5710 5230 5010 5230 Wire Wire Line - 2960 6230 2960 7230 + 5010 4230 5010 5230 Wire Wire Line - 2360 6230 2960 6230 + 4410 4230 5010 4230 Wire Wire Line - 1560 6430 430 6430 + 3610 4430 2480 4430 Wire Wire Line - 1560 6230 1560 6430 + 3610 4230 3610 4430 Wire Wire Line - 1760 6230 1560 6230 + 3810 4230 3610 4230 Wire Wire Line - 1640 6830 420 6830 + 3690 4830 2470 4830 Wire Wire Line - 1640 6330 1640 6830 + 3690 4330 3690 4830 Wire Wire Line - 1760 6330 1640 6330 + 3810 4330 3690 4330 Wire Wire Line - 2710 6330 2360 6330 + 4760 4330 4410 4330 Wire Wire Line - 2710 4420 2710 6330 + 4760 2420 4760 4330 Wire Wire Line - 3360 4420 2710 4420 -Text Label 420 6830 0 48 ~ 0 + 5410 2420 4760 2420 +Text Label 2470 4830 0 48 ~ 0 FPGA_PROM_W_N Wire Wire Line - 3360 6130 2360 6130 + 5410 4130 4410 4130 Wire Wire Line - 3660 6130 3360 6130 + 5710 4130 5410 4130 Wire Wire Line - 430 6130 1760 6130 -Text GLabel 430 6130 0 48 Input ~ 0 + 2480 4130 3810 4130 +Text GLabel 2480 4130 0 48 Input ~ 0 FPGA_CFG_CTRL_ARM_ENA -Connection ~ 3360 4420 +Connection ~ 5410 2420 $Comp L Cryptech_Alpha:N25Q128A13ES IC3 U 1 1 58023F42 -P 8400 6550 -F 0 "IC3" H 7890 6290 60 0000 L BNN -F 1 "N25Q128A13ESE*" H 8100 6920 60 0000 L BNN -F 2 "Cryptech_Alpha_Footprints:SO08" H 8100 6920 60 0001 C CNN -F 3 "" H 8100 6920 60 0000 C CNN - 1 8400 6550 +P 10450 4550 +F 0 "IC3" H 9940 4290 60 0000 L BNN +F 1 "N25Q128A13ESE*" H 10150 4920 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO08" H 10150 4920 60 0001 C CNN +F 3 "" H 10150 4920 60 0000 C CNN + 1 10450 4550 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R4 U 1 1 58023F41 -P 6500 9500 -F 0 "R4" H 6610 9645 60 0000 R TNN -F 1 "0" H 6460 9660 60 0000 R TNN -F 2 "Cryptech_Alpha_Footprints:R_0402" H 6460 9660 60 0001 C CNN -F 3 "" H 6460 9660 60 0000 C CNN - 1 6500 9500 +P 8550 7500 +F 0 "R4" H 8660 7645 60 0000 R TNN +F 1 "0" H 8510 7660 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8510 7660 60 0001 C CNN +F 3 "" H 8510 7660 60 0000 C CNN + 1 8550 7500 -1 0 0 1 $EndComp $Comp L Cryptech_Alpha:74*244DW_NEW IC2 U 1 1 58023F40 -P 4160 5830 -F 0 "IC2" H 3830 5300 60 0000 L BNN -F 1 "MC74AC244DW*" H 3850 5300 60 0000 L BNN -F 2 "Cryptech_Alpha_Footprints:SO20W" H 3850 5300 60 0001 C CNN -F 3 "" H 3850 5300 60 0000 C CNN - 1 4160 5830 +P 6210 3830 +F 0 "IC2" H 5880 3300 60 0000 L BNN +F 1 "MC74AC244DW*" H 5900 3300 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5900 3300 60 0001 C CNN +F 3 "" H 5900 3300 60 0000 C CNN + 1 6210 3830 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:74*244DW_NEW IC2 U 2 1 58023F3F -P 4160 6930 -F 0 "IC2" H 3830 6400 60 0000 L BNN -F 1 "MC74AC244DW*" H 3860 6390 60 0000 L BNN -F 2 "Cryptech_Alpha_Footprints:SO20W" H 3860 6390 60 0001 C CNN -F 3 "" H 3860 6390 60 0000 C CNN - 2 4160 6930 +P 6210 4930 +F 0 "IC2" H 5880 4400 60 0000 L BNN +F 1 "MC74AC244DW*" H 5910 4390 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 5910 4390 60 0001 C CNN +F 3 "" H 5910 4390 60 0000 C CNN + 2 6210 4930 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:74*244DW_NEW IC2 U 3 1 58023F3E -P 1660 5130 -F 0 "IC2" H 1690 4980 60 0000 L BNN -F 1 "MC74AC244DW*" H 1860 5110 60 0000 L BNN -F 2 "Cryptech_Alpha_Footprints:SO20W" H 1860 5110 60 0001 C CNN -F 3 "" H 1860 5110 60 0000 C CNN - 3 1660 5130 +P 3710 3130 +F 0 "IC2" H 3740 2980 60 0000 L BNN +F 1 "MC74AC244DW*" H 3910 3110 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:SO20W" H 3910 3110 60 0001 C CNN +F 3 "" H 3910 3110 60 0000 C CNN + 3 3710 3130 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:ASF* Q5 U 1 1 58023F3D -P 5600 9500 -F 0 "Q5" H 5270 9070 60 0000 L BNN -F 1 "ASFL1-50.000MHZ-EK-T" H 5080 9830 60 0000 L BNN -F 2 "Cryptech_Alpha_Footprints:ASF" H 5080 9830 60 0001 C CNN -F 3 "" H 5080 9830 60 0000 C CNN - 1 5600 9500 +P 7650 7500 +F 0 "Q5" H 7320 7070 60 0000 L BNN +F 1 "ASFL1-50.000MHZ-EK-T" H 7130 7830 60 0000 L BNN +F 2 "Cryptech_Alpha_Footprints:ASF" H 7130 7830 60 0001 C CNN +F 3 "" H 7130 7830 60 0000 C CNN + 1 7650 7500 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:M03X2NO_SILK JP7 U 1 1 58023F3C -P 2060 6230 -F 0 "JP7" H 1850 5920 60 0000 L BNN -F 1 "~" H 2060 6230 50 0001 C CNN -F 2 "Cryptech_Alpha_Footprints:PLD-6" H 1850 5920 60 0001 C CNN -F 3 "" H 2060 6230 50 0001 C CNN - 1 2060 6230 +P 4110 4230 +F 0 "JP7" H 3900 3920 60 0000 L BNN +F 1 "~" H 4110 4230 50 0001 C CNN +F 2 "Cryptech_Alpha_Footprints:PLD-6" H 3900 3920 60 0001 C CNN +F 3 "" H 4110 4230 50 0001 C CNN + 1 4110 4230 1 0 0 -1 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R51 U 1 1 58023F3B -P 7600 5900 -F 0 "R51" V 7510 5855 60 0000 R TNN -F 1 "4.7k" V 7510 5810 60 0000 R TNN -F 2 "Cryptech_Alpha_Footprints:R_0402" H 7510 5810 60 0001 C CNN -F 3 "" H 7510 5810 60 0000 C CNN - 1 7600 5900 +P 9650 3900 +F 0 "R51" V 9560 3855 60 0000 R TNN +F 1 "4.7k" V 9560 3810 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 9560 3810 60 0001 C CNN +F 3 "" H 9560 3810 60 0000 C CNN + 1 9650 3900 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:R-EU_R0402 R50 U 1 1 58023F3A -P 6700 6900 -F 0 "R50" V 6610 6855 60 0000 R TNN -F 1 "4.7k" V 6620 6800 60 0000 R TNN -F 2 "Cryptech_Alpha_Footprints:R_0402" H 6620 6800 60 0001 C CNN -F 3 "" H 6620 6800 60 0000 C CNN - 1 6700 6900 +P 8750 4900 +F 0 "R50" V 8660 4855 60 0000 R TNN +F 1 "4.7k" V 8670 4800 60 0000 R TNN +F 2 "Cryptech_Alpha_Footprints:R_0402" H 8670 4800 60 0001 C CNN +F 3 "" H 8670 4800 60 0000 C CNN + 1 8750 4900 0 -1 -1 0 $EndComp $Comp L Cryptech_Alpha:C-EUC0402 C111 U 1 1 58023F39 -P 4400 9600 -F 0 "C111" H 4480 9410 60 0000 L BNN -F 1 "~" H 4400 9600 50 0001 C CNN -F 2 "Cryptech_Alpha_Footprints:C_0402" H 4480 9410 60 0001 C CNN -F 3 "" H 4400 9600 50 0001 C CNN - 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