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-rw-r--r--KiCAD/rev02_13.sch-bak170
1 files changed, 84 insertions, 86 deletions
diff --git a/KiCAD/rev02_13.sch-bak b/KiCAD/rev02_13.sch-bak
index cf36ec9..597028e 100644
--- a/KiCAD/rev02_13.sch-bak
+++ b/KiCAD/rev02_13.sch-bak
@@ -1,9 +1,9 @@
EESchema Schematic File Version 4
-EELAYER 26 0
+EELAYER 30 0
EELAYER END
$Descr B 17000 11000
encoding utf-8
-Sheet 15 27
+Sheet 14 27
Title "rev02_13"
Date "15 10 2016"
Rev ""
@@ -17,11 +17,11 @@ Text Notes 1100 4300 0 60 ~ 12
*) Configuration Interface
Text Notes 1000 8700 0 60 ~ 12
M[2:0] == 3'b001 => Master SPI
-Text Notes 700 7400 0 60 ~ 12
+Text Notes 700 7400 0 60 ~ 12
*) Since VCCO is 3.3V, CFGBVS must be tied High.\n*) Battery is not used\n*) PROG_B is dedicated input -- can be driven by STM32 directly\n*) INIT_B is bi-directional open-drain, must be driven with MOSFET to ground
Text Notes 3700 9800 0 60 ~ 12
*) "Not DONE" LED, should be of red color
-Text Notes 8590 10210 0 54 ~ 12
+Text Notes 8590 10210 0 54 ~ 11
FPGA configuration interface
Text Notes 1600 9380 0 60 ~ 12
R35
@@ -42,10 +42,10 @@ U13
Text Notes 1050 6300 0 60 ~ 12
XC7A200TFBG484
$Comp
-L power:GND GND_92
+L power:GND #GND_092
U 1 1 58023F77
P 2200 6300
-F 0 "GND_92" H 2200 6300 20 0000 C CNN
+F 0 "#GND_092" H 2200 6300 20 0000 C CNN
F 1 "+GND" H 2200 6230 30 0000 C CNN
F 2 "" H 2200 6300 70 0000 C CNN
F 3 "" H 2200 6300 70 0000 C CNN
@@ -53,10 +53,10 @@ F 3 "" H 2200 6300 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_93
+L power:GND #GND_093
U 1 1 58023F76
P 1500 9800
-F 0 "GND_93" H 1500 9800 20 0000 C CNN
+F 0 "#GND_093" H 1500 9800 20 0000 C CNN
F 1 "+GND" H 1500 9730 30 0000 C CNN
F 2 "" H 1500 9800 70 0000 C CNN
F 3 "" H 1500 9800 70 0000 C CNN
@@ -64,10 +64,10 @@ F 3 "" H 1500 9800 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_94
+L power:GND #GND_094
U 1 1 58023F75
P 2300 9800
-F 0 "GND_94" H 2300 9800 20 0000 C CNN
+F 0 "#GND_094" H 2300 9800 20 0000 C CNN
F 1 "+GND" H 2300 9730 30 0000 C CNN
F 2 "" H 2300 9800 70 0000 C CNN
F 3 "" H 2300 9800 70 0000 C CNN
@@ -75,10 +75,10 @@ F 3 "" H 2300 9800 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_95
+L power:GND #GND_095
U 1 1 58023F74
P 5800 6400
-F 0 "GND_95" H 5800 6400 20 0000 C CNN
+F 0 "#GND_095" H 5800 6400 20 0000 C CNN
F 1 "+GND" H 5800 6330 30 0000 C CNN
F 2 "" H 5800 6400 70 0000 C CNN
F 3 "" H 5800 6400 70 0000 C CNN
@@ -86,10 +86,10 @@ F 3 "" H 5800 6400 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_96
+L power:GND #GND_096
U 1 1 58023F73
P 6600 6400
-F 0 "GND_96" H 6600 6400 20 0000 C CNN
+F 0 "#GND_096" H 6600 6400 20 0000 C CNN
F 1 "+GND" H 6600 6330 30 0000 C CNN
F 2 "" H 6600 6400 70 0000 C CNN
F 3 "" H 6600 6400 70 0000 C CNN
@@ -97,10 +97,10 @@ F 3 "" H 6600 6400 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_97
+L power:GND #GND_097
U 1 1 58023F72
P 9100 9300
-F 0 "GND_97" H 9100 9300 20 0000 C CNN
+F 0 "#GND_097" H 9100 9300 20 0000 C CNN
F 1 "+GND" H 9100 9230 30 0000 C CNN
F 2 "" H 9100 9300 70 0000 C CNN
F 3 "" H 9100 9300 70 0000 C CNN
@@ -108,10 +108,10 @@ F 3 "" H 9100 9300 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L power:GND GND_98
+L power:GND #GND_098
U 1 1 58023F71
P 7700 9300
-F 0 "GND_98" H 7700 9300 20 0000 C CNN
+F 0 "#GND_098" H 7700 9300 20 0000 C CNN
F 1 "+GND" H 7700 9230 30 0000 C CNN
F 2 "" H 7700 9300 70 0000 C CNN
F 3 "" H 7700 9300 70 0000 C CNN
@@ -119,10 +119,10 @@ F 3 "" H 7700 9300 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_21
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_021
U 1 1 58023F70
P 3100 8200
-F 0 "VCCO_3V3_21" H 3100 8200 20 0000 C CNN
+F 0 "#VCCO_3V3_021" H 3100 8200 20 0000 C CNN
F 1 "+VCCO_3V3" H 3100 8130 30 0000 C CNN
F 2 "" H 3100 8200 70 0000 C CNN
F 3 "" H 3100 8200 70 0000 C CNN
@@ -130,10 +130,10 @@ F 3 "" H 3100 8200 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_22
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_022
U 1 1 58023F6F
P 4700 8200
-F 0 "VCCO_3V3_22" H 4700 8200 20 0000 C CNN
+F 0 "#VCCO_3V3_022" H 4700 8200 20 0000 C CNN
F 1 "+VCCO_3V3" H 4700 8130 30 0000 C CNN
F 2 "" H 4700 8200 70 0000 C CNN
F 3 "" H 4700 8200 70 0000 C CNN
@@ -141,10 +141,10 @@ F 3 "" H 4700 8200 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_23
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_023
U 1 1 58023F6E
P 7700 8200
-F 0 "VCCO_3V3_23" H 7700 8200 20 0000 C CNN
+F 0 "#VCCO_3V3_023" H 7700 8200 20 0000 C CNN
F 1 "+VCCO_3V3" H 7700 8130 30 0000 C CNN
F 2 "" H 7700 8200 70 0000 C CNN
F 3 "" H 7700 8200 70 0000 C CNN
@@ -152,10 +152,10 @@ F 3 "" H 7700 8200 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_24
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_024
U 1 1 58023F6D
P 9100 7400
-F 0 "VCCO_3V3_24" H 9100 7400 20 0000 C CNN
+F 0 "#VCCO_3V3_024" H 9100 7400 20 0000 C CNN
F 1 "+VCCO_3V3" H 9100 7330 30 0000 C CNN
F 2 "" H 9100 7400 70 0000 C CNN
F 3 "" H 9100 7400 70 0000 C CNN
@@ -163,10 +163,10 @@ F 3 "" H 9100 7400 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_25
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_025
U 1 1 58023F6C
P 2400 4500
-F 0 "VCCO_3V3_25" H 2400 4500 20 0000 C CNN
+F 0 "#VCCO_3V3_025" H 2400 4500 20 0000 C CNN
F 1 "+VCCO_3V3" H 2400 4430 30 0000 C CNN
F 2 "" H 2400 4500 70 0000 C CNN
F 3 "" H 2400 4500 70 0000 C CNN
@@ -174,10 +174,10 @@ F 3 "" H 2400 4500 70 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L Cryptech_Alpha:VCCO_3V3 VCCO_3V3_26
+L Cryptech_Alpha:VCCO_3V3 #VCCO_3V3_026
U 1 1 58023F6B
P 6000 4100
-F 0 "VCCO_3V3_26" H 6000 4100 20 0000 C CNN
+F 0 "#VCCO_3V3_026" H 6000 4100 20 0000 C CNN
F 1 "+VCCO_3V3" H 6000 4030 30 0000 C CNN
F 2 "" H 6000 4100 70 0000 C CNN
F 3 "" H 6000 4100 70 0000 C CNN
@@ -265,65 +265,57 @@ Connection ~ 2400 4800
Connection ~ 2400 4900
Wire Wire Line
3400 5700 2000 5700
-Text Label 3400 5700 2 48 ~ 0
+Text Label 3400 5700 2 48 ~ 0
FPGA_M2
Wire Wire Line
1500 9000 1500 9200
Wire Wire Line
- 1500 9000 900 9000
-Text Label 900 9000 0 48 ~ 0
+ 1500 9000 900 9000
+Text Label 900 9000 0 48 ~ 0
FPGA_M2
Wire Wire Line
3400 5800 2000 5800
-Text Label 3400 5800 2 48 ~ 0
+Text Label 3400 5800 2 48 ~ 0
FPGA_JTAG_TCK
-Text Label 8430 8500 0 48 ~
+Text Label 8430 8500 0 48 ~ 0
FPGA_JTAG_TCK
Wire Wire Line
3400 5900 2000 5900
-Text Label 3400 5900 2 48 ~ 0
+Text Label 3400 5900 2 48 ~ 0
FPGA_JTAG_TDI
Wire Wire Line
- 9000 8700 8800 8700
-Wire Wire Line
9300 8700 9000 8700
-Wire Wire Line
- 8800 8700 8430 8700
-Text Label 8430 8700 0 48 ~
+Text Label 8430 8700 0 48 ~ 0
FPGA_JTAG_TDI
Wire Wire Line
3400 6000 2000 6000
-Text Label 3400 6000 2 48 ~ 0
+Text Label 3400 6000 2 48 ~ 0
FPGA_JTAG_TDO
Wire Wire Line
9300 8800 8430 8800
-Text Label 8430 8800 0 48 ~
+Text Label 8430 8800 0 48 ~ 0
FPGA_JTAG_TDO
Wire Wire Line
3400 6100 2000 6100
-Text Label 3400 6100 2 48 ~ 0
+Text Label 3400 6100 2 48 ~ 0
FPGA_JTAG_TMS
Wire Wire Line
- 9100 8600 8900 8600
-Wire Wire Line
9300 8600 9100 8600
-Wire Wire Line
- 8900 8600 8430 8600
-Text Label 8430 8600 0 48 ~
+Text Label 8430 8600 0 48 ~ 0
FPGA_JTAG_TMS
Wire Wire Line
6200 4900 6200 5100
Wire Wire Line
7600 5100 6200 5100
-Text GLabel 7600 5100 2 48 Input ~ 0
+Text GLabel 7600 5100 2 48 Input ~ 0
FPGA_PROGRAM_B
Wire Wire Line
3940 5300 3240 5300
-Text GLabel 3940 5300 2 48 Input ~ 0
+Text GLabel 3940 5300 2 48 Input ~ 0
FPGA_PROGRAM_B
Wire Wire Line
3400 5100 2000 5100
-Text Label 3400 5100 2 48 ~ 0
+Text Label 3400 5100 2 48 ~ 0
FPGA_DONE_INT
Wire Wire Line
4700 9400 4700 9500
@@ -331,28 +323,28 @@ Wire Wire Line
4700 9500 3700 9500
Wire Wire Line
5000 9500 4700 9500
-Text Label 3700 9500 0 48 ~
+Text Label 3700 9500 0 48 ~ 0
FPGA_DONE_INT
Connection ~ 4700 9500
Wire Wire Line
3400 5500 2000 5500
-Text Label 3400 5500 2 48 ~ 0
+Text Label 3400 5500 2 48 ~ 0
FPGA_M0
Wire Wire Line
3100 9000 2500 9000
Wire Wire Line
3100 8800 3100 9000
-Text Label 2500 9000 0 48 ~ 0
+Text Label 2500 9000 0 48 ~ 0
FPGA_M0
Wire Wire Line
3400 5600 2000 5600
-Text Label 3400 5600 2 48 ~ 0
+Text Label 3400 5600 2 48 ~ 0
FPGA_M1
Wire Wire Line
2300 9000 1700 9000
Wire Wire Line
2300 9000 2300 9200
-Text Label 1700 9000 0 48 ~ 0
+Text Label 1700 9000 0 48 ~ 0
FPGA_M1
Wire Wire Line
5800 4900 5800 5400
@@ -360,12 +352,12 @@ Wire Wire Line
5800 5400 4800 5400
Wire Wire Line
6000 5400 5800 5400
-Text Label 4800 5400 0 48 ~
+Text Label 4800 5400 0 48 ~ 0
FPGA_INIT_B_INT
Connection ~ 5800 5400
Wire Wire Line
3940 5200 3240 5200
-Text Label 3940 5200 2 48 ~ 0
+Text Label 3940 5200 2 48 ~ 0
FPGA_INIT_B_INT
Wire Wire Line
6600 5600 6400 5600
@@ -373,30 +365,30 @@ Wire Wire Line
6600 5600 6600 5800
Wire Wire Line
7600 5600 6600 5600
-Text GLabel 7600 5600 2 48 BiDi ~ 0
+Text GLabel 7600 5600 2 48 BiDi ~ 0
FPGA_INIT_B
Connection ~ 6600 5600
Wire Wire Line
4700 8900 4700 9100
Wire Wire Line
5700 9500 5400 9500
-Text GLabel 5700 9500 2 48 Output ~ 0
+Text GLabel 5700 9500 2 48 Output ~ 0
FPGA_DONE
Wire Wire Line
3940 5400 3240 5400
-Text GLabel 3940 5400 2 48 Output ~ 0
+Text GLabel 3940 5400 2 48 Output ~ 0
FPGA_CFG_SCLK
Wire Wire Line
2840 5200 2000 5200
-Text Label 2220 5200 0 48 ~
+Text Label 2220 5200 0 48 ~ 0
FPGA_INIT_B_INT1
Wire Wire Line
2840 5300 2000 5300
-Text Label 2220 5300 0 48 ~
+Text Label 2220 5300 0 48 ~ 0
FPGA_PROGRAM_B1
Wire Wire Line
2840 5400 2000 5400
-Text Label 2220 5400 0 48 ~
+Text Label 2220 5400 0 48 ~ 0
FPGA_CFG_SCLK1
Wire Wire Line
9100 8600 9100 8200
@@ -420,7 +412,7 @@ F 1 "1k" V 1430 9310 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 1430 9310 60 0001 C CNN
F 3 "" H 1430 9310 60 0000 C CNN
1 1500 9400
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R39
@@ -431,7 +423,7 @@ F 1 "100" H 5220 9650 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 5220 9650 60 0001 C CNN
F 3 "" H 5220 9650 60 0000 C CNN
1 5200 9500
- -1 0 0 1
+ -1 0 0 1
$EndComp
$Comp
L Cryptech_Alpha:MA08-1 SV1
@@ -442,7 +434,7 @@ F 1 "MA08-1" H 9560 9330 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:PLS-8" H 9560 9330 60 0001 C CNN
F 3 "" H 9560 9330 60 0000 C CNN
1 9600 8700
- -1 0 0 1
+ -1 0 0 1
$EndComp
$Comp
L Cryptech_Alpha:C-EUC0402 C108
@@ -453,7 +445,7 @@ F 1 "0.1uF" H 7860 8710 60 0000 L BNN
F 2 "Cryptech_Alpha_Footprints:C_0402" H 7860 8710 60 0001 C CNN
F 3 "" H 7860 8710 60 0000 C CNN
1 7700 8800
- 1 0 0 -1
+ 1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R43
@@ -464,7 +456,7 @@ F 1 "10k" V 9170 7450 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7450 60 0001 C CNN
F 3 "" H 9170 7450 60 0000 C CNN
1 9000 8000
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R44
@@ -475,7 +467,7 @@ F 1 "10k" V 9170 7550 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7550 60 0001 C CNN
F 3 "" H 9170 7550 60 0000 C CNN
1 9100 8000
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R45
@@ -486,7 +478,7 @@ F 1 "10k" V 9170 7650 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 9170 7650 60 0001 C CNN
F 3 "" H 9170 7650 60 0000 C CNN
1 9200 8000
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0603 R62
@@ -497,7 +489,7 @@ F 1 "0" H 2940 4890 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 4890 60 0001 C CNN
F 3 "" H 2940 4890 60 0000 C CNN
1 3040 5200
- -1 0 0 1
+ -1 0 0 1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0603 R63
@@ -508,7 +500,7 @@ F 1 "0" H 2940 4950 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 4950 60 0001 C CNN
F 3 "" H 2940 4950 60 0000 C CNN
1 3040 5300
- -1 0 0 1
+ -1 0 0 1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0603 R71
@@ -519,16 +511,18 @@ F 1 "0" H 2940 5020 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 2940 5020 60 0001 C CNN
F 3 "" H 2940 5020 60 0000 C CNN
1 3040 5400
- -1 0 0 1
+ -1 0 0 1
$EndComp
$Comp
L Cryptech_Alpha:XC7A200TFBG484_1 U13
U 1 1 58023F60
P 1800 5400
F 0 "U13" H 1390 4490 60 0000 L BNN
- 1 1800 5400
- 1 0 0 -1
+F 1 "~" H 1800 5400 50 0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 1390 4490 60 0001 C CNN
+F 3 "" H 1800 5400 50 0001 C CNN
+ 1 1800 5400
+ 1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R36
@@ -539,7 +533,7 @@ F 1 "1k" V 2240 9310 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 2240 9310 60 0001 C CNN
F 3 "" H 2240 9310 60 0000 C CNN
1 2300 9400
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R37
@@ -550,7 +544,7 @@ F 1 "1k" V 3060 8460 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 3060 8460 60 0001 C CNN
F 3 "" H 3060 8460 60 0000 C CNN
1 3100 8600
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R41
@@ -561,7 +555,7 @@ F 1 "4.7k" V 6190 4550 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 6190 4550 60 0001 C CNN
F 3 "" H 6190 4550 60 0000 C CNN
1 6200 4700
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R40
@@ -572,7 +566,7 @@ F 1 "4.7k" V 5780 5050 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 5780 5050 60 0001 C CNN
F 3 "" H 5780 5050 60 0000 C CNN
1 5800 4700
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:2N7002 Q4
@@ -583,7 +577,7 @@ F 1 "2N7002P,235" H 6420 5655 60 0000 R BNN
F 2 "Cryptech_Alpha_Footprints:SOT-23" H 6420 5655 60 0001 C CNN
F 3 "" H 6420 5655 60 0000 C CNN
1 6200 5500
- -1 0 0 -1
+ -1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R42
@@ -594,7 +588,7 @@ F 1 "4.7k" V 6470 5850 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 6470 5850 60 0001 C CNN
F 3 "" H 6470 5850 60 0000 C CNN
1 6600 6000
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
$Comp
L Cryptech_Alpha:LEDCHIP-LED0603 LED13
@@ -605,7 +599,7 @@ F 1 "LTST-C191KRKT" H 4820 9075 60 0000 L BNN
F 2 "Cryptech_Alpha_Footprints:VD_0603" H 4820 9075 60 0001 C CNN
F 3 "" H 4820 9075 60 0000 C CNN
1 4700 9200
- 1 0 0 -1
+ 1 0 0 -1
$EndComp
$Comp
L Cryptech_Alpha:R-EU_R0402 R38
@@ -616,6 +610,10 @@ F 1 "330" V 4670 8560 60 0000 R TNN
F 2 "Cryptech_Alpha_Footprints:R_0402" H 4670 8560 60 0001 C CNN
F 3 "" H 4670 8560 60 0000 C CNN
1 4700 8700
- 0 -1 -1 0
+ 0 -1 -1 0
$EndComp
-$EndSCHEMATC \ No newline at end of file
+Wire Wire Line
+ 8430 8700 9000 8700
+Wire Wire Line
+ 8430 8600 9100 8600
+$EndSCHEMATC