diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:50:56 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:50:56 +0300 |
commit | f66f8e0815ed28ab80065a381fcecb27bc4f8c66 (patch) | |
tree | 15d6d53d816c84aaeeb0aa226ab48b83abb17732 /helper | |
parent | 92d06b7fc8649d046e8a29b84fd58d91bdfe2178 (diff) |
Okay, capacitor parameters (tolerance, rated voltage, dielectric) were lost
too. This is too painful to type in manually, so I created a simple script to
make all the capacitors 10% 50V X7R. This way I can then manually edit those,
that differ.
Diffstat (limited to 'helper')
-rw-r--r-- | helper/repair_capacitors.py | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/helper/repair_capacitors.py b/helper/repair_capacitors.py new file mode 100644 index 0000000..2000f01 --- /dev/null +++ b/helper/repair_capacitors.py @@ -0,0 +1,94 @@ +# +# quick and dirty script to add tolerance, voltage & dielectric fields to all the capacitors +# +import os +import re + +from enum import IntEnum + +PROJ_DIR_SRC = "./KiCAD_SRC" +PROJ_DIR_DST = "./KiCAD_DST" + +class State(IntEnum): + Idle = 0 + SeenComp = 1 + WaitField = 2 + +def find_pages(): + print("Finding pages...") + pgs = [] + fs = os.listdir(PROJ_DIR_SRC) + re_sch = re.compile("^rev04_\d+.sch$") + for f in fs: + f_is_sch = re.match(re_sch, f) + if f_is_sch is None: continue + print(" page '%s'" % f) + pgs.append(f) + return pgs + + +def repair_caps(pgs): + # + #$Comp + #L Cryptech_Alpha:C-EUC1210 C2 + #U 1 1 580240C1 + #P 4000 7200 + #F 0 "C2" H 4080 7010 60 0000 L BNN + #F 1 "10uF" H 4000 7200 50 0001 C CNN + #F 2 "Cryptech_Alpha_Footprints:C_1210" H 4080 7010 60 0001 C CNN + #F 3 "" H 4000 7200 50 0001 C CNN + # + #F 4 "10%" H 4000 7200 50 0001 C CNN "Tolerance" + #F 5 "50V" H 4000 7200 50 0001 C CNN "Voltage" + #F 6 "X7R" H 4000 7200 50 0001 C CNN "Dielectric" + # + # 1 4000 7200 + # 1 0 0 -1 + #$EndComp # + # + print("Processing pages...") + re_refdes_c = re.compile("^L \S+ C\d+$") + re_f3 = re.compile("^F 3 \"\" H (\d{4,5}) (\d{4,5}) (\d{2}) (\d{4}) C CNN$") + for pg in pgs: + print(" '%s'" % pg) + fls_new = [] + with open("%s/%s" % (PROJ_DIR_SRC, pg), 'r') as f: + fls = f.readlines() + state = State.Idle + for i in range(len(fls)): + flsi = fls[i] + fls_new.append(flsi) + fl = flsi.strip() + if state == State.Idle: + if fl == '$Comp': + state = State.SeenComp + continue + elif state == State.SeenComp: + mc = re.match(re_refdes_c, fl) + if not mc is None: + print(" %s" % fl) + state = State.WaitField + continue + else: + state = State.Idle + continue + elif state == State.WaitField: + mf3 = re.match(re_f3, fl) + if not mf3 is None: + print(" %s" % fl) + fls_new.append('F 4 "10%%" H %s %s %s %s C CNN "Tolerance"\n' % (mf3.group(1), mf3.group(2), mf3.group(3), mf3.group(4))) + fls_new.append('F 5 "25V" H %s %s %s %s C CNN "Voltage"\n' % (mf3.group(1), mf3.group(2), mf3.group(3), mf3.group(4))) + fls_new.append('F 6 "X7R" H %s %s %s %s C CNN "Dielectric"\n' % (mf3.group(1), mf3.group(2), mf3.group(3), mf3.group(4))) + state = State.Idle + continue + elif fl == '$EndComp': + raise RuntimeError + else: + raise RuntimeError + with open("%s/%s" % (PROJ_DIR_DST, pg), 'w') as f: + f.writelines(fls_new) + + +if __name__ == "__main__": + repair_caps(find_pages()) +
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