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//======================================================================

`timescale 1ns / 1ps

module modexpa7_buffer_core
  #(parameter OPERAND_ADDR_WIDTH      =  5)     // 1024 / 32 = 32 -> 5 bits
   (
    input wire                        clk,

    input wire [OPERAND_ADDR_WIDTH:0] rw_coeff_bram_addr,
    input wire                        rw_coeff_bram_wr,
    input wire [31:0]                 rw_coeff_bram_in,
    output wire [31:0]                rw_coeff_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] rw_mm_bram_addr,
    input wire                        rw_mm_bram_wr,
    input wire [31:0]                 rw_mm_bram_in,
    output wire [31:0]                rw_mm_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] rw_nn_bram_addr,
    input wire                        rw_nn_bram_wr,
    input wire [31:0]                 rw_nn_bram_in,

    input wire [OPERAND_ADDR_WIDTH:0] rw_y_bram_addr,
    input wire                        rw_y_bram_wr,
    input wire [31:0]                 rw_y_bram_in,
    output wire [31:0]                rw_y_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] rw_r_bram_addr,
    input wire                        rw_r_bram_wr,
    input wire [31:0]                 rw_r_bram_in,
    output wire [31:0]                rw_r_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] rw_t_bram_addr,
    input wire                        rw_t_bram_wr,
    input wire [31:0]                 rw_t_bram_in,
    output wire [31:0]                rw_t_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] ro_coeff_bram_addr,
    output wire [31:0]                ro_coeff_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] ro_mm_bram_addr,
    output wire [31:0]                ro_mm_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] ro_nn_bram_addr,
    output wire [31:0]                ro_nn_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] ro_r_bram_addr,
    output wire [31:0]                ro_r_bram_out,

    input wire [OPERAND_ADDR_WIDTH:0] ro_t_bram_addr,
    output wire [31:0]                ro_t_bram_out
    );


   //
   // Montgomery Coefficient
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_coeff
     (
      .clk              (clk),

      .a_addr           (rw_coeff_bram_addr),
      .a_wr             (rw_coeff_bram_wr),
      .a_in             (rw_coeff_bram_in),
      .a_out            (rw_coeff_bram_out),

      .b_addr           (ro_coeff_bram_addr),
      .b_out            (ro_coeff_bram_out)
      );


   //
   // Powers of Message
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_mm
     (
      .clk              (clk),

      .a_addr           (rw_mm_bram_addr),
      .a_wr             (rw_mm_bram_wr),
      .a_in             (rw_mm_bram_in),
      .a_out            (rw_mm_bram_out),

      .b_addr           (ro_mm_bram_addr),
      .b_out            (ro_mm_bram_out)
      );


   //
   // Extended Modulus
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_nn
     (
      .clk              (clk),

      .a_addr           (rw_nn_bram_addr),
      .a_wr             (rw_nn_bram_wr),
      .a_in             (rw_nn_bram_in),
      .a_out            (),

      .b_addr           (ro_nn_bram_addr),
      .b_out            (ro_nn_bram_out)
      );


   //
   // Output
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_y
     (
      .clk              (clk),

      .a_addr           (rw_y_bram_addr),
      .a_wr             (rw_y_bram_wr),
      .a_in             (rw_y_bram_in),
      .a_out            (rw_y_bram_out),

      .b_addr           ({(OPERAND_ADDR_WIDTH+1){1'b0}}),
      .b_out            ()
      );


   //
   // Result of Multiplication
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_r
     (
      .clk              (clk),

      .a_addr           (rw_r_bram_addr),
      .a_wr             (rw_r_bram_wr),
      .a_in             (rw_r_bram_in),
      .a_out            (rw_r_bram_out),

      .b_addr           (ro_r_bram_addr),
      .b_out            (ro_r_bram_out)
      );


   //
   // Temporary Buffer
   //
   ram_1rw_1ro_readfirst #
     (
      .MEM_WIDTH        (32),
      .MEM_ADDR_BITS    (OPERAND_ADDR_WIDTH+1)
      )
   mem_t
     (
      .clk              (clk),

      .a_addr           (rw_t_bram_addr),
      .a_wr             (rw_t_bram_wr),
      .a_in             (rw_t_bram_in),
      .a_out            (rw_t_bram_out),

      .b_addr           (ro_t_bram_addr),
      .b_out            (ro_t_bram_out)
      );


endmodule