From 2c92500715a13e017ae7e792ba8283c91a716b7d Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Wed, 1 Jun 2016 10:44:54 +0300
Subject: Ported ModExpS6 core to the new Alpha platform, hence the core now
 becomes ModExpA7.

Note, that the core takes advantage of built-in DSP slices available in 7-Series FPGAs.
This considerably speeds up computations, because the core can operate in 32-bit-word-serial
mode instead of just bit-serial mode. The core directly instantiates DSP slices instead of
using IP wizard to avoid using CoreGen during console bitstream builds.
---
 rtl/dsp_subtractor_a7.v | 142 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 142 insertions(+)
 create mode 100644 rtl/dsp_subtractor_a7.v

(limited to 'rtl/dsp_subtractor_a7.v')

diff --git a/rtl/dsp_subtractor_a7.v b/rtl/dsp_subtractor_a7.v
new file mode 100644
index 0000000..00c2f95
--- /dev/null
+++ b/rtl/dsp_subtractor_a7.v
@@ -0,0 +1,142 @@
+//======================================================================
+//
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module dsp_subtractor_a7
+	(
+	input		[31: 0]	a,
+	input		[31: 0]	b,
+	output	[31: 0]	s,
+	input					c_in,
+	output				c_out
+	);
+
+	wire	[47: 0]	p;
+	assign s = p[31:0];
+	assign c_out = p[32];
+
+	DSP48E1 #
+	(
+		.AREG						(0),
+		.BREG						(0),
+		.CREG						(0),
+		.DREG						(0),
+		.MREG						(0),
+		.PREG						(0),
+		.ADREG					(0),
+		.ACASCREG				(0),
+		.BCASCREG				(0),
+		.ALUMODEREG				(0),
+		.INMODEREG				(0),
+		.OPMODEREG				(0),
+		.CARRYINREG				(0),
+		.CARRYINSELREG			(0),
+
+		.A_INPUT					("DIRECT"),
+		.B_INPUT					("DIRECT"),
+		.USE_DPORT				("FALSE"),
+		.USE_MULT				("NONE"),
+		.USE_SIMD				("ONE48"),
+
+		.USE_PATTERN_DETECT	("NO_PATDET"),
+		.SEL_PATTERN			("PATTERN"),
+		.SEL_MASK				("MASK"),
+		.PATTERN					(48'h000000000000),
+		.MASK						(48'h3fffffffffff),
+		.AUTORESET_PATDET		("NO_RESET")
+	)
+	DSP48E1_inst
+	(
+		.CLK					(1'b0),
+
+		.RSTA					(1'b0),
+		.RSTB					(1'b0),
+		.RSTC					(1'b0),
+		.RSTD					(1'b0),
+		.RSTM					(1'b0),
+		.RSTP					(1'b0),
+
+		.RSTCTRL				(1'b0),
+		.RSTINMODE			(1'b0),
+		.RSTALUMODE			(1'b0),
+		.RSTALLCARRYIN		(1'b0),
+
+		.CEA1					(1'b0),
+		.CEA2					(1'b0),
+		.CEB1					(1'b0),
+		.CEB2					(1'b0),
+		.CEC					(1'b0),
+		.CED					(1'b0),
+		.CEM					(1'b0),
+		.CEP					(1'b0),
+		.CEAD					(1'b0),
+		.CEALUMODE			(1'b0),
+		.CEINMODE			(1'b0),
+
+		.CECTRL				(1'b0),
+		.CECARRYIN			(1'b0),
+
+		.A						({{16{1'b0}}, b[31:18]}),
+		.B						(b[17: 0]),
+		.C						({{16{1'b0}}, a[31:0]}),
+		.D						(25'd0),
+		.P						(p),
+
+		.CARRYIN				(c_in),
+		.CARRYOUT			(),
+		.CARRYINSEL			(3'b000),
+
+		.CARRYCASCIN		(1'b0),
+		.CARRYCASCOUT		(),
+
+		.PATTERNDETECT		(),
+		.PATTERNBDETECT	(),
+
+		.OPMODE				(7'b0110011),
+		.ALUMODE				(4'b0011),
+		.INMODE				(5'b00000),
+
+		.MULTSIGNIN			(1'b0),
+		.MULTSIGNOUT		(),
+
+		.UNDERFLOW			(),
+		.OVERFLOW			(),
+
+		.ACIN					(30'd0),
+		.BCIN					(18'd0),
+		.PCIN					(48'd0),
+
+		.ACOUT				(),
+		.BCOUT				(),
+		.PCOUT				()
+  );
+ 
+endmodule
-- 
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