aboutsummaryrefslogtreecommitdiff
path: root/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
blob: 350de24e4aacc28e4104ef4f637fb62d392c09c0 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
/**
  ******************************************************************************
  * @file    stm32f4xx_hal_pwr.h
  * @author  MCD Application Team
  * @version V1.0.0
  * @date    18-February-2014
  * @brief   Header file of PWR HAL module.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_PWR_H
#define __STM32F4xx_HAL_PWR_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"

/** @addtogroup STM32F4xx_HAL_Driver
  * @{
  */

/** @addtogroup PWR
  * @{
  */ 

/* Exported types ------------------------------------------------------------*/
/**
  * @brief  PWR PVD configuration structure definition
  */
typedef struct
{
  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level
                            This parameter can be a value of @ref PWR_PVD_detection_level */

  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
                           This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;

/* Exported constants --------------------------------------------------------*/
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET      (PWR_BASE - PERIPH_BASE)

/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET       (PWR_OFFSET + 0x00)
#define DBP_BitNumber   0x08
#define CR_DBP_BB       (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))

/* Alias word address of PVDE bit */
#define PVDE_BitNumber  0x04
#define CR_PVDE_BB      (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))

/* Alias word address of FPDS bit */
#define FPDS_BitNumber  0x09
#define CR_FPDS_BB      (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))

/* Alias word address of PMODE bit */
#define PMODE_BitNumber 0x0E
#define CR_PMODE_BB     (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))

/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET      (PWR_OFFSET + 0x04)
#define EWUP_BitNumber  0x08
#define CSR_EWUP_BB     (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))

/* Alias word address of BRE bit */
#define BRE_BitNumber   0x09
#define CSR_BRE_BB      (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
   
/** @defgroup PWR_Exported_Constants
  * @{
  */
 
/** @defgroup PWR_WakeUp_Pins
  * @{
  */

#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP
#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
/**
  * @}
  */

/** @defgroup PWR_PVD_detection_level 
  * @{
  */ 
#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
/**
  * @}
  */   
 
/** @defgroup PWR_PVD_Mode 
  * @{
  */
#define  PWR_MODE_EVT                  ((uint32_t)0x00000000)   /*!< No Interrupt */
#define  PWR_MODE_IT_RISING            ((uint32_t)0x00000001)   /*!< External Interrupt Mode with Rising edge trigger detection */
#define  PWR_MODE_IT_FALLING           ((uint32_t)0x00000002)   /*!< External Interrupt Mode with Falling edge trigger detection */
#define  PWR_MODE_IT_RISING_FALLING    ((uint32_t)0x00000003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
                               ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
/**
  * @}
  */ 

/** @defgroup PWR_Regulator_state_in_STOP_mode 
  * @{
  */
#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS

#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
/**
  * @}
  */
    
/** @defgroup PWR_SLEEP_mode_entry 
  * @{
  */
#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/**
  * @}
  */

/** @defgroup PWR_STOP_mode_entry 
  * @{
  */
#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
  * @}
  */

/** @defgroup PWR_Regulator_Voltage_Scale 
  * @{
  */
#define PWR_REGULATOR_VOLTAGE_SCALE1    ((uint32_t)0x0000C000)
#define PWR_REGULATOR_VOLTAGE_SCALE2    ((uint32_t)0x00008000)
#define PWR_REGULATOR_VOLTAGE_SCALE3    ((uint32_t)0x00004000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/**
  * @}
  */

/** @defgroup PWR_Flag 
  * @{
  */
#define PWR_FLAG_WU                     PWR_CSR_WUF
#define PWR_FLAG_SB                     PWR_CSR_SBF
#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
#define PWR_FLAG_BRR                    PWR_CSR_BRR
#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY

/**
  * @}
  */

/**
  * @}
  */ 
  
/* Exported macro ------------------------------------------------------------*/

/** @brief  macros configure the main internal regulator output voltage.
  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
  *         a tradeoff between performance and power consumption when the device does
  *         not operate at the maximum frequency (refer to the datasheets for more details).
  *          This parameter can be one of the following values:
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
  * @retval None
  */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))

/** @brief  Check PWR flag is set or not.
  * @param  __FLAG__: specifies the flag to check.
  *           This parameter can be one of the following values:
  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
  *                  An additional wakeup event is detected if the WKUP pin is enabled 
  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
  *                  resumed from StandBy mode.    
  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
  *                  For this reason, this bit is equal to 0 after Standby or reset
  *                  until the PVDE bit is set.
  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
  *                  when the device wakes up from Standby mode or by a system reset 
  *                  or power reset.  
  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
  *                 scaling output selection is ready.
  * @retval The new state of __FLAG__ (TRUE or FALSE).
  */
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))

/** @brief  Clear the PWR's pending flags.
  * @param  __FLAG__: specifies the flag to clear.
  *          This parameter can be one of the following values:
  *            @arg PWR_FLAG_WU: Wake Up flag
  *            @arg PWR_FLAG_SB: StandBy flag
  */
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2)

#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
  * @brief Enable the PVD Exti Line.
  * @param  __EXTILINE__: specifies the PVD Exti sources to be enabled.
  * This parameter can be:
  *   @arg PWR_EXTI_LINE_PVD     
  * @retval None.
  */
#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__)   (EXTI->IMR |= (__EXTILINE__))

/**
  * @brief Disable the PVD EXTI Line.
  * @param  __EXTILINE__: specifies the PVD EXTI sources to be disabled.
  * This parameter can be:
  *  @arg PWR_EXTI_LINE_PVD    
  * @retval None.
  */
#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__)  (EXTI->IMR &= ~(__EXTILINE__))

/**
  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
  * @param  __EXTILINE__: specifies the PVD Exti sources to be cleared.
  * This parameter can be:
  *   @arg PWR_EXTI_LINE_PVD  
  * @retval EXTI PVD Line Status.
  */
#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__)  (EXTI->PR & (__EXTILINE__))

/**
  * @brief Clear the PVD Exti flag.
  * @param  __EXTILINE__: specifies the PVD Exti sources to be cleared.
  * This parameter can be:
  *   @arg PWR_EXTI_LINE_PVD  
  * @retval None.
  */
#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__)  (EXTI->PR = (__EXTILINE__))


/* Include PWR HAL Extension module */
#include "stm32f4xx_hal_pwr_ex.h"

/* Exported functions --------------------------------------------------------*/

/* Initialization and de-initialization functions *******************************/
void        HAL_PWR_DeInit(void);
void        HAL_PWR_EnableBkUpAccess(void);
void        HAL_PWR_DisableBkUpAccess(void);

/* Peripheral Control functions  ************************************************/
void        HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
void        HAL_PWR_EnablePVD(void);
void        HAL_PWR_DisablePVD(void);
void        HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
void        HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);

void        HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void        HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void        HAL_PWR_EnterSTANDBYMode(void);

void        HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);


/**
  * @}
  */ 

/**
  * @}
  */
  
#ifdef __cplusplus
}
#endif


#endif /* __STM32F4xx_HAL_PWR_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
vided with the distribution. // // - Neither the name of the NORDUnet nor the names of its contributors may // be used to endorse or promote products derived from this software // without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED // TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== module tb_keywrap(); parameter DEBUG = 0; parameter DUMP_TOP = 0; parameter DUMP_CORE = 0; parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; // API for the core. localparam ADDR_NAME0 = 8'h00; localparam ADDR_NAME1 = 8'h01; localparam ADDR_VERSION = 8'h02; localparam ADDR_CTRL = 8'h08; localparam CTRL_INIT_BIT = 0; localparam CTRL_NEXT_BIT = 1; localparam ADDR_STATUS = 8'h09; localparam STATUS_READY_BIT = 0; localparam STATUS_VALID_BIT = 1; localparam ADDR_CONFIG = 8'h0a; localparam CTRL_ENCDEC_BIT = 0; localparam CTRL_KEYLEN_BIT = 1; localparam ADDR_RLEN = 8'h0c; localparam ADDR_R_BANK = 8'h0d; localparam ADDR_A0 = 8'h0e; localparam ADDR_A1 = 8'h0f; localparam ADDR_KEY0 = 8'h10; localparam ADDR_KEY1 = 8'h11; localparam ADDR_KEY2 = 8'h12; localparam ADDR_KEY3 = 8'h13; localparam ADDR_KEY4 = 8'h14; localparam ADDR_KEY5 = 8'h15; localparam ADDR_KEY6 = 8'h16; localparam ADDR_KEY7 = 8'h17; localparam ADDR_R_DATA0 = 8'h80; localparam ADDR_R_DATA127 = 8'hff; localparam DUT_ASPACE = 12; //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- reg [31 : 0] cycle_ctr; reg [31 : 0] error_ctr; reg [31 : 0] tc_ctr; reg [31 : 0] read_data; reg [127 : 0] result_data; reg tb_clk; reg tb_reset_n; reg tb_cs; reg tb_we; reg [(DUT_ASPACE - 1) : 0] tb_address; reg [31 : 0] tb_write_data; wire [31 : 0] tb_read_data; wire tb_error; //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- keywrap dut( .clk(tb_clk), .reset_n(tb_reset_n), .cs(tb_cs), .we(tb_we), .address(tb_address), .write_data(tb_write_data), .read_data(tb_read_data), .error(tb_error) ); //---------------------------------------------------------------- // clk_gen // // Always running clock generator process. //---------------------------------------------------------------- always begin : clk_gen #CLK_HALF_PERIOD; tb_clk = !tb_clk; end // clk_gen //---------------------------------------------------------------- // sys_monitor() // // An always running process that creates a cycle counter and // conditionally displays information about the DUT. //---------------------------------------------------------------- always begin : sys_monitor cycle_ctr = cycle_ctr + 1; if (DEBUG) dump_dut_state(); #(CLK_PERIOD); end //---------------------------------------------------------------- // read_word() // // Read a data word from the given address in the DUT. // the word read will be available in the global variable // read_data. //---------------------------------------------------------------- task read_word(input [11 : 0] address); begin tb_address = address; tb_cs = 1; tb_we = 0; #(CLK_PERIOD); read_data = tb_read_data; tb_cs = 0; if (DEBUG) begin $display("*** Reading 0x%08x from 0x%02x.", read_data, address); $display(""); end end endtask // read_word //---------------------------------------------------------------- // write_word() // // Write the given word to the DUT using the DUT interface. //---------------------------------------------------------------- task write_word(input [11 : 0] address, input [31 : 0] word); begin if (DEBUG) begin $display("*** Writing 0x%08x to 0x%02x.", word, address); $display(""); end tb_address = address; tb_write_data = word; tb_cs = 1; tb_we = 1; #(1 * CLK_PERIOD); tb_cs = 0; tb_we = 0; end endtask // write_word //---------------------------------------------------------------- // wait_ready // // Wait for the DUT to signal that the result is ready //---------------------------------------------------------------- task wait_ready; begin : wait_ready reg rdy; rdy = 1'b0; while (rdy != 1'b1) begin read_word(ADDR_STATUS); rdy = tb_read_data[STATUS_READY_BIT]; end end endtask // wait_ready //---------------------------------------------------------------- // dump_mem() // // Dump the n first memory positions in the dut internal memory. //---------------------------------------------------------------- task dump_mem(input integer n); begin : dump_mem integer i; for (i = 0 ; i < n ; i = i + 1) $display("mem0[0x%06x] = 0x%08x mem1[0x%06x] = 0x%08x", i, dut.core.mem.mem0[i], i, dut.core.mem.mem1[i]); $display(""); end endtask // dump_mem //---------------------------------------------------------------- // dump_dut_state() // // Dump the state of the dump when needed. //---------------------------------------------------------------- task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); $display("------------"); if (DUMP_TOP) begin $display("top level state:"); $display("init_reg = 0x%x next_reg = 0x%x", dut.init_reg, dut.next_reg); $display("endec_reg = 0x%x keylen_reg = 0x%x", dut.encdec_reg, dut.keylen_reg); $display("rlen_reg = 0x%06x r_bank_reg = 0x%06x", dut.rlen_reg, dut.r_bank_reg); $display("a0_reg = 0x%08x a1_reg = 0x%08x", dut.a0_reg, dut.a1_reg); $display(""); end if (DUMP_CORE) begin $display("core level state:"); $display("init = 0x%0x next = 0x%0x ready = 0x%0x valid = 0x%0x", dut.core.init, dut.core.next, dut.core.ready, dut.core.valid); $display("api_we = 0x%0x api_addr = 0x%0x api_wr_data = 0x%0x api_rd_data = 0x%0x", dut.core.api_we, dut.core.api_addr, dut.core.api_wr_data, dut.core.api_rd_data); $display("rlen = 0x%0x", dut.core.rlen); $display("key = 0x%0x", dut.core.key); $display("a_init = 0x%0x a_result = 0x%0x", dut.core.a_init, dut.core.a_result); $display(""); $display("update_state = 0x%0x", dut.core.update_state); $display("a_reg = 0x%0x a_new = 0x%0x a_we = 0x%0x", dut.core.a_reg, dut.core.a_new, dut.core.a_we); $display("core_we = 0x%0x core_addr = 0x%0x", dut.core.core_we, dut.core.core_addr); $display("core_rd_data = 0x%0x core_wr_data = 0x%0x ", dut.core.core_rd_data, dut.core.core_wr_data); $display("xor_val = 0x%0x", dut.core.keywrap_logic.xor_val); $display(""); $display("aes_ready = 0x%0x aes_valid = 0x%0x", dut.core.aes_ready, dut.core.aes_valid); $display("aes_init = 0x%0x aes_next = 0x%0x", dut.core.aes_init, dut.core.aes_next); $display("aes_block = 0x%0x aes_result = 0x%0x", dut.core.aes_block, dut.core.aes_result); $display(""); $display("block_ctr_reg = 0x%0x iteration_ctr_reg = 0x%0x", dut.core.block_ctr_reg, dut.core.iteration_ctr_reg); $display("keywrap_core_ctrl_reg = 0x%0x", dut.core.keywrap_core_ctrl_reg); $display("keywrap_core_ctrl_new = 0x%0x", dut.core.keywrap_core_ctrl_new); $display("keywrap_core_ctrl_we = 0x%0x", dut.core.keywrap_core_ctrl_we); end $display(""); $display(""); end endtask // dump_dut_state //---------------------------------------------------------------- // display_test_results() // // Display the accumulated test results. //---------------------------------------------------------------- task display_test_results; begin if (error_ctr == 0) begin $display("*** All %02d test cases completed successfully", tc_ctr); end else begin $display("*** %02d tests completed - %02d test cases did not complete successfully.", tc_ctr, error_ctr); end end endtask // display_test_results //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- task init_sim; begin cycle_ctr = 0; error_ctr = 0; tc_ctr = 0; tb_clk = 0; tb_reset_n = 1; tb_cs = 0; tb_we = 0; tb_address = 8'h0; tb_write_data = 32'h0; end endtask // init_sim //---------------------------------------------------------------- // reset_dut() // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- task reset_dut; begin $display("** Toggling reset."); tb_reset_n = 0; #(2 * CLK_PERIOD); tb_reset_n = 1; $display(""); end endtask // reset_dut //---------------------------------------------------------------- // test_core_access // Simple test that we can perform read access to regs // in the core. //---------------------------------------------------------------- task test_core_access; begin : test_core_access $display("** TC test_core_access START."); read_word(ADDR_NAME0); $display("NAME0: %s", read_data); read_word(ADDR_NAME1); $display("NAME1: %s", read_data); read_word(ADDR_VERSION); $display("version: %s", read_data); $display(""); $display("** TC test_core_access END."); end endtask // test_core_access //---------------------------------------------------------------- // test_kwp_ae_128_1 // Implements wrap test based on NIST KWP_AE 128 bit key // with 248 bit plaintext. //---------------------------------------------------------------- task test_kwp_ae_128_1; begin : kwp_ae_128_1 integer i; tc_ctr = tc_ctr + 1; $display("** TC kwp_ae_128_1 START."); // Write key and keylength, we also want to encrypt/wrap. write_word(ADDR_KEY0, 32'hc03db3cc); write_word(ADDR_KEY1, 32'h1416dcd1); write_word(ADDR_KEY2, 32'hc069a195); write_word(ADDR_KEY3, 32'ha8d77e3d); write_word(ADDR_CONFIG, 32'h00000001); // Initialize the AES engine (to expand the key). // Wait for init to complete. // Note, not actually needed to wait. We can write R data during init. $display("* Trying to initialize."); write_word(ADDR_CTRL, 32'h00000001); #(2 * CLK_PERIOD); wait_ready(); $display("* Init should be done."); // Set the length or R in blocks. // Write the R bank to be written to. // Write the R blocks to be processed. write_word(ADDR_RLEN, 32'h00000004); write_word(ADDR_R_BANK, 32'h0); write_word(ADDR_R_DATA0 + 0, 32'h46f87f58); write_word(ADDR_R_DATA0 + 1, 32'hcdda4200); write_word(ADDR_R_DATA0 + 2, 32'hf53d99ce); write_word(ADDR_R_DATA0 + 3, 32'h2e49bdb7); write_word(ADDR_R_DATA0 + 4, 32'h6212511f); write_word(ADDR_R_DATA0 + 5, 32'he0cd4d0b); write_word(ADDR_R_DATA0 + 6, 32'h5f37a27d); write_word(ADDR_R_DATA0 + 7, 32'h45a28800); // Write magic words to A. write_word(ADDR_A0, 32'ha65959a6); write_word(ADDR_A1, 32'h0000001f); $display("* Contents of memory and dut before wrap processing:"); dump_mem(6); // Start wrapping and wait for wrap to complete. $display("* Trying to start processing."); write_word(ADDR_CTRL, 32'h00000002); #(2 * CLK_PERIOD); wait_ready(); $display("* Processing should be done."); $display("Contents of memory and dut after wrap processing:"); dump_mem(6); dump_dut_state(); // Read and display the A registers. read_word(ADDR_A0); $display("A0 after wrap: 0x%08x", read_data); read_word(ADDR_A1); $display("A1 after wrap: 0x%08x", read_data); // Read and display the R blocks that has been processed. for (i = 0 ; i < 8 ; i = i + 1) begin read_word(ADDR_R_DATA0 + i); $display("mem[0x%07x] = 0x%08x", i, read_data); end $display("** TC kwp_ae_128_2 END.\n"); end endtask // test_kwp_ae_128_2 //---------------------------------------------------------------- // test_kwp_ad_128_1 // Implements unwrap test based on NIST KWP_AE 128 bit key // with 248 bit plaintext. //---------------------------------------------------------------- task test_kwp_ad_128_1; begin : kwp_ad_128_1 integer i; tc_ctr = tc_ctr + 1; $display("** TC kwp_ad_128_1 START."); // Write key and keylength, we also want to decrypt/unwrap. write_word(ADDR_KEY0, 32'hc03db3cc); write_word(ADDR_KEY1, 32'h1416dcd1); write_word(ADDR_KEY2, 32'hc069a195); write_word(ADDR_KEY3, 32'ha8d77e3d); write_word(ADDR_CONFIG, 32'h00000000); // Initialize the AES engine (to expand the key). // Wait for init to complete. // Note, not actually needed to wait. We can write R data during init. $display("* Trying to initialize."); write_word(ADDR_CTRL, 32'h00000001); #(2 * CLK_PERIOD); wait_ready(); $display("* Init should be done."); // Set the length or R in blocks. // Write the R bank to be written to. // Write the R blocks to be processed. write_word(ADDR_RLEN, 32'h00000004); write_word(ADDR_R_BANK, 32'h0); write_word(ADDR_R_DATA0 + 0, 32'h59a69492); write_word(ADDR_R_DATA0 + 1, 32'hbb7e2cd0); write_word(ADDR_R_DATA0 + 2, 32'h0160d2eb); write_word(ADDR_R_DATA0 + 3, 32'hef9bf4d4); write_word(ADDR_R_DATA0 + 4, 32'heb16fbf7); write_word(ADDR_R_DATA0 + 5, 32'h98f1340f); write_word(ADDR_R_DATA0 + 6, 32'h6df6558a); write_word(ADDR_R_DATA0 + 7, 32'h4fb84cd0); // Write magic words to A. write_word(ADDR_A0, 32'h57e3b669); write_word(ADDR_A1, 32'h9c6e8177); $display("* Contents of memory and dut before unwrap processing:"); dump_mem(6); // Start unwrapping and wait for unwrap to complete. $display("* Trying to start processing."); write_word(ADDR_CTRL, 32'h00000002); #(2 * CLK_PERIOD); wait_ready(); $display("* Processing should be done."); $display("Contents of memory and dut after unwrap processing:"); dump_mem(6); dump_dut_state(); // Read and display the A registers. read_word(ADDR_A0); $display("A0 after unwrap: 0x%08x", read_data); read_word(ADDR_A1); $display("A1 after unwrap: 0x%08x", read_data); // Read and display the R blocks that has been processed. for (i = 0 ; i < 8 ; i = i + 1) begin read_word(ADDR_R_DATA0 + i); $display("mem[0x%07x] = 0x%08x", i, read_data); end $display("** TC kwp_ad_128_1 END.\n"); end endtask // test_kwp_ad_128_1 //---------------------------------------------------------------- // test_kwp_ae_128_2 // Implements wrap test based on NIST KWP_AE 128 bit key with // 4096 bit plaintext. //---------------------------------------------------------------- task test_kwp_ae_128_2; begin : kwp_ae_128_2 integer i; tc_ctr = tc_ctr + 1; $display("** TC kwp_ae_128_2 START."); // Write key and keylength, we also want to encrypt/wrap. write_word(ADDR_KEY0, 32'h6b8ba9cc); write_word(ADDR_KEY1, 32'h9b31068b); write_word(ADDR_KEY2, 32'ha175abfc); write_word(ADDR_KEY3, 32'hc60c1338); write_word(ADDR_CONFIG, 32'h00000001); // Initialize the AES engine (to expand the key). // Wait for init to complete. $display("* Trying to initialize."); write_word(ADDR_CTRL, 32'h00000001); #(2 * CLK_PERIOD); wait_ready(); $display("* Init should be done."); // Set the length or R in blocks. // Write the R bank to be written to. // Write the R blocks to be processed. write_word(ADDR_RLEN, 32'h00000040); write_word(ADDR_R_BANK, 32'h0); write_word(ADDR_R_DATA0 + 0, 32'h8af887c5); write_word(ADDR_R_DATA0 + 1, 32'h8dfbc38e); write_word(ADDR_R_DATA0 + 2, 32'he0423eef); write_word(ADDR_R_DATA0 + 3, 32'hcc0e032d); write_word(ADDR_R_DATA0 + 4, 32'hcc79dd11); write_word(ADDR_R_DATA0 + 5, 32'h6638ca65); write_word(ADDR_R_DATA0 + 6, 32'had75dca2); write_word(ADDR_R_DATA0 + 7, 32'ha2459f13); write_word(ADDR_R_DATA0 + 8, 32'h934dbe61); write_word(ADDR_R_DATA0 + 9, 32'ha62cb26d); write_word(ADDR_R_DATA0 + 10, 32'h8bbddbab); write_word(ADDR_R_DATA0 + 11, 32'hf9bf52bb); write_word(ADDR_R_DATA0 + 12, 32'he137ef1d); write_word(ADDR_R_DATA0 + 13, 32'h3e30eacf); write_word(ADDR_R_DATA0 + 14, 32'h0fe456ec); write_word(ADDR_R_DATA0 + 15, 32'h808d6798); write_word(ADDR_R_DATA0 + 16, 32'hdc29fe54); write_word(ADDR_R_DATA0 + 17, 32'hfa1f784a); write_word(ADDR_R_DATA0 + 18, 32'ha3c11cf3); write_word(ADDR_R_DATA0 + 19, 32'h94050095); write_word(ADDR_R_DATA0 + 20, 32'h81d3f1d5); write_word(ADDR_R_DATA0 + 21, 32'h96843813); write_word(ADDR_R_DATA0 + 22, 32'ha6685e50); write_word(ADDR_R_DATA0 + 23, 32'h3fac8535); write_word(ADDR_R_DATA0 + 24, 32'he0c06ecc); write_word(ADDR_R_DATA0 + 25, 32'ha8561b6a); write_word(ADDR_R_DATA0 + 26, 32'h1f22c578); write_word(ADDR_R_DATA0 + 27, 32'heefb6919); write_word(ADDR_R_DATA0 + 28, 32'h12be2e16); write_word(ADDR_R_DATA0 + 29, 32'h67946101); write_word(ADDR_R_DATA0 + 30, 32'hae8c3501); write_word(ADDR_R_DATA0 + 31, 32'he6c66eb1); write_word(ADDR_R_DATA0 + 32, 32'h7e14f260); write_word(ADDR_R_DATA0 + 33, 32'h8c9ce6fb); write_word(ADDR_R_DATA0 + 34, 32'hab4a1597); write_word(ADDR_R_DATA0 + 35, 32'hed49ccb3); write_word(ADDR_R_DATA0 + 36, 32'h930b1060); write_word(ADDR_R_DATA0 + 37, 32'hf98c97d8); write_word(ADDR_R_DATA0 + 38, 32'hdc4ce81e); write_word(ADDR_R_DATA0 + 39, 32'h35279c4d); write_word(ADDR_R_DATA0 + 40, 32'h30d1bf86); write_word(ADDR_R_DATA0 + 41, 32'hc9b919a3); write_word(ADDR_R_DATA0 + 42, 32'hce4f0109); write_word(ADDR_R_DATA0 + 43, 32'he77929e5); write_word(ADDR_R_DATA0 + 44, 32'h8c4c3aeb); write_word(ADDR_R_DATA0 + 45, 32'h5de1ec5e); write_word(ADDR_R_DATA0 + 46, 32'h0afa38ae); write_word(ADDR_R_DATA0 + 47, 32'h896df912); write_word(ADDR_R_DATA0 + 48, 32'h1c72c255); write_word(ADDR_R_DATA0 + 49, 32'h141f2f5c); write_word(ADDR_R_DATA0 + 50, 32'h9a51be50); write_word(ADDR_R_DATA0 + 51, 32'h72547cf8); write_word(ADDR_R_DATA0 + 52, 32'ha3b06740); write_word(ADDR_R_DATA0 + 53, 32'h4e62f961); write_word(ADDR_R_DATA0 + 54, 32'h5a02479c); write_word(ADDR_R_DATA0 + 55, 32'hf8c202e7); write_word(ADDR_R_DATA0 + 56, 32'hfeb2e258); write_word(ADDR_R_DATA0 + 57, 32'h314e0ebe); write_word(ADDR_R_DATA0 + 58, 32'h62878a5c); write_word(ADDR_R_DATA0 + 59, 32'h4ecd4e9d); write_word(ADDR_R_DATA0 + 60, 32'hf7dab2e1); write_word(ADDR_R_DATA0 + 61, 32'hfa9a7b53); write_word(ADDR_R_DATA0 + 62, 32'h2c2169ac); write_word(ADDR_R_DATA0 + 63, 32'hedb7998d); write_word(ADDR_R_DATA0 + 64, 32'h5cd8a711); write_word(ADDR_R_DATA0 + 65, 32'h8848ce7e); write_word(ADDR_R_DATA0 + 66, 32'he9fb2f68); write_word(ADDR_R_DATA0 + 67, 32'he28c2b27); write_word(ADDR_R_DATA0 + 68, 32'h9ddc064d); write_word(ADDR_R_DATA0 + 69, 32'hb70ad73c); write_word(ADDR_R_DATA0 + 70, 32'h6dbe10c5); write_word(ADDR_R_DATA0 + 71, 32'he1c56a70); write_word(ADDR_R_DATA0 + 72, 32'h9c1407f9); write_word(ADDR_R_DATA0 + 73, 32'h3a727cce); write_word(ADDR_R_DATA0 + 74, 32'h1075103a); write_word(ADDR_R_DATA0 + 75, 32'h4009ae2f); write_word(ADDR_R_DATA0 + 76, 32'h7731b7d7); write_word(ADDR_R_DATA0 + 77, 32'h1756eee1); write_word(ADDR_R_DATA0 + 78, 32'h19b828ef); write_word(ADDR_R_DATA0 + 79, 32'h4ed61eff); write_word(ADDR_R_DATA0 + 80, 32'h16493553); write_word(ADDR_R_DATA0 + 81, 32'h2a94fa8f); write_word(ADDR_R_DATA0 + 82, 32'he62dc2e2); write_word(ADDR_R_DATA0 + 83, 32'h2cf20f16); write_word(ADDR_R_DATA0 + 84, 32'h8ae65f4b); write_word(ADDR_R_DATA0 + 85, 32'h6785286c); write_word(ADDR_R_DATA0 + 86, 32'h253f365f); write_word(ADDR_R_DATA0 + 87, 32'h29453a47); write_word(ADDR_R_DATA0 + 88, 32'h9dc2824b); write_word(ADDR_R_DATA0 + 89, 32'h8bdabd96); write_word(ADDR_R_DATA0 + 90, 32'h2da3b76a); write_word(ADDR_R_DATA0 + 91, 32'he9c8a720); write_word(ADDR_R_DATA0 + 92, 32'h155e158f); write_word(ADDR_R_DATA0 + 93, 32'he389c8cc); write_word(ADDR_R_DATA0 + 94, 32'h7fa6ad52); write_word(ADDR_R_DATA0 + 95, 32'h2c951b5c); write_word(ADDR_R_DATA0 + 96, 32'h236bf964); write_word(ADDR_R_DATA0 + 97, 32'hb5b1bfb0); write_word(ADDR_R_DATA0 + 98, 32'h98a39835); write_word(ADDR_R_DATA0 + 99, 32'h759b9540); write_word(ADDR_R_DATA0 + 100, 32'h4b72b17f); write_word(ADDR_R_DATA0 + 101, 32'h7dbcda93); write_word(ADDR_R_DATA0 + 102, 32'h6177ae05); write_word(ADDR_R_DATA0 + 103, 32'h9269f41e); write_word(ADDR_R_DATA0 + 104, 32'hcdac81a4); write_word(ADDR_R_DATA0 + 105, 32'h9f5bbfd2); write_word(ADDR_R_DATA0 + 106, 32'he801392a); write_word(ADDR_R_DATA0 + 107, 32'h043ef068); write_word(ADDR_R_DATA0 + 108, 32'h73550a67); write_word(ADDR_R_DATA0 + 109, 32'hfcbc039f); write_word(ADDR_R_DATA0 + 110, 32'h0b5d30ce); write_word(ADDR_R_DATA0 + 111, 32'h490baa97); write_word(ADDR_R_DATA0 + 112, 32'h9dbbaf9e); write_word(ADDR_R_DATA0 + 113, 32'h53d45d7e); write_word(ADDR_R_DATA0 + 114, 32'h2dff26b2); write_word(ADDR_R_DATA0 + 115, 32'hf7e6628d); write_word(ADDR_R_DATA0 + 116, 32'hed694217); write_word(ADDR_R_DATA0 + 117, 32'ha39f454b); write_word(ADDR_R_DATA0 + 118, 32'h288e7906); write_word(ADDR_R_DATA0 + 119, 32'hb79faf4a); write_word(ADDR_R_DATA0 + 120, 32'h407a7d20); write_word(ADDR_R_DATA0 + 121, 32'h7646f930); write_word(ADDR_R_DATA0 + 122, 32'h96a157f0); write_word(ADDR_R_DATA0 + 123, 32'hd1dca05a); write_word(ADDR_R_DATA0 + 124, 32'h7f92e318); write_word(ADDR_R_DATA0 + 125, 32'hfc1ff62c); write_word(ADDR_R_DATA0 + 126, 32'he2de7f12); write_word(ADDR_R_DATA0 + 127, 32'h9b187053); // Write magic words to A. write_word(ADDR_A0, 32'ha65959a6); write_word(ADDR_A1, 32'h00000200); $display("* Contents of memory and dut before wrap processing:"); dump_mem(65); // Start wrapping and wait for wrap to complete. $display("* Trying to start processing."); write_word(ADDR_CTRL, 32'h00000002); #(2 * CLK_PERIOD); wait_ready(); $display("* Processing should be done."); $display("Contents of memory and dut after wrap processing:"); dump_mem(65); dump_dut_state(); // Read and display the A registers. read_word(ADDR_A0); $display("A0 after wrap: 0x%08x", read_data); read_word(ADDR_A1); $display("A1 after wrap: 0x%08x", read_data); // Read and display the R blocks that has been processed. for (i = 0 ; i < 128 ; i = i + 1) begin read_word(ADDR_R_DATA0 + i); $display("mem[0x%07x] = 0x%08x", i, read_data); end $display("** TC kwp_ae_128_2 END.\n"); end endtask // test_kwp_ae_128_2 //---------------------------------------------------------------- // test_kwp_ad_128_2 // Implements unwrap test based on NIST KWP_AD 128 bit key with // 4096 bit plaintext. //---------------------------------------------------------------- task test_kwp_ad_128_2; begin : kwp_ad_128_2 integer i; tc_ctr = tc_ctr + 1; $display("** TC kwp_ad_128_2 START."); // Write key and keylength, we also want to unwrap/decrypt. write_word(ADDR_KEY0, 32'h6b8ba9cc); write_word(ADDR_KEY1, 32'h9b31068b); write_word(ADDR_KEY2, 32'ha175abfc); write_word(ADDR_KEY3, 32'hc60c1338); write_word(ADDR_CONFIG, 32'h00000000); // Initialize the AES engine (to expand the key). // Wait for init to complete. $display("* Trying to initialize."); write_word(ADDR_CTRL, 32'h00000001); #(2 * CLK_PERIOD); wait_ready(); $display("* Init should be done."); // Set the length or R in blocks. // Write the R bank to be written to. // Write the R blocks to be processed. write_word(ADDR_RLEN, 32'h00000040); write_word(ADDR_R_BANK, 32'h0); write_word(ADDR_R_DATA0 + 0, 32'h4501c1ec); write_word(ADDR_R_DATA0 + 1, 32'hadc6b5e3); write_word(ADDR_R_DATA0 + 2, 32'hf1c23c29); write_word(ADDR_R_DATA0 + 3, 32'heca60890); write_word(ADDR_R_DATA0 + 4, 32'h5f9cabdd); write_word(ADDR_R_DATA0 + 5, 32'h46e34a55); write_word(ADDR_R_DATA0 + 6, 32'he1f7ac83); write_word(ADDR_R_DATA0 + 7, 32'h08e75c90); write_word(ADDR_R_DATA0 + 8, 32'h3675982b); write_word(ADDR_R_DATA0 + 9, 32'hda99173a); write_word(ADDR_R_DATA0 + 10, 32'h2ba57d2c); write_word(ADDR_R_DATA0 + 11, 32'hcf2e01a0); write_word(ADDR_R_DATA0 + 12, 32'h2589f89d); write_word(ADDR_R_DATA0 + 13, 32'hfd4b3c7f); write_word(ADDR_R_DATA0 + 14, 32'hd229ec91); write_word(ADDR_R_DATA0 + 15, 32'hc9d0c46e); write_word(ADDR_R_DATA0 + 16, 32'ha5dee3c0); write_word(ADDR_R_DATA0 + 17, 32'h48cd4611); write_word(ADDR_R_DATA0 + 18, 32'hbfeadc9b); write_word(ADDR_R_DATA0 + 19, 32'hf26daa1e); write_word(ADDR_R_DATA0 + 20, 32'h02cb72e2); write_word(ADDR_R_DATA0 + 21, 32'h22cf3dab); write_word(ADDR_R_DATA0 + 22, 32'h120dd1e8); write_word(ADDR_R_DATA0 + 23, 32'hc2dd9bd5); write_word(ADDR_R_DATA0 + 24, 32'h8bbefa5d); write_word(ADDR_R_DATA0 + 25, 32'h14526abd); write_word(ADDR_R_DATA0 + 26, 32'h1e8d2170); write_word(ADDR_R_DATA0 + 27, 32'ha6ba8283); write_word(ADDR_R_DATA0 + 28, 32'hc243ec2f); write_word(ADDR_R_DATA0 + 29, 32'hd5ef0703); write_word(ADDR_R_DATA0 + 30, 32'h0b1ef5f6); write_word(ADDR_R_DATA0 + 31, 32'h9f9620e4); write_word(ADDR_R_DATA0 + 32, 32'hb17a3639); write_word(ADDR_R_DATA0 + 33, 32'h34100588); write_word(ADDR_R_DATA0 + 34, 32'h7b9ffc79); write_word(ADDR_R_DATA0 + 35, 32'h35335947); write_word(ADDR_R_DATA0 + 36, 32'h03e5dcae); write_word(ADDR_R_DATA0 + 37, 32'h67bd0ce7); write_word(ADDR_R_DATA0 + 38, 32'ha3c98ca6); write_word(ADDR_R_DATA0 + 39, 32'h5815a4d0); write_word(ADDR_R_DATA0 + 40, 32'h67f27e6e); write_word(ADDR_R_DATA0 + 41, 32'h66d6636c); write_word(ADDR_R_DATA0 + 42, 32'hebb78973); write_word(ADDR_R_DATA0 + 43, 32'h2566a52a); write_word(ADDR_R_DATA0 + 44, 32'hc3970e14); write_word(ADDR_R_DATA0 + 45, 32'hc37310dc); write_word(ADDR_R_DATA0 + 46, 32'h2fcee0e7); write_word(ADDR_R_DATA0 + 47, 32'h39a16291); write_word(ADDR_R_DATA0 + 48, 32'h029fd2b4); write_word(ADDR_R_DATA0 + 49, 32'hd534e304); write_word(ADDR_R_DATA0 + 50, 32'h45474b26); write_word(ADDR_R_DATA0 + 51, 32'h711a8b3e); write_word(ADDR_R_DATA0 + 52, 32'h1ee3cc88); write_word(ADDR_R_DATA0 + 53, 32'hb09e8b17); write_word(ADDR_R_DATA0 + 54, 32'h45b6cc0f); write_word(ADDR_R_DATA0 + 55, 32'h067624ec); write_word(ADDR_R_DATA0 + 56, 32'hb232db75); write_word(ADDR_R_DATA0 + 57, 32'h0b01fe54); write_word(ADDR_R_DATA0 + 58, 32'h57fdea77); write_word(ADDR_R_DATA0 + 59, 32'hb251b10f); write_word(ADDR_R_DATA0 + 60, 32'he95d3eee); write_word(ADDR_R_DATA0 + 61, 32'hdb083bdf); write_word(ADDR_R_DATA0 + 62, 32'h109c41db); write_word(ADDR_R_DATA0 + 63, 32'ha26cc965); write_word(ADDR_R_DATA0 + 64, 32'h4f787bf9); write_word(ADDR_R_DATA0 + 65, 32'h5735ff07); write_word(ADDR_R_DATA0 + 66, 32'h070b175c); write_word(ADDR_R_DATA0 + 67, 32'hea8b6230); write_word(ADDR_R_DATA0 + 68, 32'h2e6087b9); write_word(ADDR_R_DATA0 + 69, 32'h1a041547); write_word(ADDR_R_DATA0 + 70, 32'h46056910); write_word(ADDR_R_DATA0 + 71, 32'h99f1a9e2); write_word(ADDR_R_DATA0 + 72, 32'hb626c4b3); write_word(ADDR_R_DATA0 + 73, 32'hbb7aeb8e); write_word(ADDR_R_DATA0 + 74, 32'had9922bc); write_word(ADDR_R_DATA0 + 75, 32'h3617cb42); write_word(ADDR_R_DATA0 + 76, 32'h7c669b88); write_word(ADDR_R_DATA0 + 77, 32'hbe5f98ae); write_word(ADDR_R_DATA0 + 78, 32'ha7edb8b0); write_word(ADDR_R_DATA0 + 79, 32'h063bec80); write_word(ADDR_R_DATA0 + 80, 32'haf4c081f); write_word(ADDR_R_DATA0 + 81, 32'h89778d7c); write_word(ADDR_R_DATA0 + 82, 32'h7242ddae); write_word(ADDR_R_DATA0 + 83, 32'h88e8d3af); write_word(ADDR_R_DATA0 + 84, 32'hf1f80e57); write_word(ADDR_R_DATA0 + 85, 32'h5e1aab4a); write_word(ADDR_R_DATA0 + 86, 32'h5d115bc2); write_word(ADDR_R_DATA0 + 87, 32'h7636fd14); write_word(ADDR_R_DATA0 + 88, 32'hd19bc594); write_word(ADDR_R_DATA0 + 89, 32'h33f69763); write_word(ADDR_R_DATA0 + 90, 32'h5ecd870d); write_word(ADDR_R_DATA0 + 91, 32'h17e7f5b0); write_word(ADDR_R_DATA0 + 92, 32'h04dee400); write_word(ADDR_R_DATA0 + 93, 32'h1cddc34a); write_word(ADDR_R_DATA0 + 94, 32'hb6e377ee); write_word(ADDR_R_DATA0 + 95, 32'hb3fb08e9); write_word(ADDR_R_DATA0 + 96, 32'h47697076); write_word(ADDR_R_DATA0 + 97, 32'h5105d93e); write_word(ADDR_R_DATA0 + 98, 32'h4558fe3d); write_word(ADDR_R_DATA0 + 99, 32'h4fc6fe05); write_word(ADDR_R_DATA0 + 100, 32'h3aab9c6c); write_word(ADDR_R_DATA0 + 101, 32'hf032f111); write_word(ADDR_R_DATA0 + 102, 32'h6e70c2d6); write_word(ADDR_R_DATA0 + 103, 32'h5f7c8cde); write_word(ADDR_R_DATA0 + 104, 32'hb6ad63ac); write_word(ADDR_R_DATA0 + 105, 32'h4291f93d); write_word(ADDR_R_DATA0 + 106, 32'h467ebbb2); write_word(ADDR_R_DATA0 + 107, 32'h9ead265c); write_word(ADDR_R_DATA0 + 108, 32'h05ac684d); write_word(ADDR_R_DATA0 + 109, 32'h20a6bef0); write_word(ADDR_R_DATA0 + 110, 32'h9b71830f); write_word(ADDR_R_DATA0 + 111, 32'h717e08bc); write_word(ADDR_R_DATA0 + 112, 32'hb4f9d377); write_word(ADDR_R_DATA0 + 113, 32'h3bec928f); write_word(ADDR_R_DATA0 + 114, 32'h66eeb64d); write_word(ADDR_R_DATA0 + 115, 32'hc451e958); write_word(ADDR_R_DATA0 + 116, 32'he357ebbf); write_word(ADDR_R_DATA0 + 117, 32'hef5a342d); write_word(ADDR_R_DATA0 + 118, 32'hf28707ac); write_word(ADDR_R_DATA0 + 119, 32'h4b8e3e8c); write_word(ADDR_R_DATA0 + 120, 32'h854e8d69); write_word(ADDR_R_DATA0 + 121, 32'h1cb92e87); write_word(ADDR_R_DATA0 + 122, 32'hc0d57558); write_word(ADDR_R_DATA0 + 123, 32'he44cd754); write_word(ADDR_R_DATA0 + 124, 32'h424865c2); write_word(ADDR_R_DATA0 + 125, 32'h29c9e1ab); write_word(ADDR_R_DATA0 + 126, 32'hb28e003b); write_word(ADDR_R_DATA0 + 127, 32'h6819400b); // Write magic words to A. write_word(ADDR_A0, 32'haea19443); write_word(ADDR_A1, 32'hd7f8ad7d); $display("* Contents of memory and dut before unwrap processing:"); dump_mem(65); // Start unwrapping and wait for unwrap to complete. $display("* Trying to start processing."); write_word(ADDR_CTRL, 32'h00000002); #(2 * CLK_PERIOD); wait_ready(); $display("* Processing should be done."); $display("Contents of memory and dut after unwrap processing:"); dump_mem(65); dump_dut_state(); // Read and display the A registers. read_word(ADDR_A0); $display("A0 after unwrap: 0x%08x", read_data); read_word(ADDR_A1); $display("A1 after unwrap: 0x%08x", read_data); // Read and display the R blocks that has been processed. for (i = 0 ; i < 128 ; i = i + 1) begin read_word(ADDR_R_DATA0 + i); $display("mem[0x%07x] = 0x%08x", i, read_data); end $display("** TC kwp_ad_128_2 END.\n"); end endtask // test_kwp_ad_128_2 //---------------------------------------------------------------- // main //---------------------------------------------------------------- initial begin : main $display(" -= Testbench for Keywrap started =-"); $display(" =================================="); $display(""); init_sim(); dump_dut_state(); reset_dut(); dump_dut_state(); test_core_access(); test_kwp_ae_128_1(); test_kwp_ad_128_1(); test_kwp_ae_128_2(); test_kwp_ad_128_2(); display_test_results(); $display(""); $display(" -= Testbench for Keywrap completed =-"); $display(" ===================================="); $finish; end // main endmodule // tb_keywrap //====================================================================== // EOF tb_keywrap.v //======================================================================