From 478179fd21ec7147208f071260b887e866b3a5c9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 14 Jun 2018 13:42:19 +0200
Subject: Adding toggle design including testbench and Makefile to run
 simulation.

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 README.md | 14 ++++++++++++++
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 create mode 100644 README.md

(limited to 'README.md')

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+toggle
+======
+## Introduction ##
+
+This repo contains a simple deign that toggles an ouput pin. The toggle
+is in sync with the given sys_clk, but the toggle circuit divides down
+the clock. The divisor is build time defined.
+
+The design is used in the Cryptech FPGA design to observe internal
+clock frequencies.
+
+
+## Status ##
+Has been simulated with Icarus Verilog.
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