path: root/README.md

   
toggle
Introduction
This repo contains a simple deign that toggles an ouput pin. The toggle
is in sync with the given sys_clk, but the toggle circuit divides down
the clock. The divisor is build time defined.
The design is used in the Cryptech FPGA design to observe internal
clock frequencies.
Status
Has been simulated with Icarus Verilog.