path: root/src/tb/tb_keywrap.v

//======================================================================
//
// tb_keywrap.v
// ------------
// Testbench for the keywrap top level wrapper (and core).
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module tb_keywrap();

  parameter DEBUG     = 1;
  parameter DUMP_TOP  = 1;
  parameter DUMP_CORE = 1;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;

  // API for the core.
  localparam ADDR_NAME0       = 8'h00;
  localparam ADDR_NAME1       = 8'h01;
  localparam ADDR_VERSION     = 8'h02;

  localparam ADDR_CTRL        = 8'h08;
  localparam CTRL_INIT_BIT    = 0;
  localparam CTRL_NEXT_BIT    = 1;

  localparam ADDR_STATUS      = 8'h09;
  localparam STATUS_READY_BIT = 0;
  localparam STATUS_VALID_BIT = 1;

  localparam ADDR_CONFIG      = 8'h0a;
  localparam CTRL_ENCDEC_BIT  = 0;
  localparam CTRL_KEYLEN_BIT  = 1;

  localparam ADDR_RLEN        = 8'h0c;
  localparam ADDR_A0          = 8'h0e;
  localparam ADDR_A1          = 8'h0f;

  localparam ADDR_KEY0        = 8'h10;
  localparam ADDR_KEY1        = 8'h11;
  localparam ADDR_KEY2        = 8'h12;
  localparam ADDR_KEY3        = 8'h13;
  localparam ADDR_KEY4        = 8'h14;
  localparam ADDR_KEY5        = 8'h15;
  localparam ADDR_KEY6        = 8'h16;
  localparam ADDR_KEY7        = 8'h17;

  localparam ADDR_WRITE_DATA  = 8'h20;

  localparam ADDR_READ_DATA   = 8'h30;


  //----------------------------------------------------------------
  // Register and Wire declarations.
  //----------------------------------------------------------------
  reg [31 : 0]  cycle_ctr;
  reg [31 : 0]  error_ctr;
  reg [31 : 0]  tc_ctr;

  reg [31 : 0]  read_data;
  reg [127 : 0] result_data;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_cs;
  reg           tb_we;
  reg [7  : 0]  tb_address;
  reg [31 : 0]  tb_write_data;
  wire [31 : 0] tb_read_data;
  wire          tb_error;


  //----------------------------------------------------------------
  // Device Under Test.
  //----------------------------------------------------------------
  keywrap dut(
              .clk(tb_clk),
              .reset_n(tb_reset_n),
              .cs(tb_cs),
              .we(tb_we),
              .address(tb_address),
              .write_data(tb_write_data),
              .read_data(tb_read_data),
              .error(tb_error)
             );


  //----------------------------------------------------------------
  // clk_gen
  //
  // Always running clock generator process.
  //----------------------------------------------------------------
  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end // clk_gen


  //----------------------------------------------------------------
  // sys_monitor()
  //
  // An always running process that creates a cycle counter and
  // conditionally displays information about the DUT.
  //----------------------------------------------------------------
  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      if (DEBUG)
        dump_dut_state();
      #(CLK_PERIOD);
    end



  //----------------------------------------------------------------
  // read_word()
  //
  // Read a data word from the given address in the DUT.
  // the word read will be available in the global variable
  // read_data.
  //----------------------------------------------------------------
  task read_word(input [11 : 0]  address);
    begin
      tb_address = address;
      tb_cs = 1;
      tb_we = 0;

      #(CLK_PERIOD);
      read_data = tb_read_data;
      tb_cs = 0;

      if (DEBUG)
        begin
          $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
          $display("");
        end
    end
  endtask // read_word


  //----------------------------------------------------------------
  // write_word()
  //
  // Write the given word to the DUT using the DUT interface.
  //----------------------------------------------------------------
  task write_word(input [11 : 0] address,
                  input [31 : 0] word);
    begin
      if (DEBUG)
        begin
          $display("*** Writing 0x%08x to 0x%02x.", word, address);
          $display("");
        end

      tb_address = address;
      tb_write_data = word;
      tb_cs = 1;
      tb_we = 1;

      #(1 * CLK_PERIOD);
      tb_cs = 0;
      tb_we = 0;
    end
  endtask // write_word


  //----------------------------------------------------------------
  // wait_ready
  //
  // Wait for the DUT to signal that the result is ready
  //----------------------------------------------------------------
  task wait_ready;
    begin : wait_ready
      reg rdy;
      rdy = 1'b0;

      while (rdy != 1'b1)
        begin
          read_word(ADDR_STATUS);
          rdy = tb_read_data[STATUS_READY_BIT];
        end
    end
  endtask // wait_ready


  //----------------------------------------------------------------
  // dump_mem()
  //
  // Dump the n first memory positions in the dut internal memory.
  //----------------------------------------------------------------
  task dump_mem(integer n);
    begin : dump_mem
      integer i;
      for (i  = 0 ; i < n ; i = i + 2)
        $display("mem0[0x%06x] = 0x%08x  mem1[0x%06x] = 0x%08x",
                 i, dut.core.mem.mem0[i], i, dut.core.mem.mem1[i]);
      $display("");
    end
  endtask // dump_mem


  //----------------------------------------------------------------
  // dump_dut_state()
  //
  // Dump the state of the dump when needed.
  //----------------------------------------------------------------
  task dump_dut_state;
    begin
      $display("cycle: 0x%016x", cycle_ctr);
      $display("State of DUT");
      $display("------------");

      if (DUMP_TOP)
        begin
          $display("top level state:");
          $display("init_reg  = 0x%x next_reg   = 0x%x", dut.init_reg, dut.next_reg);
          $display("endec_reg = 0x%x keylen_reg = 0x%x", dut.encdec_reg, dut.keylen_reg);
          $display("rlen_reg  = 0x%06x", dut.rlen_reg);
          $display("a0_reg    = 0x%08x  a1_reg  = 0x%08x", dut.a0_reg, dut.a1_reg);
          $display("");
        end

      if (DUMP_CORE)
        begin
          $display("core level state:");
          $display("init   = 0x%0x  next = 0x%0x  ready = 0x%0x  valid = 0x%0x",
                   dut.core.init, dut.core.next, dut.core.ready, dut.core.valid);
          $display("rlen   = 0x%0x", dut.core.rlen);
          $display("key    = 0x%0x", dut.core.key);
          $display("a_init = 0x%0x  a_result = 0x%0x", dut.core.a_init, dut.core.a_result);
          $display("");

          $display("update_state = 0x%0x", dut.core.update_state);
          $display("a_reg  = 0x%0x  a_new = 0x%0x  a_we = 0x%0x",
                   dut.core.a_reg, dut.core.a_new, dut.core.a_we);
          $display("aes_block = 0x%0x  aes_result = 0x%0x",
                   dut.core.aes_block, dut.core.aes_result);
          $display("core_we = 0x%0x  core_addr = 0x%0x",
                   dut.core.core_we, dut.core.block_ctr_reg);
          $display("core_rd_data = 0x%0x  core_wr_data = 0x%0x ",
                   dut.core.core_rd_data, dut.core.core_wr_data);
          $display("");

          $display("block_ctr_reg = 0x%0x  iteration_ctr_reg = 0x%0x",
                   dut.core.block_ctr_reg, dut.core.iteration_ctr_reg);
          $display("keywrap_core_ctrl_reg = 0x%0x", dut.core.keywrap_core_ctrl_reg);
          $display("keywrap_core_ctrl_new = 0x%0x", dut.core.keywrap_core_ctrl_new);
          $display("keywrap_core_ctrl_we  = 0x%0x", dut.core.keywrap_core_ctrl_we);
        end

      $display("");
    end
  endtask // dump_dut_state


  //----------------------------------------------------------------
  // display_test_results()
  //
  // Display the accumulated test results.
  //----------------------------------------------------------------
  task display_test_results;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask // display_test_results


  //----------------------------------------------------------------
  // init_sim()
  //
  // Initialize all counters and testbed functionality as well
  // as setting the DUT inputs to defined values.
  //----------------------------------------------------------------
  task init_sim;
    begin
      cycle_ctr     = 0;
      error_ctr     = 0;
      tc_ctr        = 0;

      tb_clk        = 0;
      tb_reset_n    = 1;

      tb_cs         = 0;
      tb_we         = 0;
      tb_address    = 8'h0;
      tb_write_data = 32'h0;
    end
  endtask // init_sim


  //----------------------------------------------------------------
  // reset_dut()
  //
  // Toggle reset to put the DUT into a well known state.
  //----------------------------------------------------------------
  task reset_dut;
    begin
      $display("** Toggling reset.");
      tb_reset_n = 0;

      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
      $display("");
    end
  endtask // reset_dut


  //----------------------------------------------------------------
  // Implements test based on NIST KWP_AE 128 bit key test 4.
  //----------------------------------------------------------------
  task test_kwp_ae_128_4;
    begin : kwp_ae_128_4
      integer i;

      tc_ctr = tc_ctr + 1;

      $display("** TC kwp_ae_128_4 START.");


      // Write key and keylength, we also want to encrypt/wrap.
      write_word(ADDR_KEY0,   32'hc03db3cc);
      write_word(ADDR_KEY1,   32'h1416dcd1);
      write_word(ADDR_KEY2,   32'hc069a195);
      write_word(ADDR_KEY3,   32'ha8d77e3d);
      write_word(ADDR_CONFIG, 32'h00000001);

      $display("* State after key has been set:");
      dump_dut_state();


      // Initialize the AES engine and reset counters.
      // Wait for init to complete.
      $display("* Trying to initialize.");
      write_word(ADDR_CTRL, 32'h00000001);
      #(2 * CLK_PERIOD);
      wait_ready();
      $display("* Init should be done.");


      // Write the R blocks to be processed.
      write_word(ADDR_WRITE_DATA, 32'h46f87f58);
      write_word(ADDR_WRITE_DATA, 32'hcdda4200);

      write_word(ADDR_WRITE_DATA, 32'hf53d99ce);
      write_word(ADDR_WRITE_DATA, 32'h2e49bdb7);

      write_word(ADDR_WRITE_DATA, 32'h6212511f);
      write_word(ADDR_WRITE_DATA, 32'he0cd4d0b);

      write_word(ADDR_WRITE_DATA, 32'h5f37a27d);
      write_word(ADDR_WRITE_DATA, 32'h45a28800);

      // Write magic words to the A state regs.
      // Also set the rlen.
      write_word(ADDR_A0, 32'ha65959a6);
      write_word(ADDR_A1, 32'h0000001f);
      write_word(ADDR_RLEN,  32'h00000004);


      $display("* Contents of memory and dut before wrap processing:");
      dump_mem(6);


      // Start wrapping and wait for wrap to complete.
      $display("* Trying to start processing.");
      write_word(ADDR_CTRL, 32'h00000002);
      #(2 * CLK_PERIOD);
      wait_ready();
      $display("* Processing should be done.");


      $display("Contents of memory and dut after wrap processing:");
      dump_mem(6);
      dump_dut_state();


      // Read and display the A registers.
      read_word(ADDR_A0);
      $display("A0 after wrap: 0x%08x", read_data);
      read_word(ADDR_A1);
      $display("A1 after wrap: 0x%08x", read_data);

      // Read and display the R blocks that has been processed.
      for (i = 0 ; i < 8 ; i = i + 1)
        begin
          read_word(ADDR_READ_DATA);
          $display("mem[0x%07x] = 0x%08x", i, read_data);
        end

      $display("** TC kwp_ae_128_4 END.\n");
    end
  endtask // test_kwp_ae_128_4


  //----------------------------------------------------------------
  // main
  //----------------------------------------------------------------
  initial
    begin : main
      $display("   -= Testbench for Keywrap started =-");
      $display("    ==================================");
      $display("");

      init_sim();

      dump_dut_state();
      reset_dut();
      dump_dut_state();

      test_kwp_ae_128_4();

      display_test_results();

      $display("");
      $display("   -= Testbench for Keywrap completed =-");
      $display("    ====================================");
      $finish;
    end // main

endmodule // tb_keywrap

//======================================================================
// EOF tb_keywrap.v
//======================================================================