aboutsummaryrefslogtreecommitdiff
path: root/src/rtl/keywrap_mem.v
blob: 2076a57d6f6eba3682ddc59ca9d22641db79e96d (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
//======================================================================
//
// keywrap_mem.v
// -------------
// Memory for AES KEY WRAP processing.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module keywrap_mem

  (
   input wire           clk,
   input wire           reset_n,

   input wire           api_we,
   input wire [8 : 0]   api_addr,
   input wire [31 : 0]  api_wr_data,
   output wire [31 : 0] api_rd_data,

   input wire           core_we,
   input wire [7 : 0]   core_addr,
   input wire [63 : 0]  core_wr_data,
   output wire [63 : 0] core_rd_data
  );


  reg [31 : 0] tmp_api_rd_data;
  reg [63 : 0] tmp_core_rd_data;

  reg [31 : 0] mem0 [0 : 255];
  reg [31 : 0] mem0_data;
  reg  [7 : 0] mem0_addr;
  reg          mem0_we;

  reg [31 : 0] mem1 [0 : 255];
  reg [31 : 0] mem1_data;
  reg  [7 : 0] mem1_addr;
  reg          mem1_we;


  //----------------------------------------------------------------
  // Assignments for ports.
  //----------------------------------------------------------------
  assign api_rd_data = tmp_api_rd_data;
  assign core_rd_data = tmp_core_rd_data;


  //----------------------------------------------------------------
  // mem_access
  //
  // Clocked read and write to the memory banks.
  //----------------------------------------------------------------
  always @(posedge clk)
    begin : mem_access
      tmp_core_rd_data <= {mem1[core_addr], mem0[core_addr]};

      if (api_addr[0])
        tmp_api_rd_data <= mem1[api_addr[8 : 1]];
      else
        tmp_api_rd_data <= mem0[api_addr[8 : 1]];


      if (mem0_we)
        mem0[mem0_addr] <= mem0_data;

      if (mem1_we)
        mem1[mem1_addr] <= mem1_data;
    end


  //----------------------------------------------------------------
  // write_mux
  // Mux that handles priority of writes and selection
  // of memory bank to write api data to.
  //----------------------------------------------------------------
  always @*
    begin : write_mux
      mem0_data = 32'h0;
      mem0_addr = 8'h0;
      mem0_we   = 1'h0;
      mem1_data = 32'h0;
      mem1_addr = 8'h0;
      mem1_we   = 1'h0;

      if (core_we)
        begin
          mem0_data = core_wr_data[31 : 0];
          mem0_addr = core_addr;
          mem0_we   = 1'h1;
          mem1_data = core_wr_data[63 : 32];
          mem1_addr = core_addr;
          mem1_we   = 1'h1;
        end

      else if (api_we)
        begin
          if (api_addr[0])
            begin
              mem1_data = api_wr_data;
              mem1_addr = api_addr[7 : 0];
              mem1_we   = 1'h1;
            end
          else
            begin
              mem0_data = api_wr_data;
              mem0_addr = api_addr[7 : 0];
              mem0_we   = 1'h1;
            end
        end
    end
endmodule // keywrap_mem

//======================================================================
// EOF keywrap_mem.v
//======================================================================