From 3a600f879582905f83573eb2fc26ccb88886df79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 27 Jun 2018 15:27:48 +0200 Subject: (1) Adding initial version of top level testbench. (2) Updating Makefile to be able to bild and run top level simulation as well as linting all rtl code. --- toolruns/Makefile | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'toolruns') diff --git a/toolruns/Makefile b/toolruns/Makefile index 996e6e7..9b890ad 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -46,13 +46,20 @@ TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v +TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) +TB_TOP_SRC = ../src/tb/tb_keywrap.v + CC = iverilog CC_FLAGS = -Wall LINT = verilator LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME -all: core.sim mem.sim +all: top.sim core.sim mem.sim + + +top.sim: $(TB_TOP_SRC) $(TOP_SRC) + $(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) core.sim: $(TB_CORE_SRC) $(CORE_SRC) @@ -63,6 +70,10 @@ mem.sim: $(TB_MEM_SRC) $(MEM_SRC) $(CC) $(CC_FLAGS) -o mem.sim $(TB_MEM_SRC) $(MEM_SRC) +sim-top: top.sim + ./top.sim + + sim-core: core.sim ./core.sim @@ -71,11 +82,12 @@ sim-mem: mem.sim ./mem.sim -lint: $(CORE_SRC) - $(LINT) $(LINT_FLAGS) $(CORE_SRC) +lint: $(TOP_SRC) + $(LINT) $(LINT_FLAGS) $(TOP_SRC) clean: + rm -f top.sim rm -f core.sim rm -f mem.sim @@ -85,7 +97,9 @@ help: @echo "------------------" @echo "all: Build all simulation targets." @echo "lint: Lint all rtl source files." + @echo "top.sim: Build top simulation target." @echo "core.sim: Build core simulation target." + @echo "sim-top: Run top simulation." @echo "sim-core: Run core simulation." @echo "mem.sim: Build mem simulation target." @echo "sim-mem: Run mem simulation." -- cgit v1.2.3