From 36fcc28a75ed9fa6d0dc76d9ff3351ee1dd63b89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 22 Jun 2018 08:32:33 +0200 Subject: (1) Added initial version of keywrap_core which will implement the actual wrapping using aes_core and the keywrap_mem. (2) Minor cleanup to the keywrap_mem code. --- src/rtl/keywrap_core.v | 213 +++++++++++++++++++++++++++++++++++++++++++++++++ src/rtl/keywrap_mem.v | 50 ++++++------ 2 files changed, 239 insertions(+), 24 deletions(-) create mode 100644 src/rtl/keywrap_core.v (limited to 'src') diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v new file mode 100644 index 0000000..eda8459 --- /dev/null +++ b/src/rtl/keywrap_core.v @@ -0,0 +1,213 @@ +//====================================================================== +// +// keywrap_core.v +// -------------- +// Core that tries to implement AES KEY WRAP as specified in +// RFC 3394. Experimental core at the moment. +// The maximum wrap object size is 64 kByte. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2018, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module keywrap_core ( + input wire clk, + input wire reset_n, + + input wire encdec, + input wire init, + output wire ready, + input wire [255 : 0] key, + input wire keylen, + input wire [13 : 0] message_len, + + input wire api_we, + input wire [13 : 0] api_addr, + input wire [31 : 0] api_wr_data, + output wire [31 : 0] api_rd_data + ); + + + //---------------------------------------------------------------- + // Paramenters and local defines. + //---------------------------------------------------------------- + localparam OUTER_LOOP_MAX = 6; + + + localparam CTRL_IDLE = 3'h0; + localparam CTRL_INIT = 3'h1; + localparam CTRL_NEXT = 3'h2; + + + //---------------------------------------------------------------- + // Registers and memories including control signals. + //---------------------------------------------------------------- + reg [63 : 0] a_reg; + reg [63 : 0] a_new; + reg a_we; + reg a_init; + + reg ready_reg; + reg ready_new; + reg ready_we; + + reg [12 : 0] block_loop_ctr_reg; + reg [12 : 0] block_loop_ctr_new; + reg block_loop_ctr_we; + reg block_loop_ctr_inc; + reg block_loop_ctr_rst; + + reg [2 : 0] outer_loop_ctr_reg; + reg [2 : 0] outer_loop_ctr_new; + reg outer_loop_ctr_we; + reg outer_loop_ctr_inc; + reg outer_loop_ctr_dec; + reg outer_loop_ctr_set; + reg outer_loop_ctr_rst; + + reg [12 : 0] core_addr_ctr_reg; + reg [12 : 0] core_addr_ctr_new; + reg core_addr_ctr_we; + + reg [2 : 0] keywrap_core_ctrl_reg; + reg [2 : 0] keywrap_core_ctrl_new; + reg keywrap_core_ctrl_we; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg aes_encdec; + reg aes_init; + reg aes_next; + wire aes_ready; + wire [255 : 0] aes_key; + wire aes_keylen; + reg [127 : 0] aes_block; + wire [127 : 0] aes_result; + wire aes_valid; + + reg core_we; + reg [12 : 0] core_addr; + reg [63 : 0] core_wr_data; + wire [63 : 0] core_rd_data; + + + //---------------------------------------------------------------- + // Instantiations. + //---------------------------------------------------------------- + keywrap_mem mem( + .clk(), + .reset_n(), + .api_we(api_we), + .api_addr(api_addr), + .api_wr_data(api_wr_data), + .api_rd_data(api_rd_data), + .core_we(), + .core_addr(), + .core_wr_data(), + .core_rd_data() + ); + + + aes_core aes( + .clk(clk), + .reset_n(reset_n), + .encdec(aes_encdec), + .init(aes_init), + .next(aes_next), + .ready(aes_ready), + .key(aes_key), + .keylen(aes_keylen), + .block(aes_block), + .result(aes_result), + .result_valid(aes_valid) + ); + + //---------------------------------------------------------------- + // Assignments for ports. + //---------------------------------------------------------------- + + + //---------------------------------------------------------------- + // reg_update + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin: reg_update + if (!reset_n) + begin + keywrap_core_ctrl_reg <= CTRL_IDLE; + + end + + else + begin + + if (keywrap_core_ctrl_we) + keywrap_core_ctrl_reg <= keywrap_core_ctrl_new; + end + end // reg_update + + + //---------------------------------------------------------------- + // keywrap_core_ctrl + //---------------------------------------------------------------- + always @* + begin : keywrap_core_ctrl + aes_encdec = 0; + aes_init = 0; + aes_next = 0; + block_loop_ctr_inc = 0; + block_loop_ctr_rst = 0; + outer_loop_ctr_inc = 0; + outer_loop_ctr_dec = 0; + outer_loop_ctr_set = 0; + outer_loop_ctr_rst = 0; + + + case (keywrap_core_ctrl_reg) + CTRL_IDLE: + begin + end + + default: + begin + + end + endcase // case (keywrap_core_ctrl_reg) + end // keywrap_core_ctrl + +endmodule // keywrap_core + +//====================================================================== +// EOF keywrap_core.v +//====================================================================== diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v index 8ddb465..e54798a 100644 --- a/src/rtl/keywrap_mem.v +++ b/src/rtl/keywrap_mem.v @@ -37,45 +37,47 @@ // //====================================================================== -module keywrap_mem +module keywrap_mem ( + input wire clk, + input wire reset_n, - ( - input wire clk, - input wire reset_n, + input wire api_we, + input wire [13 : 0] api_addr, + input wire [31 : 0] api_wr_data, + output wire [31 : 0] api_rd_data, - input wire api_we, - input wire [13 : 0] api_addr, - input wire [31 : 0] api_wr_data, - output wire [31 : 0] api_rd_data, - - input wire core_we, - input wire [12 : 0] core_addr, - input wire [63 : 0] core_wr_data, - output wire [63 : 0] core_rd_data - ); + input wire core_we, + input wire [12 : 0] core_addr, + input wire [63 : 0] core_wr_data, + output wire [63 : 0] core_rd_data + ); //---------------------------------------------------------------- - // Registers and memories including conntrol signals. + // Registers and memories including control signals. //---------------------------------------------------------------- - reg [31 : 0] tmp_api_rd_data0; - reg [31 : 0] tmp_api_rd_data1; - reg [31 : 0] muxed_tmp_api_rd_data; - - reg [31 : 0] tmp_core_rd_data0; - reg [31 : 0] tmp_core_rd_data1; - reg [31 : 0] mem0 [0 : 8191]; reg [31 : 0] mem0_data; - reg [12 : 0] mem0_addr; + reg [12 : 0] mem0_addr; reg mem0_we; reg [31 : 0] mem1 [0 : 8191]; reg [31 : 0] mem1_data; - reg [12 : 0] mem1_addr; + reg [12 : 0] mem1_addr; reg mem1_we; + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg [31 : 0] tmp_api_rd_data0; + reg [31 : 0] tmp_api_rd_data1; + reg [31 : 0] muxed_tmp_api_rd_data; + + reg [31 : 0] tmp_core_rd_data0; + reg [31 : 0] tmp_core_rd_data1; + + //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- -- cgit v1.2.3