From 16f31cdf1c1b51e87486207fda89511cdb65cf5f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 21 Jun 2018 23:03:08 +0200
Subject: Reworked code a bit to match what ISE expects to map to block RAM
 instances.

---
 src/rtl/keywrap_mem.v | 49 ++++++++++++++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index 2076a57..a9e80d8 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -55,8 +55,15 @@ module keywrap_mem
   );
 
 
-  reg [31 : 0] tmp_api_rd_data;
-  reg [63 : 0] tmp_core_rd_data;
+  //----------------------------------------------------------------
+  // Registers and memories including conntrol signals.
+  //----------------------------------------------------------------
+  reg [31 : 0] tmp_api_rd_data0;
+  reg [31 : 0] tmp_api_rd_data1;
+  reg [31 : 0] muxed_tmp_api_rd_data;
+
+  reg [31 : 0] tmp_core_rd_data0;
+  reg [31 : 0] tmp_core_rd_data1;
 
   reg [31 : 0] mem0 [0 : 255];
   reg [31 : 0] mem0_data;
@@ -72,33 +79,45 @@ module keywrap_mem
   //----------------------------------------------------------------
   // Assignments for ports.
   //----------------------------------------------------------------
-  assign api_rd_data = tmp_api_rd_data;
-  assign core_rd_data = tmp_core_rd_data;
+  assign api_rd_data = muxed_tmp_api_rd_data;
+  assign core_rd_data = {tmp_core_rd_data1, tmp_core_rd_data0};
 
 
   //----------------------------------------------------------------
-  // mem_access
-  //
-  // Clocked read and write to the memory banks.
+  // mem0_access
   //----------------------------------------------------------------
   always @(posedge clk)
-    begin : mem_access
-      tmp_core_rd_data <= {mem1[core_addr], mem0[core_addr]};
-
-      if (api_addr[0])
-        tmp_api_rd_data <= mem1[api_addr[8 : 1]];
-      else
-        tmp_api_rd_data <= mem0[api_addr[8 : 1]];
-
+    begin : mem0_access
+      tmp_core_rd_data0 <= mem0[core_addr];
+      tmp_api_rd_data0  <= mem0[api_addr[8 : 1]];
 
       if (mem0_we)
         mem0[mem0_addr] <= mem0_data;
+    end
+
+
+  //----------------------------------------------------------------
+  // mem1_access
+  //----------------------------------------------------------------
+  always @(posedge clk)
+    begin : mem1_access
+      tmp_core_rd_data1 <= mem1[core_addr];
+      tmp_api_rd_data1  <= mem1[api_addr[8 : 1]];
 
       if (mem1_we)
         mem1[mem1_addr] <= mem1_data;
     end
 
 
+  always @*
+    begin
+      if (api_addr[0])
+        muxed_tmp_api_rd_data = tmp_api_rd_data1;
+      else
+        muxed_tmp_api_rd_data = tmp_api_rd_data0;
+    end
+
+
   //----------------------------------------------------------------
   // write_mux
   // Mux that handles priority of writes and selection
-- 
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