From 8836e5db9c8c8cdcf7e0a144f8d9a42f73d212f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 4 Sep 2018 11:58:04 +0200 Subject: Updated testbench to work with the parameterized memory. --- src/tb/tb_keywrap_mem.v | 59 +++++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 24 deletions(-) diff --git a/src/tb/tb_keywrap_mem.v b/src/tb/tb_keywrap_mem.v index 000bd16..0cc8ca0 100644 --- a/src/tb/tb_keywrap_mem.v +++ b/src/tb/tb_keywrap_mem.v @@ -42,11 +42,15 @@ module tb_keywrap_mem(); //---------------------------------------------------------------- // Parameters. //---------------------------------------------------------------- + parameter DEBUG = 1; + parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; - parameter API_ADDR_MAX = 2**14 - 1; - parameter CORE_ADDR_MAX = 2**13 - 1; + parameter API_ADDR_BITS = 4; + parameter CORE_ADDR_BITS = API_ADDR_BITS - 1; + parameter API_ADDR_MAX = (2 ** API_ADDR_BITS) - 1; + parameter CORE_ADDR_MAX = (2 ** CORE_ADDR_BITS) - 1; //---------------------------------------------------------------- @@ -56,21 +60,22 @@ module tb_keywrap_mem(); reg [31 : 0] error_ctr; reg [31 : 0] tc_ctr; - reg tb_clk; - reg tb_api_we; - reg [13 : 0] tb_api_addr; - reg [31 : 0] tb_api_wr_data; - wire [31 : 0] tb_api_rd_data; - reg tb_core_we; - reg [12 : 0] tb_core_addr; - reg [63 : 0] tb_core_wr_data; - wire [63 : 0] tb_core_rd_data; + reg tb_clk; + reg tb_api_we; + reg [(API_ADDR_BITS - 1) : 0] tb_api_addr; + reg [31 : 0] tb_api_wr_data; + wire [31 : 0] tb_api_rd_data; + reg tb_core_we; + reg [(CORE_ADDR_BITS - 1) : 0] tb_core_addr; + reg [63 : 0] tb_core_wr_data; + wire [63 : 0] tb_core_rd_data; //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- - keywrap_mem dut( + keywrap_mem #(.API_ADDR_BITS(API_ADDR_BITS)) + dut( .clk(tb_clk), .api_we(tb_api_we), .api_addr(tb_api_addr), @@ -120,11 +125,11 @@ module tb_keywrap_mem(); cycle_ctr = 0; tb_clk = 0; - tb_api_we = 0; - tb_api_addr = 14'h0; + tb_api_we = 1'h0; + tb_api_addr = {API_ADDR_BITS{1'h0}}; tb_api_wr_data = 32'h0; - tb_core_we = 0; - tb_core_addr = 13'h0; + tb_core_we = 1'h0; + tb_core_addr = {CORE_ADDR_BITS{1'h0}}; tb_core_wr_data = 64'h0; #(CLK_PERIOD); @@ -140,11 +145,12 @@ module tb_keywrap_mem(); reg [13 : 0] addr_ctr; - for (addr_ctr = 0 ; addr_ctr < API_ADDR_MAX ; addr_ctr = addr_ctr + 1) + $display("Content of the memory:"); + for (addr_ctr = 0 ; addr_ctr <= API_ADDR_MAX ; addr_ctr = addr_ctr + 1) begin tb_api_addr = addr_ctr; #(CLK_PERIOD); - $display("api_mem [0x%05x] = 0x%08x", addr_ctr, tb_api_rd_data); + $display("api_mem [0x%08x] = 0x%08x", addr_ctr, tb_api_rd_data); end end endtask // dump_api_mem @@ -158,11 +164,12 @@ module tb_keywrap_mem(); reg [12 : 0] addr_ctr; - for (addr_ctr = 0 ; addr_ctr < CORE_ADDR_MAX ; addr_ctr = addr_ctr + 1) + $display("Content of the memory:"); + for (addr_ctr = 0 ; addr_ctr <= CORE_ADDR_MAX ; addr_ctr = addr_ctr + 1) begin tb_core_addr = addr_ctr; #(CLK_PERIOD); - $display("core_mem [0x%04x] = 0x%016x", addr_ctr, tb_core_rd_data); + $display("core_mem [0x%08x] = 0x%016x", addr_ctr, tb_core_rd_data); end end endtask // dump_core_mem @@ -177,7 +184,7 @@ module tb_keywrap_mem(); $display("** TC CORE RMW START"); - for (addr_ctr = 0 ; addr_ctr < CORE_ADDR_MAX ; addr_ctr = addr_ctr + 1) + for (addr_ctr = 0 ; addr_ctr <= CORE_ADDR_MAX ; addr_ctr = addr_ctr + 1) begin tb_core_addr = addr_ctr; #(CLK_PERIOD); @@ -199,7 +206,7 @@ module tb_keywrap_mem(); //---------------------------------------------------------------- task test_api_write; begin : test_api_write - reg [13 : 0] addr_ctr; + reg [(API_ADDR_BITS - 1) : 0] addr_ctr; $display("** TC API WRITE START"); @@ -207,7 +214,11 @@ module tb_keywrap_mem(); begin tb_api_we = 1; tb_api_addr = addr_ctr; - tb_api_wr_data = {2'h0, addr_ctr, 2'h0, addr_ctr}; + tb_api_wr_data = {{(32 - API_ADDR_BITS){1'h0}}, addr_ctr, + {(32 - API_ADDR_BITS){1'h1}}, addr_ctr}; + if (DEBUG) + $display("Writing 0x%08x to address 0x%08x", tb_api_wr_data, tb_api_addr); + #(CLK_PERIOD); tb_api_we = 0; end @@ -224,7 +235,7 @@ module tb_keywrap_mem(); // test_api_read; //---------------------------------------------------------------- task test_api_read; - begin : test_api_reaqd + begin : test_api_read $display("** TC API READ START"); -- cgit v1.2.3