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-rw-r--r--src/tb/tb_keywrap_core.v47
1 files changed, 28 insertions, 19 deletions
diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 8d055fe..17c8f30 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -42,38 +42,47 @@ module tb_keywrap_core();
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
+ parameter DEBUG = 1;
+
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+ parameter API_ADDR_BITS = 8;
+ parameter RLEN_BITS = API_ADDR_BITS - 1;
+ parameter CORE_ADDR_BITS = API_ADDR_BITS - 1;
+ parameter API_ADDR_MAX = (2 ** API_ADDR_BITS) - 1;
+ parameter CORE_ADDR_MAX = (2 ** CORE_ADDR_BITS) - 1;
//----------------------------------------------------------------
// Variables, regs and wires.
//----------------------------------------------------------------
integer cycle_ctr;
-
- reg tb_clk;
- reg tb_reset_n;
-
- reg tb_init;
- reg tb_next;
- reg tb_encdec;
- wire tb_ready;
- wire tb_valid;
- reg [12 : 0] tb_rlen;
- reg [255 : 0] tb_key;
- reg tb_keylen;
- reg [63 : 0] tb_a_init;
- wire [63 : 0] tb_a_result;
- reg tb_api_we;
- reg [13 : 0] tb_api_addr;
- reg [31 : 0] tb_api_wr_data;
- wire [31 : 0] tb_api_rd_data;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_init;
+ reg tb_next;
+ reg tb_encdec;
+ wire tb_ready;
+ wire tb_valid;
+ reg [(RLEN_BITS - 1) : 0] tb_rlen;
+ reg [255 : 0] tb_key;
+ reg tb_keylen;
+ reg [63 : 0] tb_a_init;
+ wire [63 : 0] tb_a_result;
+ reg tb_api_we;
+ reg [(API_ADDR_BITS - 1) : 0] tb_api_addr;
+ reg [31 : 0] tb_api_wr_data;
+ wire [31 : 0] tb_api_rd_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
- keywrap_core dut(
+ keywrap_core #(.MEM_BITS(API_ADDR_BITS))
+ dut(
.clk(tb_clk),
.reset_n(tb_reset_n),