diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/keywrap_core.v | 113 | ||||
| -rw-r--r-- | src/tb/tb_keywrap_core.v | 100 |
2 files changed, 184 insertions, 29 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index eda8459..61f7859 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -3,7 +3,8 @@ // keywrap_core.v // -------------- // Core that tries to implement AES KEY WRAP as specified in -// RFC 3394. Experimental core at the moment. +// RFC 3394 and extended with padding in RFC 5649. +// Experimental core at the moment. Does Not Work. // The maximum wrap object size is 64 kByte. // // @@ -67,6 +68,8 @@ module keywrap_core ( localparam CTRL_INIT = 3'h1; localparam CTRL_NEXT = 3'h2; + localparam RFC5649_A_IV = 32'ha65959a6; + //---------------------------------------------------------------- // Registers and memories including control signals. @@ -80,23 +83,19 @@ module keywrap_core ( reg ready_new; reg ready_we; - reg [12 : 0] block_loop_ctr_reg; - reg [12 : 0] block_loop_ctr_new; - reg block_loop_ctr_we; - reg block_loop_ctr_inc; - reg block_loop_ctr_rst; - - reg [2 : 0] outer_loop_ctr_reg; - reg [2 : 0] outer_loop_ctr_new; - reg outer_loop_ctr_we; - reg outer_loop_ctr_inc; - reg outer_loop_ctr_dec; - reg outer_loop_ctr_set; - reg outer_loop_ctr_rst; + reg [12 : 0] block_ctr_reg; + reg [12 : 0] block_ctr_new; + reg block_ctr_we; + reg block_ctr_inc; + reg block_ctr_rst; - reg [12 : 0] core_addr_ctr_reg; - reg [12 : 0] core_addr_ctr_new; - reg core_addr_ctr_we; + reg [2 : 0] iteration_ctr_reg; + reg [2 : 0] iteration_ctr_new; + reg iteration_ctr_we; + reg iteration_ctr_inc; + reg iteration_ctr_dec; + reg iteration_ctr_set; + reg iteration_ctr_rst; reg [2 : 0] keywrap_core_ctrl_reg; reg [2 : 0] keywrap_core_ctrl_new; @@ -126,8 +125,8 @@ module keywrap_core ( // Instantiations. //---------------------------------------------------------------- keywrap_mem mem( - .clk(), - .reset_n(), + .clk(clk), + .reset_n(reset_n), .api_we(api_we), .api_addr(api_addr), .api_wr_data(api_wr_data), @@ -179,20 +178,76 @@ module keywrap_core ( //---------------------------------------------------------------- + // block_ctr + //---------------------------------------------------------------- + always @* + begin : block_ctr + block_ctr_new = 13'h0; + block_ctr_we = 1'h0; + + if (block_ctr_rst) + begin + block_ctr_new = 13'h0; + block_ctr_we = 1'h1; + end + + if (block_ctr_inc) + begin + block_ctr_new = block_ctr_reg + 1'h1; + block_ctr_we = 1'h1; + end + end + + + //---------------------------------------------------------------- + // iteration_ctr + //---------------------------------------------------------------- + always @* + begin : iteration_ctr + iteration_ctr_new = 3'h0; + iteration_ctr_we = 1'h0; + + if (iteration_ctr_rst) + begin + iteration_ctr_new = 3'h0; + iteration_ctr_we = 1'h1; + end + + if (iteration_ctr_set) + begin + iteration_ctr_new = 3'h5; + iteration_ctr_we = 1'h1; + end + + if (iteration_ctr_dec) + begin + iteration_ctr_new = iteration_ctr_reg + 1'h1; + iteration_ctr_we = 1'h1; + end + + if (iteration_ctr_inc) + begin + iteration_ctr_new = iteration_ctr_reg + 1'h1; + iteration_ctr_we = 1'h1; + end + + end + + + //---------------------------------------------------------------- // keywrap_core_ctrl //---------------------------------------------------------------- always @* begin : keywrap_core_ctrl - aes_encdec = 0; - aes_init = 0; - aes_next = 0; - block_loop_ctr_inc = 0; - block_loop_ctr_rst = 0; - outer_loop_ctr_inc = 0; - outer_loop_ctr_dec = 0; - outer_loop_ctr_set = 0; - outer_loop_ctr_rst = 0; - + aes_encdec = 0; + aes_init = 0; + aes_next = 0; + block_ctr_inc = 0; + block_ctr_rst = 0; + iteration_ctr_inc = 0; + iteration_ctr_dec = 0; + iteration_ctr_set = 0; + iteration_ctr_rst = 0; case (keywrap_core_ctrl_reg) CTRL_IDLE: diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v new file mode 100644 index 0000000..875240c --- /dev/null +++ b/src/tb/tb_keywrap_core.v @@ -0,0 +1,100 @@ +//====================================================================== +// +// tb_keywrap_mem.v +// ---------------- +// Testbench for the keywrap core. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2018, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module tb_keywrap_core(); + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + integer cycle_ctr; + reg tb_sys_clk; + reg tb_reset_n; + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD; + tb_sys_clk = !tb_sys_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + cycle_ctr = cycle_ctr + 1; + + #(CLK_PERIOD); + end + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + initial + begin + cycle_ctr = 0; + tb_sys_clk = 0; + tb_reset_n = 0; + + #(CLK_PERIOD * 10); + + tb_reset_n = 1; + + #(CLK_PERIOD * 10); + $finish; + end + +endmodule // tb_keywrap_core + +//====================================================================== +// EOF tb_keywrap_core.v +//====================================================================== |