diff options
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_keywrap.v | 57 | ||||
| -rw-r--r-- | src/tb/tb_keywrap_core.v | 8 |
2 files changed, 23 insertions, 42 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v index 4d1c25c..43e03ee 100644 --- a/src/tb/tb_keywrap.v +++ b/src/tb/tb_keywrap.v @@ -39,9 +39,9 @@ module tb_keywrap(); - parameter DEBUG = 0; - parameter DUMP_TOP = 0; - parameter DUMP_CORE = 0; + parameter DEBUG = 1; + parameter DUMP_TOP = 1; + parameter DUMP_CORE = 1; parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; @@ -67,8 +67,7 @@ module tb_keywrap(); localparam CTRL_ENCDEC_BIT = 0; localparam CTRL_KEYLEN_BIT = 1; - localparam ADDR_RLEN = 8'h0c; - localparam ADDR_R_BANK = 8'h0d; + localparam ADDR_LENGTH = 8'h0c; localparam ADDR_A0 = 8'h0e; localparam ADDR_A1 = 8'h0f; @@ -249,10 +248,10 @@ module tb_keywrap(); if (DUMP_TOP) begin $display("top level state:"); - $display("init_reg = 0x%x next_reg = 0x%x", dut.init_reg, dut.next_reg); - $display("endec_reg = 0x%x keylen_reg = 0x%x", dut.encdec_reg, dut.keylen_reg); - $display("rlen_reg = 0x%08x", dut.rlen_reg); - $display("a0_reg = 0x%08x a1_reg = 0x%08x", dut.a0_reg, dut.a1_reg); + $display("init_reg = 0x%x next_reg = 0x%x", dut.init_reg, dut.next_reg); + $display("endec_reg = 0x%x keylen_reg = 0x%x", dut.encdec_reg, dut.keylen_reg); + $display("length_reg = 0x%08x", dut.length_reg); + $display("a0_reg = 0x%08x a1_reg = 0x%08x", dut.a0_reg, dut.a1_reg); $display(""); end @@ -263,6 +262,7 @@ module tb_keywrap(); dut.core.init, dut.core.next, dut.core.ready, dut.core.valid); $display("api_we = 0x%0x api_addr = 0x%0x api_wr_data = 0x%0x api_rd_data = 0x%0x", dut.core.api_we, dut.core.api_addr, dut.core.api_wr_data, dut.core.api_rd_data); + $display("length = 0x%0x", dut.core.length); $display("rlen = 0x%0x", dut.core.rlen); $display("key = 0x%0x", dut.core.key); $display("a_init = 0x%0x a_result = 0x%0x", dut.core.a_init, dut.core.a_result); @@ -416,13 +416,6 @@ module tb_keywrap(); wait_ready(); $display("* Init should be done."); - - // Set the length or R in blocks. - // Write the R bank to be written to. - // Write the R blocks to be processed. - write_word(ADDR_RLEN, 32'h00000004); - - // Write the data to be wrapped. write_word(MEM_BASE + 0, 32'h46f87f58); write_word(MEM_BASE + 1, 32'hcdda4200); @@ -433,9 +426,8 @@ module tb_keywrap(); write_word(MEM_BASE + 6, 32'h5f37a27d); write_word(MEM_BASE + 7, 32'h45a28800); - // Write magic words to A. - write_word(ADDR_A0, 32'ha65959a6); - write_word(ADDR_A1, 32'h0000001f); + // Set the length of the data before padding. + write_word(ADDR_LENGTH, 32'h0000001f); $display("* Dumping state and mem after data write and A words."); @@ -523,10 +515,8 @@ module tb_keywrap(); $display("* Init should be done."); - // Set the length or R in blocks. - // Write the R bank to be written to. - // Write the R blocks to be processed. - write_word(ADDR_RLEN, 32'h00000004); + // Set the length before paddfing. + write_word(ADDR_LENGTH, 32'h0000001f); write_word(MEM_BASE + 0, 32'h59a69492); write_word(MEM_BASE + 1, 32'hbb7e2cd0); @@ -632,10 +622,8 @@ module tb_keywrap(); $display("* Init should be done."); - // Set the length or R in blocks. - // Write the R bank to be written to. - // Write the R blocks to be processed. - write_word(ADDR_RLEN, 32'h00000040); + // Set the length before padding. + write_word(ADDR_LENGTH, 32'h00000200); write_word(MEM_BASE + 0, 32'h8af887c5); write_word(MEM_BASE + 1, 32'h8dfbc38e); @@ -766,10 +754,6 @@ module tb_keywrap(); write_word(MEM_BASE + 126, 32'he2de7f12); write_word(MEM_BASE + 127, 32'h9b187053); - // Write magic words to A. - write_word(ADDR_A0, 32'ha65959a6); - write_word(ADDR_A1, 32'h00000200); - $display("* Contents of memory and dut before wrap processing:"); dump_mem(65); @@ -859,10 +843,8 @@ module tb_keywrap(); $display("* Init should be done."); - // Set the length or R in blocks. - // Write the R bank to be written to. - // Write the R blocks to be processed. - write_word(ADDR_RLEN, 32'h00000040); + // Set the length before padding. + write_word(ADDR_LENGTH, 32'h00000200); write_word(MEM_BASE + 0, 32'h4501c1ec); write_word(MEM_BASE + 1, 32'hadc6b5e3); @@ -1096,7 +1078,7 @@ module tb_keywrap(); // Set the length or R in blocks. // Write the R bank to be written to. // Write the R blocks to be processed. - write_word(ADDR_RLEN, 32'h000007f8); + write_word(ADDR_LENGTH, 32'h000007f8); // Write the data to be wrapped. @@ -1168,8 +1150,7 @@ module tb_keywrap(); test_kwp_ad_128_1(); test_kwp_ae_128_2(); test_kwp_ad_128_2(); - - test_big_wrap_256(); +// test_big_wrap_256(); display_test_results(); diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v index 17c8f30..2b88b8c 100644 --- a/src/tb/tb_keywrap_core.v +++ b/src/tb/tb_keywrap_core.v @@ -48,7 +48,7 @@ module tb_keywrap_core(); parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; parameter API_ADDR_BITS = 8; - parameter RLEN_BITS = API_ADDR_BITS - 1; + parameter LEN_BITS = API_ADDR_BITS + 2; parameter CORE_ADDR_BITS = API_ADDR_BITS - 1; parameter API_ADDR_MAX = (2 ** API_ADDR_BITS) - 1; parameter CORE_ADDR_MAX = (2 ** CORE_ADDR_BITS) - 1; @@ -67,7 +67,7 @@ module tb_keywrap_core(); reg tb_encdec; wire tb_ready; wire tb_valid; - reg [(RLEN_BITS - 1) : 0] tb_rlen; + reg [(LEN_BITS - 1) : 0] tb_length; reg [255 : 0] tb_key; reg tb_keylen; reg [63 : 0] tb_a_init; @@ -93,7 +93,7 @@ module tb_keywrap_core(); .ready(tb_ready), .valid(tb_valid), - .rlen(tb_rlen), + .length(tb_length), .key(tb_key), .keylen(tb_keylen), @@ -150,7 +150,7 @@ module tb_keywrap_core(); tb_init = 0; tb_next = 0; tb_encdec = 0; - tb_rlen = 13'h0; + tb_length = {LEN_BITS{1'h0}}; tb_key = 256'h0; tb_keylen = 0; tb_a_init = 64'h0; |