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-rw-r--r--src/rtl/keywrap.v24
-rw-r--r--src/rtl/keywrap_core.v2
-rw-r--r--src/tb/tb_keywrap_core.v8
3 files changed, 30 insertions, 4 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 786ab54..870a85c 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -77,6 +77,8 @@ module keywrap #(parameter ADDR_BITS = 13)
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
+ localparam CTRL_READ_BIT = 2;
+ localparam CTRL_WRITE_BIT = 3;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
@@ -122,6 +124,12 @@ module keywrap #(parameter ADDR_BITS = 13)
reg next_reg;
reg next_new;
+ reg read_reg;
+ reg read_new;
+
+ reg write_reg;
+ reg write_new;
+
reg encdec_reg;
reg keylen_reg;
reg config_we;
@@ -191,6 +199,8 @@ module keywrap #(parameter ADDR_BITS = 13)
.init(init_reg),
.next(next_reg),
+ .read(read_reg),
+ .write(write_reg),
.encdec(encdec_reg),
.ready(core_ready),
@@ -226,6 +236,8 @@ module keywrap #(parameter ADDR_BITS = 13)
init_reg <= 1'h0;
next_reg <= 1'h0;
+ read_reg <= 1'h0;
+ write_reg <= 1'h0;
encdec_reg <= 1'h0;
keylen_reg <= 1'h0;
rlen_reg <= {RLEN_BITS{1'h0}};
@@ -241,6 +253,8 @@ module keywrap #(parameter ADDR_BITS = 13)
valid_reg <= core_valid;
init_reg <= init_new;
next_reg <= next_new;
+ read_reg <= read_new;
+ write_reg <= write_new;
api_rd_delay_reg <= api_rd_delay_new;
if (config_we)
@@ -273,6 +287,8 @@ module keywrap #(parameter ADDR_BITS = 13)
begin : api
init_new = 1'h0;
next_new = 1'h0;
+ read_new = 1'h0;
+ write_new = 1'h0;
config_we = 1'h0;
rlen_we = 1'h0;
key_we = 1'h0;
@@ -296,8 +312,10 @@ module keywrap #(parameter ADDR_BITS = 13)
// Write access
if (address == {{PAD{1'h0}}, ADDR_CTRL})
begin
- init_new = write_data[CTRL_INIT_BIT];
- next_new = write_data[CTRL_NEXT_BIT];
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ read_new = write_data[CTRL_READ_BIT];
+ write_new = write_data[CTRL_WRITE_BIT];
end
if (address == {{PAD{1'h0}}, ADDR_CONFIG})
@@ -332,7 +350,7 @@ module keywrap #(parameter ADDR_BITS = 13)
api_rd_delay_new = CORE_VERSION;
if (address == {{PAD{1'h0}}, ADDR_CTRL})
- api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+ api_rd_delay_new = {26'h0, keylen_reg, encdec_reg, write_reg, read_reg, next_reg, init_reg};
if (address == {{PAD{1'h0}}, ADDR_STATUS})
api_rd_delay_new = {30'h0, valid_reg, ready_reg};
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 6810307..9c2fa50 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -52,6 +52,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
input wire init,
input wire next,
+ input wire read,
+ input wire write,
input wire encdec,
output wire ready,
diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 358b512..4b94b26 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -64,6 +64,8 @@ module tb_keywrap_core();
reg tb_reset_n;
reg tb_init;
reg tb_next;
+ reg tb_read;
+ reg tb_write;
reg tb_encdec;
wire tb_ready;
wire tb_valid;
@@ -98,7 +100,9 @@ module tb_keywrap_core();
.init(tb_init),
.next(tb_next),
- .encdec(tb_encdec),
+ .read(tb_read),
+ .write(tb_write),
+ .encdec(tb_encdec),
.ready(tb_ready),
.valid(tb_valid),
@@ -159,6 +163,8 @@ module tb_keywrap_core();
tb_init = 0;
tb_next = 0;
+ tb_read = 0;
+ tb_write = 0;
tb_encdec = 0;
tb_rlen = 13'h0;
tb_key = 256'h0;