diff options
| -rw-r--r-- | src/tb/tb_keywrap.v | 100 | ||||
| -rwxr-xr-x | toolruns/Makefile | 20 |
2 files changed, 117 insertions, 3 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v new file mode 100644 index 0000000..f42d58f --- /dev/null +++ b/src/tb/tb_keywrap.v @@ -0,0 +1,100 @@ +//====================================================================== +// +// tb_keywrap.v +// ------------ +// Testbench for the keywrap top level wrapper (and core). +// +// +// Author: Joachim Strombergson +// Copyright (c) 2018, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module tb_keywrap(); + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + integer cycle_ctr; + reg tb_sys_clk; + reg tb_reset_n; + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD; + tb_sys_clk = !tb_sys_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + cycle_ctr = cycle_ctr + 1; + + #(CLK_PERIOD); + end + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + initial + begin + cycle_ctr = 0; + tb_sys_clk = 0; + tb_reset_n = 0; + + #(CLK_PERIOD * 10); + + tb_reset_n = 1; + + #(CLK_PERIOD * 10); + $finish; + end + +endmodule // tb_keywrap + +//====================================================================== +// EOF tb_keywrap.v +//====================================================================== diff --git a/toolruns/Makefile b/toolruns/Makefile index 996e6e7..9b890ad 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -46,13 +46,20 @@ TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v +TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) +TB_TOP_SRC = ../src/tb/tb_keywrap.v + CC = iverilog CC_FLAGS = -Wall LINT = verilator LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME -all: core.sim mem.sim +all: top.sim core.sim mem.sim + + +top.sim: $(TB_TOP_SRC) $(TOP_SRC) + $(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) core.sim: $(TB_CORE_SRC) $(CORE_SRC) @@ -63,6 +70,10 @@ mem.sim: $(TB_MEM_SRC) $(MEM_SRC) $(CC) $(CC_FLAGS) -o mem.sim $(TB_MEM_SRC) $(MEM_SRC) +sim-top: top.sim + ./top.sim + + sim-core: core.sim ./core.sim @@ -71,11 +82,12 @@ sim-mem: mem.sim ./mem.sim -lint: $(CORE_SRC) - $(LINT) $(LINT_FLAGS) $(CORE_SRC) +lint: $(TOP_SRC) + $(LINT) $(LINT_FLAGS) $(TOP_SRC) clean: + rm -f top.sim rm -f core.sim rm -f mem.sim @@ -85,7 +97,9 @@ help: @echo "------------------" @echo "all: Build all simulation targets." @echo "lint: Lint all rtl source files." + @echo "top.sim: Build top simulation target." @echo "core.sim: Build core simulation target." + @echo "sim-top: Run top simulation." @echo "sim-core: Run core simulation." @echo "mem.sim: Build mem simulation target." @echo "sim-mem: Run mem simulation." |