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-rw-r--r--src/tb/tb_keywrap.v140
1 files changed, 135 insertions, 5 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index f42d58f..29249ed 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -39,12 +39,73 @@
module tb_keywrap();
+ parameter DEBUG = 0;
+
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
- integer cycle_ctr;
- reg tb_sys_clk;
- reg tb_reset_n;
+ // API for the core.
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
+
+ localparam ADDR_RLEN = 8'h0c;
+ localparam ADDR_A_LSB = 8'h0e;
+ localparam ADDR_A_MSB = 8'h0f;
+
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_WRITE_DATA = 8'h20;
+
+ localparam ADDR_READ_DATA = 8'h30;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg [31 : 0] read_data;
+ reg [127 : 0] result_data;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_cs;
+ reg tb_we;
+ reg [7 : 0] tb_address;
+ reg [31 : 0] tb_write_data;
+ wire [31 : 0] tb_read_data;
+ wire tb_error;
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ keywrap dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+ .cs(tb_cs),
+ .we(tb_we),
+ .address(tb_address),
+ .write_data(tb_write_data),
+ .read_data(tb_read_data),
+ .error(tb_error)
+ );
//----------------------------------------------------------------
@@ -55,7 +116,7 @@ module tb_keywrap();
always
begin : clk_gen
#CLK_HALF_PERIOD;
- tb_sys_clk = !tb_sys_clk;
+ tb_clk = !tb_clk;
end // clk_gen
@@ -74,6 +135,75 @@ module tb_keywrap();
//----------------------------------------------------------------
+ // read_word()
+ //
+ // Read a data word from the given address in the DUT.
+ // the word read will be available in the global variable
+ // read_data.
+ //----------------------------------------------------------------
+ task read_word(input [11 : 0] address);
+ begin
+ tb_address = address;
+ tb_cs = 1;
+ tb_we = 0;
+ #(CLK_PERIOD);
+ read_data = tb_read_data;
+ tb_cs = 0;
+
+ if (DEBUG)
+ begin
+ $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
+ $display("");
+ end
+ end
+ endtask // read_word
+
+
+ //----------------------------------------------------------------
+ // write_word()
+ //
+ // Write the given word to the DUT using the DUT interface.
+ //----------------------------------------------------------------
+ task write_word(input [11 : 0] address,
+ input [31 : 0] word);
+ begin
+ if (DEBUG)
+ begin
+ $display("*** Writing 0x%08x to 0x%02x.", word, address);
+ $display("");
+ end
+
+ tb_address = address;
+ tb_write_data = word;
+ tb_cs = 1;
+ tb_we = 1;
+ #(2 * CLK_PERIOD);
+ tb_cs = 0;
+ tb_we = 0;
+ end
+ endtask // write_word
+
+
+ //----------------------------------------------------------------
+ // wait_ready
+ //
+ // Wait for the DUT to signal that the result is ready
+ //----------------------------------------------------------------
+ task wait_ready;
+ begin : wait_ready
+ reg rdy;
+ rdy = 1'b0;
+
+ while (rdy != 1'b1)
+ begin
+ read_word(ADDR_STATUS);
+ rdy = tb_read_data[STATUS_READY_BIT];
+ end
+ end
+ endtask // wait_ready
+
+
+ //----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
@@ -82,7 +212,7 @@ module tb_keywrap();
initial
begin
cycle_ctr = 0;
- tb_sys_clk = 0;
+ tb_clk = 0;
tb_reset_n = 0;
#(CLK_PERIOD * 10);