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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-08-24 10:44:10 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-08-24 10:44:10 +0200
commit860dc811015211ac41a33275d974434c323f7422 (patch)
tree847d0d714dbc56f256d63d08e7a183a79f4c3020 /toolruns/Makefile
parent378cce57f387d42aa7bf90d28fb3b1f5559248b2 (diff)
Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.
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