Adding more infrastructure needed for the integrated mkm.

1 files changed, 19 insertions, 6 deletions

diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 9ae1e75..9f9b329 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -64,6 +64,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
                      input wire [255 : 0]             key,
                      input wire                       keylen,
                      output wire [255 : 0]            read_key,
+                     output wire [31 : 0]             mkm_status,
 
                      input wire  [63 : 0]             a_init,
                      output wire [63 : 0]             a_result,
@@ -144,8 +145,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
   reg          iteration_ctr_set;
   reg          iteration_ctr_rst;
 
-  reg [31 : 0] core_key [0 : 7];
-  reg          core_key_we;
+  reg [31 : 0] mkm_key [0 : 7];
+  reg          mkm_key_we;
 
   reg [2 : 0]  mkm_word_ctr_reg;
   reg [2 : 0]  mkm_word_ctr_new;
@@ -155,6 +156,10 @@ module keywrap_core #(parameter MEM_BITS = 11)
   reg [7 : 0]  mkm_addr_new;
   reg          mkm_addr_we;
 
+  reg [31 : 0]  mkm_status_reg;
+  reg [31 : 0]  mkm_status_new;
+  reg           mkm_status_we;
+
   reg [4 : 0]  keywrap_core_ctrl_reg;
   reg [4 : 0]  keywrap_core_ctrl_new;
   reg          keywrap_core_ctrl_we;
@@ -242,9 +247,10 @@ module keywrap_core #(parameter MEM_BITS = 11)
   //----------------------------------------------------------------
   // Assignments for ports.
   //----------------------------------------------------------------
-  assign a_result = a_reg;
-  assign ready    = ready_reg;
-  assign valid    = valid_reg;
+  assign a_result   = a_reg;
+  assign ready      = ready_reg;
+  assign valid      = valid_reg;
+  assign mkm_status = mkm_status_reg;
 
 
   //----------------------------------------------------------------
@@ -257,7 +263,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
       if (!reset_n)
         begin
           for (i = 0 ; i < 8 ; i = i + 1)
-            core_key[i] <= 32'h0;
+            mkm_key[i] <= 32'h0;
 
           a_reg                 <= 64'h0;
           ready_reg             <= 1'h1;
@@ -266,6 +272,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
           iteration_ctr_reg     <= 3'h0;
           mkm_word_ctr_reg      <= 3'h0;
           mkm_addr_reg          <= 8'h0;
+          mkm_status_reg        <= 32'h0;
           keywrap_core_ctrl_reg <= CTRL_IDLE;
        end
 
@@ -274,6 +281,9 @@ module keywrap_core #(parameter MEM_BITS = 11)
           if (a_we)
             a_reg <= a_new;
 
+          if (mkm_status_we)
+            mkm_status_reg <= mkm_read_data;
+
           if (ready_we)
             ready_reg <= ready_new;
 
@@ -428,6 +438,9 @@ module keywrap_core #(parameter MEM_BITS = 11)
       mkm_we                = 1'h0;
       mkm_address           = 8'h0;
       mkm_write_data        = 32'h0;
+      mkm_word_ctr_we       = 1'h0;
+      mkm_status_we         = 1'h0;
+
       keywrap_core_ctrl_new = CTRL_IDLE;
       keywrap_core_ctrl_we  = 1'h0;