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authorJoachim StroĢˆmbergson <joachim@secworks.se>2019-01-11 15:35:00 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2019-01-11 15:35:00 +0100
commitdddf34910bae2763cfab6aee9e27a91457b39bf8 (patch)
treee13f8a9e703c16247ab64d01a2b33cf26f9fb333 /src/tb
parent3455dd0940bb09e2f08c7951d3b10f415251af80 (diff)
Adding test case that verifies that SW can keep a key alive by reading status register.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_keywrap.v80
1 files changed, 52 insertions, 28 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index 75e01e3..ef266ab 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -1259,7 +1259,7 @@ module tb_keywrap();
$display("Status of timeout counter: 0x%04x",
dut.core.key_timeout_ctr_reg);
// Display contents in key expansion register 2 again.
- $display("Contents in key_mem[2] after init: 0x%016x",
+ $display("Contents in key_mem[2] after timeout: 0x%016x",
dut.core.aes.keymem.key_mem[2]);
if (dut.core.aes.keymem.key_mem[2] != 128'h62636363626363636263636362636363)
@@ -1305,16 +1305,6 @@ module tb_keywrap();
read_word(ADDR_STATUS);
$display("Status register: 0x%032b", read_data);
- // Set the key timeout to 256 cycles.
- write_word(ADDR_TIMEOUT, 32'hdeadbeef);
- read_word(ADDR_TIMEOUT);
- if (read_data != 32'hdeadbeef)
- $display("Error. Timout value = 0x%04x, expected 0xdeadbeef", read_data);
-
- // Display contents in key expansion register 2.
- $display("Contents of the key_mem[2] before init: 0x%016x",
- dut.core.aes.keymem.key_mem[2]);
-
// Initialize the AES engine (to expand the key).
// Wait for init to complete.
// Note, not actually needed to wait. We can write R data during init.
@@ -1332,7 +1322,12 @@ module tb_keywrap();
read_word(ADDR_STATUS);
$display("Status register: 0b%032b", read_data);
+ // Set the key timeout to 256 cycles.
+ $display("Setting timout to 16 cycles and then we keep it alive.");
+ write_word(ADDR_TIMEOUT, 32'h00000010);
+
// Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
$display("Contents of timeout counter: 0x%04x",
dut.core.key_timeout_ctr_reg);
#(2 * CLK_PERIOD);
@@ -1344,33 +1339,61 @@ module tb_keywrap();
#(2 * CLK_PERIOD);
$display("Contents of timeout counter: 0x%04x",
dut.core.key_timeout_ctr_reg);
- #(2 * CLK_PERIOD);
-
read_word(ADDR_STATUS);
$display("Status register: 0x%032b", read_data);
- // Display contents in one of the key expansion registers
- $display("Contents of the key_mem[2]: 0x%016x",
- dut.core.aes.keymem.key_mem[2]);
- // Display contents in one of the key expansion registers
- $display("Contents of the key_mem[2]: 0x%016x",
- dut.core.aes.keymem.key_mem[2]);
- // Display contents in one of the key expansion registers
+ // Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
$display("Contents of the key_mem[2]: 0x%016x",
dut.core.aes.keymem.key_mem[2]);
- #(40 * CLK_PERIOD);
-
- // Set the key timeout to 16 cycles.
- // Read status to perform ping.
- write_word(ADDR_TIMEOUT, 32'h00000010);
+ // Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
read_word(ADDR_STATUS);
- #(400 * CLK_PERIOD);
+ $display("Status register: 0x%032b", read_data);
+ $display("We now allow the timer to expire");
+ #(40 * CLK_PERIOD);
read_word(ADDR_STATUS);
$display("Status register: 0x%032b", read_data);
-
+ $display("Contents of the key_mem[2]: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
$display("** TC test_zeroise2 END.\n");
end
@@ -1508,8 +1531,9 @@ module tb_keywrap();
// test_big_wrap_256();
+ reset_dut();
test_zeroise1();
-// test_zeroise2();
+ test_zeroise2();
// test_zeroise3();
display_test_results();